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authorAlex Frid <afrid@nvidia.com>2018-08-28 21:13:28 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-30 23:17:10 -0400
commita6108a4b0ed52c7a8fa58d9815d0b373be8305bf (patch)
treeb30a7635132b8d48fa8b1b7e31844a9ce5cfd778
parent9c60230b5723d6a0dbb83bf85d499a671491245f (diff)
gpu: nvgpu: Fix GM20b GPCPLL debugfs node
GM20B GPCPLL registers are accessed via sys address space with the exception of the last dvfs2 register that can be accessed only through bcast address. However, in debugfs loop dvfs2 sys address should be used as loop terminator; otherwise, loop body is never executed, and GPCPLL registers debugfs node is broken. Fixed it in this commit. Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808784 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c3
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.h1
-rw-r--r--drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c6
3 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 93bae921..2ba677b0 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -1655,7 +1655,8 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g,
1655 d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); 1655 d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r();
1656 d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); 1656 d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r());
1657 d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); 1657 d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r();
1658 d->trim_sys_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); 1658 d->trim_sys_gpcpll_dvfs2_reg = trim_sys_gpcpll_dvfs2_r();
1659 d->trim_bcast_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r();
1659 1660
1660 reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); 1661 reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
1661 d->trim_sys_gpcpll_cfg_val = reg; 1662 d->trim_sys_gpcpll_cfg_val = reg;
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
index e814ac70..c93d4ee3 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
@@ -41,6 +41,7 @@ struct nvgpu_clk_pll_debug_data {
41 41
42 u32 trim_sys_gpcpll_cfg_reg; 42 u32 trim_sys_gpcpll_cfg_reg;
43 u32 trim_sys_gpcpll_dvfs2_reg; 43 u32 trim_sys_gpcpll_dvfs2_reg;
44 u32 trim_bcast_gpcpll_dvfs2_reg;
44 45
45 u32 trim_sys_gpcpll_cfg_val; 46 u32 trim_sys_gpcpll_cfg_val;
46 bool trim_sys_gpcpll_cfg_enabled; 47 bool trim_sys_gpcpll_cfg_enabled;
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c b/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c
index f514d2c8..52eea83f 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c
@@ -108,10 +108,14 @@ static int pll_reg_raw_show(struct seq_file *s, void *data)
108 108
109 seq_puts(s, "GPCPLL REGISTERS:\n"); 109 seq_puts(s, "GPCPLL REGISTERS:\n");
110 for (reg = d.trim_sys_gpcpll_cfg_reg; 110 for (reg = d.trim_sys_gpcpll_cfg_reg;
111 reg <= d.trim_sys_gpcpll_dvfs2_reg; 111 reg < d.trim_sys_gpcpll_dvfs2_reg;
112 reg += sizeof(u32)) 112 reg += sizeof(u32))
113 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); 113 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
114 114
115 reg = d.trim_bcast_gpcpll_dvfs2_reg;
116 if (reg)
117 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
118
115 seq_puts(s, "\nGPC CLK OUT REGISTERS:\n"); 119 seq_puts(s, "\nGPC CLK OUT REGISTERS:\n");
116 120
117 seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg, 121 seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg,