gpu: nvgpu: Reorg regops HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
regops sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I7e2ccf158a8e7efa453a3326e86146660f18926f
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

9 files changed, 160 insertions, 162 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 407a442a..c2bccbee 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -277,6 +277,29 @@ static const struct gpu_ops gm20b_ops = {
                 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
                 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
         },
+        .regops = {
+                .get_global_whitelist_ranges =
+                        gm20b_get_global_whitelist_ranges,
+                .get_global_whitelist_ranges_count =
+                        gm20b_get_global_whitelist_ranges_count,
+                .get_context_whitelist_ranges =
+                        gm20b_get_context_whitelist_ranges,
+                .get_context_whitelist_ranges_count =
+                        gm20b_get_context_whitelist_ranges_count,
+                .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
+                .get_runcontrol_whitelist_count =
+                        gm20b_get_runcontrol_whitelist_count,
+                .get_runcontrol_whitelist_ranges =
+                        gm20b_get_runcontrol_whitelist_ranges,
+                .get_runcontrol_whitelist_ranges_count =
+                        gm20b_get_runcontrol_whitelist_ranges_count,
+                .get_qctl_whitelist = gm20b_get_qctl_whitelist,
+                .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
+                .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
+                .get_qctl_whitelist_ranges_count =
+                        gm20b_get_qctl_whitelist_ranges_count,
+                .apply_smpc_war = gm20b_apply_smpc_war,
+        },
         .mc = {
                 .intr_enable = mc_gk20a_intr_enable,
                 .intr_unit_config = mc_gk20a_intr_unit_config,
@@ -350,6 +373,7 @@ int gm20b_init_hal(struct gk20a *g)
         gops->fifo = gm20b_ops.fifo;
         gops->gr_ctx = gm20b_ops.gr_ctx;
         gops->therm = gm20b_ops.therm;
+        gops->regops = gm20b_ops.regops;
         gops->mc = gm20b_ops.mc;
         gops->dbg_session_ops = gm20b_ops.dbg_session_ops;
         gops->debug = gm20b_ops.debug;
@@ -404,7 +428,6 @@ int gm20b_init_hal(struct gk20a *g)
         gm20b_init_mm(gops);
         gm20b_init_pmu_ops(g);
         gm20b_init_clk_ops(gops);
-        gm20b_init_regops(gops);
 
         g->name = "gm20b";
 
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index 45e7ec3d..1e5f6bfd 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -377,105 +377,68 @@ static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = {
 static const u32 gm20b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gm20b_qctl_whitelist_ranges);
 
-static const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
+const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
 {
         return gm20b_global_whitelist_ranges;
 }
 
-static int gm20b_get_global_whitelist_ranges_count(void)
+int gm20b_get_global_whitelist_ranges_count(void)
 {
         return gm20b_global_whitelist_ranges_count;
 }
 
-static const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void)
+const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void)
 {
         return gm20b_context_whitelist_ranges;
 }
 
-static int gm20b_get_context_whitelist_ranges_count(void)
+int gm20b_get_context_whitelist_ranges_count(void)
 {
         return gm20b_context_whitelist_ranges_count;
 }
 
-static const u32 *gm20b_get_runcontrol_whitelist(void)
+const u32 *gm20b_get_runcontrol_whitelist(void)
 {
         return gm20b_runcontrol_whitelist;
 }
 
-static int gm20b_get_runcontrol_whitelist_count(void)
+int gm20b_get_runcontrol_whitelist_count(void)
 {
         return gm20b_runcontrol_whitelist_count;
 }
 
-static const
-struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void)
+const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void)
 {
         return gm20b_runcontrol_whitelist_ranges;
 }
 
-static int gm20b_get_runcontrol_whitelist_ranges_count(void)
+int gm20b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gm20b_runcontrol_whitelist_ranges_count;
 }
 
-static const u32 *gm20b_get_qctl_whitelist(void)
+const u32 *gm20b_get_qctl_whitelist(void)
 {
         return gm20b_qctl_whitelist;
 }
 
-static int gm20b_get_qctl_whitelist_count(void)
+int gm20b_get_qctl_whitelist_count(void)
 {
         return gm20b_qctl_whitelist_count;
 }
 
-static const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void)
+const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void)
 {
         return gm20b_qctl_whitelist_ranges;
 }
 
-static int gm20b_get_qctl_whitelist_ranges_count(void)
+int gm20b_get_qctl_whitelist_ranges_count(void)
 {
         return gm20b_qctl_whitelist_ranges_count;
 }
 
-static int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
 {
         /* Not needed on gm20b */
         return 0;
 }
-
-void gm20b_init_regops(struct gpu_ops *gops)
-{
-        gops->regops.get_global_whitelist_ranges =
-                gm20b_get_global_whitelist_ranges;
-        gops->regops.get_global_whitelist_ranges_count =
-                gm20b_get_global_whitelist_ranges_count;
-
-        gops->regops.get_context_whitelist_ranges =
-                gm20b_get_context_whitelist_ranges;
-        gops->regops.get_context_whitelist_ranges_count =
-                gm20b_get_context_whitelist_ranges_count;
-
-        gops->regops.get_runcontrol_whitelist =
-                gm20b_get_runcontrol_whitelist;
-        gops->regops.get_runcontrol_whitelist_count =
-                gm20b_get_runcontrol_whitelist_count;
-
-        gops->regops.get_runcontrol_whitelist_ranges =
-                gm20b_get_runcontrol_whitelist_ranges;
-        gops->regops.get_runcontrol_whitelist_ranges_count =
-                gm20b_get_runcontrol_whitelist_ranges_count;
-
-        gops->regops.get_qctl_whitelist =
-                gm20b_get_qctl_whitelist;
-        gops->regops.get_qctl_whitelist_count =
-                gm20b_get_qctl_whitelist_count;
-
-        gops->regops.get_qctl_whitelist_ranges =
-                gm20b_get_qctl_whitelist_ranges;
-        gops->regops.get_qctl_whitelist_ranges_count =
-                gm20b_get_qctl_whitelist_ranges_count;
-
-        gops->regops.apply_smpc_war =
-                gm20b_apply_smpc_war;
-}
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
index f613668b..4a40184b 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,6 +19,20 @@
 #ifndef __REGOPS_GM20B_H_
 #define __REGOPS_GM20B_H_
 
-void gm20b_init_regops(struct gpu_ops *gops);
+struct dbg_session_gk20a;
+
+const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void);
+int gm20b_get_global_whitelist_ranges_count(void);
+const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void);
+int gm20b_get_context_whitelist_ranges_count(void);
+const u32 *gm20b_get_runcontrol_whitelist(void);
+int gm20b_get_runcontrol_whitelist_count(void);
+const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void);
+int gm20b_get_runcontrol_whitelist_ranges_count(void);
+const u32 *gm20b_get_qctl_whitelist(void);
+int gm20b_get_qctl_whitelist_count(void);
+const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void);
+int gm20b_get_qctl_whitelist_ranges_count(void);
+int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GM20B_H_ */
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 8077c5e1..0caf890f 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -353,6 +353,29 @@ static const struct gpu_ops gp106_ops = {
                 .get_internal_sensor_limits = gp106_get_internal_sensor_limits,
                 .configure_therm_alert = gp106_configure_therm_alert,
         },
+        .regops = {
+                .get_global_whitelist_ranges =
+                        gp106_get_global_whitelist_ranges,
+                .get_global_whitelist_ranges_count =
+                        gp106_get_global_whitelist_ranges_count,
+                .get_context_whitelist_ranges =
+                        gp106_get_context_whitelist_ranges,
+                .get_context_whitelist_ranges_count =
+                        gp106_get_context_whitelist_ranges_count,
+                .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist,
+                .get_runcontrol_whitelist_count =
+                        gp106_get_runcontrol_whitelist_count,
+                .get_runcontrol_whitelist_ranges =
+                        gp106_get_runcontrol_whitelist_ranges,
+                .get_runcontrol_whitelist_ranges_count =
+                        gp106_get_runcontrol_whitelist_ranges_count,
+                .get_qctl_whitelist = gp106_get_qctl_whitelist,
+                .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count,
+                .get_qctl_whitelist_ranges = gp106_get_qctl_whitelist_ranges,
+                .get_qctl_whitelist_ranges_count =
+                        gp106_get_qctl_whitelist_ranges_count,
+                .apply_smpc_war = gp106_apply_smpc_war,
+        },
         .mc = {
                 .intr_enable = mc_gp10b_intr_enable,
                 .intr_unit_config = mc_gp10b_intr_unit_config,
@@ -447,6 +470,7 @@ int gp106_init_hal(struct gk20a *g)
         gops->fecs_trace = gp106_ops.fecs_trace;
         gops->pramin = gp106_ops.pramin;
         gops->therm = gp106_ops.therm;
+        gops->regops = gp106_ops.regops;
         gops->mc = gp106_ops.mc;
         gops->debug = gp106_ops.debug;
         gops->dbg_session_ops = gp106_ops.dbg_session_ops;
@@ -477,7 +501,6 @@ int gp106_init_hal(struct gk20a *g)
         gp106_init_pmu_ops(g);
         gp106_init_clk_ops(gops);
         gp106_init_clk_arb_ops(gops);
-        gp106_init_regops(gops);
 
         g->name = "gp10x";
 
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c
index a165c426..f734ef49 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GP106 GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1708,105 +1708,68 @@ static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = {
 static const u32 gp106_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp106_qctl_whitelist_ranges);
 
-static const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
+const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
 {
         return gp106_global_whitelist_ranges;
 }
 
-static int gp106_get_global_whitelist_ranges_count(void)
+int gp106_get_global_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
 
-static const struct regop_offset_range *gp106_get_context_whitelist_ranges(void)
+const struct regop_offset_range *gp106_get_context_whitelist_ranges(void)
 {
         return gp106_global_whitelist_ranges;
 }
 
-static int gp106_get_context_whitelist_ranges_count(void)
+int gp106_get_context_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
 
-static const u32 *gp106_get_runcontrol_whitelist(void)
+const u32 *gp106_get_runcontrol_whitelist(void)
 {
         return gp106_runcontrol_whitelist;
 }
 
-static int gp106_get_runcontrol_whitelist_count(void)
+int gp106_get_runcontrol_whitelist_count(void)
 {
         return gp106_runcontrol_whitelist_count;
 }
 
-static const
-struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
+const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
 {
         return gp106_runcontrol_whitelist_ranges;
 }
 
-static int gp106_get_runcontrol_whitelist_ranges_count(void)
+int gp106_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp106_runcontrol_whitelist_ranges_count;
 }
 
-static const u32 *gp106_get_qctl_whitelist(void)
+const u32 *gp106_get_qctl_whitelist(void)
 {
         return gp106_qctl_whitelist;
 }
 
-static int gp106_get_qctl_whitelist_count(void)
+int gp106_get_qctl_whitelist_count(void)
 {
         return gp106_qctl_whitelist_count;
 }
 
-static const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
+const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
 {
         return gp106_qctl_whitelist_ranges;
 }
 
-static int gp106_get_qctl_whitelist_ranges_count(void)
+int gp106_get_qctl_whitelist_ranges_count(void)
 {
         return gp106_qctl_whitelist_ranges_count;
 }
 
-static int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
 {
         /* Not needed on gp106 */
         return 0;
 }
-
-void gp106_init_regops(struct gpu_ops *gops)
-{
-        gops->regops.get_global_whitelist_ranges =
-                gp106_get_global_whitelist_ranges;
-        gops->regops.get_global_whitelist_ranges_count =
-                gp106_get_global_whitelist_ranges_count;
-
-        gops->regops.get_context_whitelist_ranges =
-                gp106_get_context_whitelist_ranges;
-        gops->regops.get_context_whitelist_ranges_count =
-                gp106_get_context_whitelist_ranges_count;
-
-        gops->regops.get_runcontrol_whitelist =
-                gp106_get_runcontrol_whitelist;
-        gops->regops.get_runcontrol_whitelist_count =
-                gp106_get_runcontrol_whitelist_count;
-
-        gops->regops.get_runcontrol_whitelist_ranges =
-                gp106_get_runcontrol_whitelist_ranges;
-        gops->regops.get_runcontrol_whitelist_ranges_count =
-                gp106_get_runcontrol_whitelist_ranges_count;
-
-        gops->regops.get_qctl_whitelist =
-                gp106_get_qctl_whitelist;
-        gops->regops.get_qctl_whitelist_count =
-                gp106_get_qctl_whitelist_count;
-
-        gops->regops.get_qctl_whitelist_ranges =
-                gp106_get_qctl_whitelist_ranges;
-        gops->regops.get_qctl_whitelist_ranges_count =
-                gp106_get_qctl_whitelist_ranges_count;
-
-        gops->regops.apply_smpc_war =
-                gp106_apply_smpc_war;
-}
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.h b/drivers/gpu/nvgpu/gp106/regops_gp106.h
index 7f6b6861..271adcbf 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.h
@@ -2,7 +2,7 @@
  *
  * Tegra GP106 GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,6 +19,18 @@
 #ifndef __REGOPS_GP106_H_
 #define __REGOPS_GP106_H_
 
-void gp106_init_regops(struct gpu_ops *gops);
+const struct regop_offset_range *gp106_get_global_whitelist_ranges(void);
+int gp106_get_global_whitelist_ranges_count(void);
+const struct regop_offset_range *gp106_get_context_whitelist_ranges(void);
+int gp106_get_context_whitelist_ranges_count(void);
+const u32 *gp106_get_runcontrol_whitelist(void);
+int gp106_get_runcontrol_whitelist_count(void);
+const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void);
+int gp106_get_runcontrol_whitelist_ranges_count(void);
+const u32 *gp106_get_qctl_whitelist(void);
+int gp106_get_qctl_whitelist_count(void);
+const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void);
+int gp106_get_qctl_whitelist_ranges_count(void);
+int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GP106_H_ */
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a2aacd2e..e2479530 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -313,6 +313,29 @@ static const struct gpu_ops gp10b_ops = {
                 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
                 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
         },
+        .regops = {
+                .get_global_whitelist_ranges =
+                        gp10b_get_global_whitelist_ranges,
+                .get_global_whitelist_ranges_count =
+                        gp10b_get_global_whitelist_ranges_count,
+                .get_context_whitelist_ranges =
+                        gp10b_get_context_whitelist_ranges,
+                .get_context_whitelist_ranges_count =
+                        gp10b_get_context_whitelist_ranges_count,
+                .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
+                .get_runcontrol_whitelist_count =
+                        gp10b_get_runcontrol_whitelist_count,
+                .get_runcontrol_whitelist_ranges =
+                        gp10b_get_runcontrol_whitelist_ranges,
+                .get_runcontrol_whitelist_ranges_count =
+                        gp10b_get_runcontrol_whitelist_ranges_count,
+                .get_qctl_whitelist = gp10b_get_qctl_whitelist,
+                .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
+                .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
+                .get_qctl_whitelist_ranges_count =
+                        gp10b_get_qctl_whitelist_ranges_count,
+                .apply_smpc_war = gp10b_apply_smpc_war,
+        },
         .mc = {
                 .intr_enable = mc_gp10b_intr_enable,
                 .intr_unit_config = mc_gp10b_intr_unit_config,
@@ -390,6 +413,7 @@ int gp10b_init_hal(struct gk20a *g)
         gops->fecs_trace = gp10b_ops.fecs_trace;
         gops->pramin = gp10b_ops.pramin;
         gops->therm = gp10b_ops.therm;
+        gops->regops = gp10b_ops.regops;
         gops->mc = gp10b_ops.mc;
         gops->debug = gp10b_ops.debug;
         gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
@@ -452,7 +476,6 @@ int gp10b_init_hal(struct gk20a *g)
         gp10b_init_fb(gops);
         gp10b_init_mm(gops);
         gp10b_init_pmu_ops(g);
-        gp10b_init_regops(gops);
 
         g->name = "gp10b";
 
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
index 885221df..f90ecaa6 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -406,105 +406,68 @@ static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
 static const u32 gp10b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
 
-static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
+const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
 {
         return gp10b_global_whitelist_ranges;
 }
 
-static int gp10b_get_global_whitelist_ranges_count(void)
+int gp10b_get_global_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
 
-static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
+const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
 {
         return gp10b_global_whitelist_ranges;
 }
 
-static int gp10b_get_context_whitelist_ranges_count(void)
+int gp10b_get_context_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
 
-static const u32 *gp10b_get_runcontrol_whitelist(void)
+const u32 *gp10b_get_runcontrol_whitelist(void)
 {
         return gp10b_runcontrol_whitelist;
 }
 
-static int gp10b_get_runcontrol_whitelist_count(void)
+int gp10b_get_runcontrol_whitelist_count(void)
 {
         return gp10b_runcontrol_whitelist_count;
 }
 
-static const
-struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
+const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
 {
         return gp10b_runcontrol_whitelist_ranges;
 }
 
-static int gp10b_get_runcontrol_whitelist_ranges_count(void)
+int gp10b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp10b_runcontrol_whitelist_ranges_count;
 }
 
-static const u32 *gp10b_get_qctl_whitelist(void)
+const u32 *gp10b_get_qctl_whitelist(void)
 {
         return gp10b_qctl_whitelist;
 }
 
-static int gp10b_get_qctl_whitelist_count(void)
+int gp10b_get_qctl_whitelist_count(void)
 {
         return gp10b_qctl_whitelist_count;
 }
 
-static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
+const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
 {
         return gp10b_qctl_whitelist_ranges;
 }
 
-static int gp10b_get_qctl_whitelist_ranges_count(void)
+int gp10b_get_qctl_whitelist_ranges_count(void)
 {
         return gp10b_qctl_whitelist_ranges_count;
 }
 
-static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
 {
         /* Not needed on gp10b */
         return 0;
 }
-
-void gp10b_init_regops(struct gpu_ops *gops)
-{
-        gops->regops.get_global_whitelist_ranges =
-                gp10b_get_global_whitelist_ranges;
-        gops->regops.get_global_whitelist_ranges_count =
-                gp10b_get_global_whitelist_ranges_count;
-
-        gops->regops.get_context_whitelist_ranges =
-                gp10b_get_context_whitelist_ranges;
-        gops->regops.get_context_whitelist_ranges_count =
-                gp10b_get_context_whitelist_ranges_count;
-
-        gops->regops.get_runcontrol_whitelist =
-                gp10b_get_runcontrol_whitelist;
-        gops->regops.get_runcontrol_whitelist_count =
-                gp10b_get_runcontrol_whitelist_count;
-
-        gops->regops.get_runcontrol_whitelist_ranges =
-                gp10b_get_runcontrol_whitelist_ranges;
-        gops->regops.get_runcontrol_whitelist_ranges_count =
-                gp10b_get_runcontrol_whitelist_ranges_count;
-
-        gops->regops.get_qctl_whitelist =
-                gp10b_get_qctl_whitelist;
-        gops->regops.get_qctl_whitelist_count =
-                gp10b_get_qctl_whitelist_count;
-
-        gops->regops.get_qctl_whitelist_ranges =
-                gp10b_get_qctl_whitelist_ranges;
-        gops->regops.get_qctl_whitelist_ranges_count =
-                gp10b_get_qctl_whitelist_ranges_count;
-
-        gops->regops.apply_smpc_war =
-                gp10b_apply_smpc_war;
-}
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
index 8727951a..524a42c8 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GP10B GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,6 +19,20 @@
 #ifndef __REGOPS_GP10B_H_
 #define __REGOPS_GP10B_H_
 
-void gp10b_init_regops(struct gpu_ops *gops);
+struct dbg_session_gk20a;
+
+const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
+int gp10b_get_global_whitelist_ranges_count(void);
+const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
+int gp10b_get_context_whitelist_ranges_count(void);
+const u32 *gp10b_get_runcontrol_whitelist(void);
+int gp10b_get_runcontrol_whitelist_count(void);
+const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
+int gp10b_get_runcontrol_whitelist_ranges_count(void);
+const u32 *gp10b_get_qctl_whitelist(void);
+int gp10b_get_qctl_whitelist_count(void);
+const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
+int gp10b_get_qctl_whitelist_ranges_count(void);
+int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GP10B_H_ */