gpu: nvgpu: Remove separation of t18x code

Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.

Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

28 files changed, 212 insertions, 393 deletions

diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig
index 7a9a99c6..cab717bb 100644
--- a/drivers/gpu/nvgpu/Kconfig
+++ b/drivers/gpu/nvgpu/Kconfig
@@ -115,8 +115,7 @@ config TEGRA_USE_NA_GPCPLL
 config GK20A_PCI
         bool "Support PCIe NVIDIA GPUs on nvgpu"
         depends on PCI && GK20A
-        default y if ARCH_TEGRA_18x_SOC
-        default n
+        default y
         help
           Enable support for GPUs on PCIe bus.
 
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index f8253e41..72946fc0 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -177,7 +177,6 @@ nvgpu-$(CONFIG_GK20A_DEVFREQ) += \
 nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \
         gk20a/css_gr_gk20a.o
 
-ifeq ($(CONFIG_ARCH_TEGRA_18x_SOC),y)
 nvgpu-y += \
         gp10b/gr_gp10b.o  \
         gp10b/gr_ctx_gp10b.o  \
@@ -249,7 +248,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
         common/linux/vgpu/gp10b/vgpu_hal_gp10b.o  \
         common/linux/vgpu/gp10b/vgpu_gr_gp10b.o  \
         common/linux/vgpu/gp10b/vgpu_mm_gp10b.o
-endif
 
 ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y)
 nvgpu-y += \
diff --git a/drivers/gpu/nvgpu/common/linux/debug.c b/drivers/gpu/nvgpu/common/linux/debug.c
index 7a4e4e9f..fb07df5b 100644
--- a/drivers/gpu/nvgpu/common/linux/debug.c
+++ b/drivers/gpu/nvgpu/common/linux/debug.c
@@ -364,23 +364,20 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
                                         S_IRUGO|S_IWUSR,
                                         l->debugfs,
                                         &g->runlist_interleave);
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         l->debugfs_force_preemption_gfxp =
                 debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR,
                 l->debugfs,
-                &g->gr.t18x.ctx_vars.force_preemption_gfxp);
+                &g->gr.ctx_vars.force_preemption_gfxp);
 
         l->debugfs_force_preemption_cilp =
                 debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR,
                 l->debugfs,
-                &g->gr.t18x.ctx_vars.force_preemption_cilp);
+                &g->gr.ctx_vars.force_preemption_cilp);
 
         l->debugfs_dump_ctxsw_stats =
                 debugfs_create_bool("dump_ctxsw_stats_on_channel_close",
                         S_IRUGO|S_IWUSR, l->debugfs,
-                        &g->gr.t18x.
-                                ctx_vars.dump_ctxsw_stats_on_channel_close);
-#endif
+                        &g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close);
 
         gr_gk20a_debugfs_init(g);
         gk20a_pmu_debugfs_init(g);
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 31651795..0ac50140 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -22,7 +22,6 @@
 #include <linux/dma-buf.h>
 #include <linux/poll.h>
 #include <uapi/linux/nvgpu.h>
-#include <uapi/linux/nvgpu-t18x.h>
 
 #include <nvgpu/semaphore.h>
 #include <nvgpu/timers.h>
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
index 2a91b87d..c28bdfdb 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
@@ -20,7 +20,6 @@
 #include <linux/anon_inodes.h>
 #include <linux/fs.h>
 #include <uapi/linux/nvgpu.h>
-#include <uapi/linux/nvgpu-t18x.h>
 
 #include <nvgpu/bitops.h>
 #include <nvgpu/kmem.h>
@@ -54,9 +53,7 @@
 struct gk20a_ctrl_priv {
         struct device *dev;
         struct gk20a *g;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         struct nvgpu_clk_session *clk_session;
-#endif
 };
 
 int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
@@ -95,9 +92,7 @@ int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
                 gk20a_idle(g);
         }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         err = nvgpu_clk_arb_init_session(g, &priv->clk_session);
-#endif
 free_ref:
         if (err)
                 gk20a_put(g);
@@ -110,10 +105,8 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp)
 
         gk20a_dbg_fn("");
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (priv->clk_session)
                 nvgpu_clk_arb_release_session(g, priv->clk_session);
-#endif
 
         gk20a_put(g);
         nvgpu_kfree(g, priv);
@@ -944,7 +937,6 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g,
         return err;
 }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
 static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
                 struct gk20a_ctrl_priv *priv,
                 struct nvgpu_gpu_clk_vf_points_args *args)
@@ -1402,7 +1394,6 @@ static int nvgpu_gpu_get_temperature(struct gk20a *g,
 
         return err;
 }
-#endif
 
 static int nvgpu_gpu_set_therm_alert_limit(struct gk20a *g,
                 struct nvgpu_gpu_set_therm_alert_limit_args *args)
@@ -1798,7 +1789,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
                         (struct nvgpu_gpu_get_memory_state_args *)buf);
                 break;
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         case NVGPU_GPU_IOCTL_CLK_GET_RANGE:
                 err = nvgpu_gpu_clk_get_range(g, priv,
                         (struct nvgpu_gpu_clk_range_args *)buf);
@@ -1843,7 +1833,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
                 err = nvgpu_gpu_get_temperature(g,
                         (struct nvgpu_gpu_get_temperature_args *)buf);
                 break;
-#endif
 
         case NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT:
                 err = nvgpu_gpu_set_therm_alert_limit(g,
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index 76b9d4db..796507a9 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -339,10 +339,8 @@ static struct of_device_id tegra_gk20a_of_match[] = {
 #ifdef CONFIG_TEGRA_GK20A
         { .compatible = "nvidia,tegra210-gm20b",
                 .data = &gm20b_tegra_platform },
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         { .compatible = "nvidia,tegra186-gp10b",
                 .data = &gp10b_tegra_platform },
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
         { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA,
                 .data = &t19x_gpu_tegra_platform },
@@ -1035,11 +1033,9 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g)
                 case GM20B_FUSE_OPT_TPC_DISABLE:
                         g->tpc_fs_mask_user = ~value;
                         break;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
                 case GP10B_FUSE_OPT_ECC_EN:
-                        g->gr.t18x.fecs_feature_override_ecc_val = value;
+                        g->gr.fecs_feature_override_ecc_val = value;
                         break;
-#endif
                 default:
                         nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
                         break;
@@ -1184,9 +1180,7 @@ int nvgpu_remove(struct device *dev, struct class *class)
         if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
                 gk20a_scale_exit(dev);
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         nvgpu_clk_arb_cleanup_arbiter(g);
-#endif
 
         gk20a_user_deinit(dev, class);
 
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
index b944844e..b42c3698 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
@@ -135,13 +135,13 @@ static int gp10b_tegra_probe(struct device *dev)
         platform->bypass_smmu = !device_is_iommuable(dev);
         platform->disable_bigpage = platform->bypass_smmu;
 
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
 
-        platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
-        platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
+        platform->g->gr.ctx_vars.force_preemption_gfxp = false;
+        platform->g->gr.ctx_vars.force_preemption_cilp = false;
 
         gp10b_tegra_get_clocks(dev);
         nvgpu_linux_init_clk_support(platform->g);
@@ -621,86 +621,86 @@ void gr_gp10b_create_sysfs(struct gk20a *g)
            initialized multiple times but we only need to create the ECC
            stats once. Therefore, add the following check to avoid
            creating duplicate stat sysfs nodes. */
-        if (g->ecc.gr.t18x.sm_lrf_single_err_count.counters != NULL)
+        if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL)
                 return;
 
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "sm_lrf_ecc_single_err_count",
-                                &g->ecc.gr.t18x.sm_lrf_single_err_count,
+                                &g->ecc.gr.sm_lrf_single_err_count,
                                 &dev_attr_sm_lrf_ecc_single_err_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "sm_lrf_ecc_double_err_count",
-                                &g->ecc.gr.t18x.sm_lrf_double_err_count,
+                                &g->ecc.gr.sm_lrf_double_err_count,
                                 &dev_attr_sm_lrf_ecc_double_err_count_array);
 
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "sm_shm_ecc_sec_count",
-                                &g->ecc.gr.t18x.sm_shm_sec_count,
+                                &g->ecc.gr.sm_shm_sec_count,
                                 &dev_attr_sm_shm_ecc_sec_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "sm_shm_ecc_sed_count",
-                                &g->ecc.gr.t18x.sm_shm_sed_count,
+                                &g->ecc.gr.sm_shm_sed_count,
                                 &dev_attr_sm_shm_ecc_sed_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "sm_shm_ecc_ded_count",
-                                &g->ecc.gr.t18x.sm_shm_ded_count,
+                                &g->ecc.gr.sm_shm_ded_count,
                                 &dev_attr_sm_shm_ecc_ded_count_array);
 
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_total_sec_pipe0_count",
-                                &g->ecc.gr.t18x.tex_total_sec_pipe0_count,
+                                &g->ecc.gr.tex_total_sec_pipe0_count,
                                 &dev_attr_tex_ecc_total_sec_pipe0_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_total_ded_pipe0_count",
-                                &g->ecc.gr.t18x.tex_total_ded_pipe0_count,
+                                &g->ecc.gr.tex_total_ded_pipe0_count,
                                 &dev_attr_tex_ecc_total_ded_pipe0_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_unique_sec_pipe0_count",
-                                &g->ecc.gr.t18x.tex_unique_sec_pipe0_count,
+                                &g->ecc.gr.tex_unique_sec_pipe0_count,
                                 &dev_attr_tex_ecc_unique_sec_pipe0_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_unique_ded_pipe0_count",
-                                &g->ecc.gr.t18x.tex_unique_ded_pipe0_count,
+                                &g->ecc.gr.tex_unique_ded_pipe0_count,
                                 &dev_attr_tex_ecc_unique_ded_pipe0_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_total_sec_pipe1_count",
-                                &g->ecc.gr.t18x.tex_total_sec_pipe1_count,
+                                &g->ecc.gr.tex_total_sec_pipe1_count,
                                 &dev_attr_tex_ecc_total_sec_pipe1_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_total_ded_pipe1_count",
-                                &g->ecc.gr.t18x.tex_total_ded_pipe1_count,
+                                &g->ecc.gr.tex_total_ded_pipe1_count,
                                 &dev_attr_tex_ecc_total_ded_pipe1_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_unique_sec_pipe1_count",
-                                &g->ecc.gr.t18x.tex_unique_sec_pipe1_count,
+                                &g->ecc.gr.tex_unique_sec_pipe1_count,
                                 &dev_attr_tex_ecc_unique_sec_pipe1_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 0,
                                 "tex_ecc_unique_ded_pipe1_count",
-                                &g->ecc.gr.t18x.tex_unique_ded_pipe1_count,
+                                &g->ecc.gr.tex_unique_ded_pipe1_count,
                                 &dev_attr_tex_ecc_unique_ded_pipe1_count_array);
 
         error |= gr_gp10b_ecc_stat_create(dev,
                                 1,
                                 "lts0_ecc_sec_count",
-                                &g->ecc.gr.t18x.l2_sec_count,
+                                &g->ecc.ltc.l2_sec_count,
                                 &dev_attr_l2_ecc_sec_count_array);
         error |= gr_gp10b_ecc_stat_create(dev,
                                 1,
                                 "lts0_ecc_ded_count",
-                                &g->ecc.gr.t18x.l2_ded_count,
+                                &g->ecc.ltc.l2_ded_count,
                                 &dev_attr_l2_ecc_ded_count_array);
 
         if (error)
@@ -713,65 +713,65 @@ static void gr_gp10b_remove_sysfs(struct device *dev)
 
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.sm_lrf_single_err_count,
+                        &g->ecc.gr.sm_lrf_single_err_count,
                         dev_attr_sm_lrf_ecc_single_err_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.sm_lrf_double_err_count,
+                        &g->ecc.gr.sm_lrf_double_err_count,
                         dev_attr_sm_lrf_ecc_double_err_count_array);
 
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.sm_shm_sec_count,
+                        &g->ecc.gr.sm_shm_sec_count,
                         dev_attr_sm_shm_ecc_sec_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.sm_shm_sed_count,
+                        &g->ecc.gr.sm_shm_sed_count,
                         dev_attr_sm_shm_ecc_sed_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.sm_shm_ded_count,
+                        &g->ecc.gr.sm_shm_ded_count,
                         dev_attr_sm_shm_ecc_ded_count_array);
 
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_total_sec_pipe0_count,
+                        &g->ecc.gr.tex_total_sec_pipe0_count,
                         dev_attr_tex_ecc_total_sec_pipe0_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_total_ded_pipe0_count,
+                        &g->ecc.gr.tex_total_ded_pipe0_count,
                         dev_attr_tex_ecc_total_ded_pipe0_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_unique_sec_pipe0_count,
+                        &g->ecc.gr.tex_unique_sec_pipe0_count,
                         dev_attr_tex_ecc_unique_sec_pipe0_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_unique_ded_pipe0_count,
+                        &g->ecc.gr.tex_unique_ded_pipe0_count,
                         dev_attr_tex_ecc_unique_ded_pipe0_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_total_sec_pipe1_count,
+                        &g->ecc.gr.tex_total_sec_pipe1_count,
                         dev_attr_tex_ecc_total_sec_pipe1_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_total_ded_pipe1_count,
+                        &g->ecc.gr.tex_total_ded_pipe1_count,
                         dev_attr_tex_ecc_total_ded_pipe1_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_unique_sec_pipe1_count,
+                        &g->ecc.gr.tex_unique_sec_pipe1_count,
                         dev_attr_tex_ecc_unique_sec_pipe1_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         0,
-                        &g->ecc.gr.t18x.tex_unique_ded_pipe1_count,
+                        &g->ecc.gr.tex_unique_ded_pipe1_count,
                         dev_attr_tex_ecc_unique_ded_pipe1_count_array);
 
         gr_gp10b_ecc_stat_remove(dev,
                         1,
-                        &g->ecc.gr.t18x.l2_sec_count,
+                        &g->ecc.ltc.l2_sec_count,
                         dev_attr_l2_ecc_sec_count_array);
         gr_gp10b_ecc_stat_remove(dev,
                         1,
-                        &g->ecc.gr.t18x.l2_ded_count,
+                        &g->ecc.ltc.l2_ded_count,
                         dev_attr_l2_ecc_ded_count_array);
 }
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
index efc9c595..fe85e113 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -21,6 +21,7 @@
 #include "common/linux/vgpu/vgpu.h"
 #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
 
+#include "gp10b/gr_gp10b.h"
 #include "vgpu_gr_gp10b.h"
 
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
@@ -45,10 +46,10 @@ void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
 
         __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel);
 
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
 
         nvgpu_kfree(g, gr_ctx);
 }
@@ -122,11 +123,11 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
         int err = 0;
 
         if (g->ops.gr.is_valid_gfx_class(g, class) &&
-                        g->gr.t18x.ctx_vars.force_preemption_gfxp)
+                        g->gr.ctx_vars.force_preemption_gfxp)
                 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
 
         if (g->ops.gr.is_valid_compute_class(g, class) &&
-                        g->gr.t18x.ctx_vars.force_preemption_cilp)
+                        g->gr.ctx_vars.force_preemption_cilp)
                 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
 
         /* check for invalid combinations */
@@ -157,54 +158,54 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
                 attrib_cb_size = ALIGN(attrib_cb_size, 128);
 
                 gk20a_dbg_info("gfxp context preempt size=%d",
-                        g->gr.t18x.ctx_vars.preempt_image_size);
+                        g->gr.ctx_vars.preempt_image_size);
                 gk20a_dbg_info("gfxp context spill size=%d", spill_size);
                 gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size);
                 gk20a_dbg_info("gfxp context attrib cb size=%d",
                         attrib_cb_size);
 
                 err = gr_gp10b_alloc_buffer(vm,
-                                        g->gr.t18x.ctx_vars.preempt_image_size,
-                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
+                                        g->gr.ctx_vars.preempt_image_size,
+                                        &gr_ctx->preempt_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
                 }
-                desc = &gr_ctx->t18x.preempt_ctxsw_buffer;
+                desc = &gr_ctx->preempt_ctxsw_buffer;
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         spill_size,
-                                        &gr_ctx->t18x.spill_ctxsw_buffer);
+                                        &gr_ctx->spill_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
                 }
-                desc = &gr_ctx->t18x.spill_ctxsw_buffer;
+                desc = &gr_ctx->spill_ctxsw_buffer;
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         pagepool_size,
-                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                                        &gr_ctx->pagepool_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
                 }
-                desc = &gr_ctx->t18x.pagepool_ctxsw_buffer;
+                desc = &gr_ctx->pagepool_ctxsw_buffer;
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
                         desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         attrib_cb_size,
-                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
+                                        &gr_ctx->betacb_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
                 }
-                desc = &gr_ctx->t18x.betacb_ctxsw_buffer;
+                desc = &gr_ctx->betacb_ctxsw_buffer;
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
                         desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
@@ -323,9 +324,9 @@ int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
         if (err)
                 return err;
 
-        g->gr.t18x.ctx_vars.preempt_image_size =
+        g->gr.ctx_vars.preempt_image_size =
                         priv->constants.preempt_ctx_size;
-        if (!g->gr.t18x.ctx_vars.preempt_image_size)
+        if (!g->gr.ctx_vars.preempt_image_size)
                 return -EINVAL;
 
         return 0;
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index da4ca10c..6806b318 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -40,6 +40,7 @@
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fb_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
+#include "gp10b/gr_gp10b.h"
 #include "gp10b/gr_ctx_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/gp10b_gating_reglist.h"
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
index 6b5a1b0d..a7491b20 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -48,6 +48,7 @@
 #include <gp10b/mm_gp10b.h>
 #include <gp10b/mc_gp10b.h>
 #include <gp10b/ce_gp10b.h>
+#include "gp10b/gr_gp10b.h"
 #include <gp10b/fifo_gp10b.h>
 #include <gp10b/therm_gp10b.h>
 #include <gp10b/priv_ring_gp10b.h>
diff --git a/drivers/gpu/nvgpu/ecc_t18x.h b/drivers/gpu/nvgpu/ecc_t18x.h
deleted file mode 100644
index e1644fd1..00000000
--- a/drivers/gpu/nvgpu/ecc_t18x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * NVIDIA T18x ECC
- *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef _NVGPU_ECC_T18X_H_
-#define _NVGPU_ECC_T18X_H_
-
-#include "gp10b/ecc_gp10b.h"
-
-#endif
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
index f04ff56c..0d1ed5df 100644
--- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -32,9 +32,6 @@ struct gk20a_ecc_stat {
 #endif
 };
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-#include "ecc_t18x.h"
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "ecc_t19x.h"
 #endif
@@ -42,15 +39,30 @@ struct gk20a_ecc_stat {
 struct ecc_gk20a {
         /* Stats per engine */
         struct {
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-                struct ecc_gr_t18x t18x;
-#endif
+                struct gk20a_ecc_stat sm_lrf_single_err_count;
+                struct gk20a_ecc_stat sm_lrf_double_err_count;
+
+                struct gk20a_ecc_stat sm_shm_sec_count;
+                struct gk20a_ecc_stat sm_shm_sed_count;
+                struct gk20a_ecc_stat sm_shm_ded_count;
+
+                struct gk20a_ecc_stat tex_total_sec_pipe0_count;
+                struct gk20a_ecc_stat tex_total_ded_pipe0_count;
+                struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
+                struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
+                struct gk20a_ecc_stat tex_total_sec_pipe1_count;
+                struct gk20a_ecc_stat tex_total_ded_pipe1_count;
+                struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
+                struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
+
 #ifdef CONFIG_TEGRA_19x_GPU
                 struct ecc_gr_t19x t19x;
 #endif
         } gr;
 
         struct {
+                struct gk20a_ecc_stat l2_sec_count;
+                struct gk20a_ecc_stat l2_ded_count;
 #ifdef CONFIG_TEGRA_19x_GPU
                 struct ecc_ltc_t19x t19x;
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 5bdd81ac..c029e9e0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -46,9 +46,7 @@
 #include "mc_gk20a.h"
 #include "hal.h"
 #include "bus_gk20a.h"
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "pstate/pstate.h"
-#endif
 
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "nvgpu_gpuid_t19x.h"
@@ -112,10 +110,9 @@ int gk20a_prepare_poweroff(struct gk20a *g)
         if (g->ops.clk.suspend_clk_support)
                 ret |= g->ops.clk.suspend_clk_support(g);
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE))
                 gk20a_deinit_pstate_support(g);
-#endif
+
         g->power_on = false;
 
         return ret;
@@ -240,7 +237,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
                 err = gk20a_init_pstate_support(g);
                 if (err) {
@@ -248,7 +244,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                         goto done;
                 }
         }
-#endif
 
         if (g->ops.pmu.is_pmu_supported(g)) {
                 err = nvgpu_init_pmu_support(g);
@@ -264,7 +259,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 goto done;
         }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
                 err = gk20a_init_pstate_pmu_support(g);
                 if (err) {
@@ -278,7 +272,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 nvgpu_err(g, "failed to init clk arb");
                 goto done;
         }
-#endif
 
         err = gk20a_init_therm_support(g);
         if (err) {
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fef9f498..8d8bfbec 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -72,12 +72,10 @@ struct nvgpu_ctxsw_trace_filter;
 #include "pmu_gk20a.h"
 #include "priv_ring_gk20a.h"
 #include "therm_gk20a.h"
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
 #include "therm/thrm.h"
-#endif
 #include "ecc_gk20a.h"
 
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
@@ -1128,12 +1126,10 @@ struct gk20a {
         struct nvgpu_pmu pmu;
         struct acr_desc acr;
         struct ecc_gk20a ecc;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         struct clk_pmupstate clk_pmu;
         struct perf_pmupstate perf_pmu;
         struct pmgr_pmupstate pmgr_pmu;
         struct therm_pmupstate therm_pmu;
-#endif
 
 #ifdef CONFIG_DEBUG_FS
         struct railgate_stats pstats;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index f44e96a7..0df88988 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -24,9 +24,6 @@
 #ifndef GR_GK20A_H
 #define GR_GK20A_H
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-#include "gr_t18x.h"
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "gr_t19x.h"
 #endif
@@ -316,6 +313,11 @@ struct gr_gk20a {
                 } ctxsw_regs;
                 int regs_base_index;
                 bool valid;
+
+                u32 preempt_image_size;
+                bool force_preemption_gfxp;
+                bool force_preemption_cilp;
+                bool dump_ctxsw_stats_on_channel_close;
         } ctx_vars;
 
         struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */
@@ -409,9 +411,11 @@ struct gr_gk20a {
         bool sw_ready;
         bool skip_ucode_init;
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-        struct gr_t18x t18x;
-#endif
+        struct nvgpu_preemption_modes_rec preemption_mode_rec;
+
+        u32 fecs_feature_override_ecc_val;
+
+        int cilp_preempt_pending_chid;
 
         u32 fbp_en_mask;
         u32 *fbp_rop_l2_en_mask;
@@ -433,9 +437,15 @@ struct gr_ctx_desc {
         u32 graphics_preempt_mode;
         u32 compute_preempt_mode;
         bool boosted_ctx;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-        struct gr_ctx_desc_t18x t18x;
-#endif
+
+        struct nvgpu_mem preempt_ctxsw_buffer;
+        struct nvgpu_mem spill_ctxsw_buffer;
+        struct nvgpu_mem betacb_ctxsw_buffer;
+        struct nvgpu_mem pagepool_ctxsw_buffer;
+        u32 ctx_id;
+        bool ctx_id_valid;
+        bool cilp_preempt_pending;
+
 #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
         u64 virt_ctx;
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index 13e6f374..d24d4bc5 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -44,7 +44,6 @@ int gpu_init_hal(struct gk20a *g)
                 if (gm20b_init_hal(g))
                         return -ENODEV;
                 break;
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
         case NVGPU_GPUID_GP10B:
                 if (gp10b_init_hal(g))
                         return -ENODEV;
@@ -54,7 +53,6 @@ int gpu_init_hal(struct gk20a *g)
                 if (gp106_init_hal(g))
                         return -ENODEV;
                 break;
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
         case TEGRA_19x_GPUID:
                 if (TEGRA_19x_GPUID_HAL(g))
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index d8478b2d..4e3eeb51 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -589,12 +589,10 @@ int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu,
 
         switch (msg->msg_type) {
         case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION:
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
                 if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1))
                         nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu),
                                 (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD));
                 else
-#endif
                         gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d",
                                 msg->hw_slct_msg.mask);
                 break;
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index fea337e7..bed08fed 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -140,11 +140,11 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
 {
         int err = 0;
 
-        if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp)
+        if (class == PASCAL_B && g->gr.ctx_vars.force_preemption_gfxp)
                 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
 
         if (class == PASCAL_COMPUTE_B &&
-                        g->gr.t18x.ctx_vars.force_preemption_cilp)
+                        g->gr.ctx_vars.force_preemption_cilp)
                 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
 
         /* check for invalid combinations */
@@ -178,8 +178,8 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
                                 attrib_cb_size);
 
                 err = gr_gp10b_alloc_buffer(vm,
-                                        g->gr.t18x.ctx_vars.preempt_image_size,
-                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
+                                        g->gr.ctx_vars.preempt_image_size,
+                                        &gr_ctx->preempt_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate preempt buffer");
                         goto fail;
@@ -187,7 +187,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         spill_size,
-                                        &gr_ctx->t18x.spill_ctxsw_buffer);
+                                        &gr_ctx->spill_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate spill buffer");
                         goto fail_free_preempt;
@@ -195,7 +195,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         attrib_cb_size,
-                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
+                                        &gr_ctx->betacb_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate beta buffer");
                         goto fail_free_spill;
@@ -203,7 +203,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         pagepool_size,
-                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                                        &gr_ctx->pagepool_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate page pool");
                         goto fail_free_betacb;
@@ -236,11 +236,11 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
         return 0;
 
 fail_free_betacb:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
 fail_free_spill:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
 fail_free_preempt:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
 fail:
         return err;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
deleted file mode 100644
index a4a6e35b..00000000
--- a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * GP10B ECC
- *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _NVGPU_ECC_GP10B_H_
-#define _NVGPU_ECC_GP10B_H_
-
-struct gk20a_ecc_stat;
-
-struct ecc_gr_t18x {
-        struct gk20a_ecc_stat sm_lrf_single_err_count;
-        struct gk20a_ecc_stat sm_lrf_double_err_count;
-
-        struct gk20a_ecc_stat sm_shm_sec_count;
-        struct gk20a_ecc_stat sm_shm_sed_count;
-        struct gk20a_ecc_stat sm_shm_ded_count;
-
-        struct gk20a_ecc_stat tex_total_sec_pipe0_count;
-        struct gk20a_ecc_stat tex_total_ded_pipe0_count;
-        struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
-        struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
-        struct gk20a_ecc_stat tex_total_sec_pipe1_count;
-        struct gk20a_ecc_stat tex_total_ded_pipe1_count;
-        struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
-        struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
-
-        struct gk20a_ecc_stat l2_sec_count;
-        struct gk20a_ecc_stat l2_ded_count;
-};
-#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 6ff1522b..f0b77ebd 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -180,7 +180,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g,
                                                 lrf_ecc_ded_status,
                                                 &lrf_single_count_delta,
                                                 lrf_double_count_delta);
-                g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_single_err_count.counters[tpc] +=
                                                         lrf_single_count_delta;
         }
         if (lrf_ecc_ded_status) {
@@ -192,7 +192,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g,
                                                 lrf_ecc_ded_status,
                                                 &lrf_double_count_delta,
                                                 lrf_single_count_delta);
-                g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_double_err_count.counters[tpc] +=
                                                         lrf_double_count_delta;
         }
         gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
@@ -217,9 +217,9 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g,
                 ecc_stats_reg_val =
                         gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
-                g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] +=
+                g->ecc.gr.sm_shm_sec_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
-                g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] +=
+                g->ecc.gr.sm_shm_sed_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
                                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
@@ -239,7 +239,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g,
                 ecc_stats_reg_val =
                         gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
-                g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] +=
+                g->ecc.gr.sm_shm_ded_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
                 gk20a_writel(g,
@@ -280,7 +280,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] +=
+                g->ecc.gr.tex_total_sec_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
                 gk20a_writel(g,
@@ -289,7 +289,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] +=
+                g->ecc.gr.tex_unique_sec_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
                 gk20a_writel(g,
@@ -304,7 +304,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] +=
+                g->ecc.gr.tex_total_sec_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
                 gk20a_writel(g,
@@ -313,7 +313,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] +=
+                g->ecc.gr.tex_unique_sec_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
                 gk20a_writel(g,
@@ -336,7 +336,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] +=
+                g->ecc.gr.tex_total_ded_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
                 gk20a_writel(g,
@@ -345,7 +345,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] +=
+                g->ecc.gr.tex_unique_ded_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
                 gk20a_writel(g,
@@ -360,7 +360,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] +=
+                g->ecc.gr.tex_total_ded_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
                 gk20a_writel(g,
@@ -369,7 +369,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] +=
+                g->ecc.gr.tex_unique_ded_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
                 gk20a_writel(g,
@@ -881,10 +881,10 @@ int gr_gp10b_init_ctx_state(struct gk20a *g)
         if (err)
                 return err;
 
-        if (!g->gr.t18x.ctx_vars.preempt_image_size) {
+        if (!g->gr.ctx_vars.preempt_image_size) {
                 op.method.addr =
                         gr_fecs_method_push_adr_discover_preemption_image_size_v();
-                op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size;
+                op.mailbox.ret = &g->gr.ctx_vars.preempt_image_size;
                 err = gr_gk20a_submit_fecs_method_op(g, op, false);
                 if (err) {
                         nvgpu_err(g, "query preempt image size failed");
@@ -893,7 +893,7 @@ int gr_gp10b_init_ctx_state(struct gk20a *g)
         }
 
         gk20a_dbg_info("preempt image size: %u",
-                g->gr.t18x.ctx_vars.preempt_image_size);
+                g->gr.ctx_vars.preempt_image_size);
 
         gk20a_dbg_fn("done");
 
@@ -940,11 +940,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
         int err = 0;
 
         if (g->ops.gr.is_valid_gfx_class(g, class) &&
-                                g->gr.t18x.ctx_vars.force_preemption_gfxp)
+                                g->gr.ctx_vars.force_preemption_gfxp)
                 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
 
         if (g->ops.gr.is_valid_compute_class(g, class) &&
-                        g->gr.t18x.ctx_vars.force_preemption_cilp)
+                        g->gr.ctx_vars.force_preemption_cilp)
                 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
 
         /* check for invalid combinations */
@@ -987,8 +987,8 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
                                 attrib_cb_size);
 
                 err = gr_gp10b_alloc_buffer(vm,
-                                        g->gr.t18x.ctx_vars.preempt_image_size,
-                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
+                                        g->gr.ctx_vars.preempt_image_size,
+                                        &gr_ctx->preempt_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate preempt buffer");
                         goto fail;
@@ -996,7 +996,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         spill_size,
-                                        &gr_ctx->t18x.spill_ctxsw_buffer);
+                                        &gr_ctx->spill_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate spill buffer");
                         goto fail_free_preempt;
@@ -1004,7 +1004,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         attrib_cb_size,
-                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
+                                        &gr_ctx->betacb_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate beta buffer");
                         goto fail_free_spill;
@@ -1012,7 +1012,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
 
                 err = gr_gp10b_alloc_buffer(vm,
                                         pagepool_size,
-                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                                        &gr_ctx->pagepool_ctxsw_buffer);
                 if (err) {
                         nvgpu_err(g, "cannot allocate page pool");
                         goto fail_free_betacb;
@@ -1046,11 +1046,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
         return 0;
 
 fail_free_betacb:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
 fail_free_spill:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
 fail_free_preempt:
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
 fail:
         return err;
 }
@@ -1070,7 +1070,7 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
         if (err)
                 return err;
 
-        (*gr_ctx)->t18x.ctx_id_valid = false;
+        (*gr_ctx)->ctx_id_valid = false;
 
         if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP)
                 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
@@ -1160,13 +1160,13 @@ void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
         if (!gr_ctx)
                 return;
 
-        if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close)
+        if (g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close)
                 dump_ctx_switch_stats(g, vm, gr_ctx);
 
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
-        nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
         gr_gk20a_free_gr_ctx(g, vm, gr_ctx);
         gk20a_dbg_fn("done");
 }
@@ -1211,7 +1211,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
                                 cta_preempt_option);
         }
 
-        if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) {
+        if (gr_ctx->preempt_ctxsw_buffer.gpu_va) {
                 u32 addr;
                 u32 size;
                 u32 cbes_reserve;
@@ -1219,10 +1219,10 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
                 if (g->ops.gr.set_preemption_buffer_va) {
                         if (ctxheader->gpu_va)
                                 g->ops.gr.set_preemption_buffer_va(g, ctxheader,
-                                gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va);
+                                gr_ctx->preempt_ctxsw_buffer.gpu_va);
                         else
                                 g->ops.gr.set_preemption_buffer_va(g, mem,
-                                gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va);
+                                gr_ctx->preempt_ctxsw_buffer.gpu_va);
                 }
 
                 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true);
@@ -1231,30 +1231,30 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
                         goto out;
                 }
 
-                addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >>
+                addr = (u64_lo32(gr_ctx->betacb_ctxsw_buffer.gpu_va) >>
                         gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) |
-                        (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) <<
+                        (u64_hi32(gr_ctx->betacb_ctxsw_buffer.gpu_va) <<
                          (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
 
                 gk20a_dbg_info("attrib cb addr : 0x%016x", addr);
                 g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true);
 
-                addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >>
+                addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >>
                         gr_scc_pagepool_base_addr_39_8_align_bits_v()) |
-                        (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) <<
+                        (u64_hi32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) <<
                          (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v()));
-                size = gr_ctx->t18x.pagepool_ctxsw_buffer.size;
+                size = gr_ctx->pagepool_ctxsw_buffer.size;
 
                 if (size == g->ops.gr.pagepool_default_size(g))
                         size = gr_scc_pagepool_total_pages_hwmax_v();
 
                 g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true);
 
-                addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >>
+                addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >>
                         gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) |
-                        (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) <<
+                        (u64_hi32(gr_ctx->spill_ctxsw_buffer.gpu_va) <<
                          (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
-                size = gr_ctx->t18x.spill_ctxsw_buffer.size /
+                size = gr_ctx->spill_ctxsw_buffer.size /
                         gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
 
                 gr_gk20a_ctx_patch_write(g, ch_ctx,
@@ -1489,8 +1489,8 @@ void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
         struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
         int attrBufferSize;
 
-        if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
-                attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size;
+        if (gr_ctx->preempt_ctxsw_buffer.gpu_va)
+                attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size;
         else
                 attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
 
@@ -1606,10 +1606,10 @@ int gr_gp10b_init_fs_state(struct gk20a *g)
                          gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
         gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
 
-        if (g->gr.t18x.fecs_feature_override_ecc_val != 0) {
+        if (g->gr.fecs_feature_override_ecc_val != 0) {
                 gk20a_writel(g,
                         gr_fecs_feature_override_ecc_r(),
-                        g->gr.t18x.fecs_feature_override_ecc_val);
+                        g->gr.fecs_feature_override_ecc_val);
         }
 
         return gr_gm20b_init_fs_state(g);
@@ -1718,7 +1718,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
         if (!gr_ctx)
                 return -EINVAL;
 
-        if (gr_ctx->t18x.cilp_preempt_pending) {
+        if (gr_ctx->cilp_preempt_pending) {
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
                                 "CILP is already pending for chid %d",
                                 fault_ch->chid);
@@ -1726,24 +1726,24 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
         }
 
         /* get ctx_id from the ucode image */
-        if (!gr_ctx->t18x.ctx_id_valid) {
+        if (!gr_ctx->ctx_id_valid) {
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
                                 "CILP: looking up ctx id");
-                ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id);
+                ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->ctx_id);
                 if (ret) {
                         nvgpu_err(g, "CILP: error looking up ctx id!");
                         return ret;
                 }
-                gr_ctx->t18x.ctx_id_valid = true;
+                gr_ctx->ctx_id_valid = true;
         }
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
-                        "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id);
+                        "CILP: ctx id is 0x%x", gr_ctx->ctx_id);
 
         /* send ucode method to set ctxsw interrupt */
         ret = gr_gk20a_submit_fecs_sideband_method_op(g,
                         (struct fecs_method_op_gk20a) {
-                        .method.data = gr_ctx->t18x.ctx_id,
+                        .method.data = gr_ctx->ctx_id,
                         .method.addr =
                         gr_fecs_method_push_adr_configure_interrupt_completion_option_v(),
                         .mailbox = {
@@ -1773,8 +1773,8 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
         }
 
         /* set cilp_preempt_pending = true and record the channel */
-        gr_ctx->t18x.cilp_preempt_pending = true;
-        g->gr.t18x.cilp_preempt_pending_chid = fault_ch->chid;
+        gr_ctx->cilp_preempt_pending = true;
+        g->gr.cilp_preempt_pending_chid = fault_ch->chid;
 
         if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
                 struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
@@ -1801,15 +1801,15 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g,
 
         /* The ucode is self-clearing, so all we need to do here is
            to clear cilp_preempt_pending. */
-        if (!gr_ctx->t18x.cilp_preempt_pending) {
+        if (!gr_ctx->cilp_preempt_pending) {
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
                                 "CILP is already cleared for chid %d\n",
                                 fault_ch->chid);
                 return 0;
         }
 
-        gr_ctx->t18x.cilp_preempt_pending = false;
-        g->gr.t18x.cilp_preempt_pending_chid = -1;
+        gr_ctx->cilp_preempt_pending = false;
+        g->gr.cilp_preempt_pending_chid = -1;
 
         return 0;
 }
@@ -1925,7 +1925,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid)
         int chid;
         int ret = -EINVAL;
 
-        chid = g->gr.t18x.cilp_preempt_pending_chid;
+        chid = g->gr.cilp_preempt_pending_chid;
 
         ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid));
         if (!ch)
@@ -1933,7 +1933,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid)
 
         gr_ctx = ch->ch_ctx.gr_ctx;
 
-        if (gr_ctx->t18x.cilp_preempt_pending) {
+        if (gr_ctx->cilp_preempt_pending) {
                 *__chid = chid;
                 ret = 0;
         }
@@ -2121,7 +2121,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
                 nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
                                    NVGPU_TIMER_CPU_TIMER);
                 do {
-                        if (!gr_ctx->t18x.cilp_preempt_pending)
+                        if (!gr_ctx->cilp_preempt_pending)
                                 break;
 
                         nvgpu_usleep_range(delay, delay * 2);
@@ -2129,7 +2129,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
                 } while (!nvgpu_timeout_expired(&timeout));
 
                 /* If cilp is still pending at this point, timeout */
-                if (gr_ctx->t18x.cilp_preempt_pending)
+                if (gr_ctx->cilp_preempt_pending)
                         err = -ETIMEDOUT;
         }
 
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 45ac5305..55117022 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -145,27 +145,4 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
 void gr_gp10b_init_czf_bypass(struct gk20a *g);
 void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem);
 
-struct gr_t18x {
-        struct {
-                u32 preempt_image_size;
-                bool force_preemption_gfxp;
-                bool force_preemption_cilp;
-                bool dump_ctxsw_stats_on_channel_close;
-        } ctx_vars;
-
-        u32 fecs_feature_override_ecc_val;
-
-        int cilp_preempt_pending_chid;
-};
-
-struct gr_ctx_desc_t18x {
-        struct nvgpu_mem preempt_ctxsw_buffer;
-        struct nvgpu_mem spill_ctxsw_buffer;
-        struct nvgpu_mem betacb_ctxsw_buffer;
-        struct nvgpu_mem pagepool_ctxsw_buffer;
-        u32 ctx_id;
-        bool ctx_id_valid;
-        bool cilp_preempt_pending;
-};
-
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index 92a899b8..6e8a53c5 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -155,7 +155,7 @@ void gp10b_ltc_isr(struct gk20a *g)
                                 ecc_stats_reg_val =
                                         gk20a_readl(g,
                                                 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
-                                g->ecc.gr.t18x.l2_sec_count.counters[ltc] +=
+                                g->ecc.ltc.l2_sec_count.counters[ltc] +=
                                         ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
                                 ecc_stats_reg_val &=
                                         ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
@@ -175,7 +175,7 @@ void gp10b_ltc_isr(struct gk20a *g)
                                 ecc_stats_reg_val =
                                         gk20a_readl(g,
                                                 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
-                                g->ecc.gr.t18x.l2_ded_count.counters[ltc] +=
+                                g->ecc.ltc.l2_ded_count.counters[ltc] +=
                                         ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
                                 ecc_stats_reg_val &=
                                         ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
diff --git a/drivers/gpu/nvgpu/gr_t18x.h b/drivers/gpu/nvgpu/gr_t18x.h
deleted file mode 100644
index 23ec54f2..00000000
--- a/drivers/gpu/nvgpu/gr_t18x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * NVIDIA T18x GR
- *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef _NVGPU_GR_T18X_H_
-#define _NVGPU_GR_T18X_H_
-
-#include "gp10b/gr_gp10b.h"
-
-#endif
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 68ac8f51..9e43941d 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -280,7 +280,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 lrf_corrected_err_count_delta +=
                         (is_lrf_ecc_corrected_total_err_overflow <<
                          gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s());
-                g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_single_err_count.counters[tpc] +=
                                                         lrf_corrected_err_count_delta;
                 gk20a_writel(g,
                         gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset,
@@ -295,7 +295,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 lrf_uncorrected_err_count_delta +=
                         (is_lrf_ecc_uncorrected_total_err_overflow <<
                          gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s());
-                g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_double_err_count.counters[tpc] +=
                                                         lrf_uncorrected_err_count_delta;
                 gk20a_writel(g,
                         gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset,
@@ -1664,8 +1664,8 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
         struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
         int attrBufferSize;
 
-        if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
-                attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size;
+        if (gr_ctx->preempt_ctxsw_buffer.gpu_va)
+                attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size;
         else
                 attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
 
@@ -2385,10 +2385,10 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
                          gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
         gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
 
-        if (g->gr.t18x.fecs_feature_override_ecc_val != 0) {
+        if (g->gr.fecs_feature_override_ecc_val != 0) {
                 gk20a_writel(g,
                         gr_fecs_feature_override_ecc_r(),
-                        g->gr.t18x.fecs_feature_override_ecc_val);
+                        g->gr.fecs_feature_override_ecc_val);
         }
 
         return gr_gm20b_init_fs_state(g);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index b6ba231e..1941f239 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -46,6 +46,8 @@ struct zbc_query_params;
 struct channel_ctx_gk20a;
 struct nvgpu_warpstate;
 struct nvgpu_gr_sm_error_state;
+struct gr_gk20a_isr_data;
+struct gk20a_debug_output;
 
 enum {
         VOLTA_CHANNEL_GPFIFO_A  = 0xC36F,
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
index 95d82254..723e2e80 100644
--- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
@@ -81,13 +81,13 @@ static int gv11b_tegra_probe(struct device *dev)
         platform->bypass_smmu = !device_is_iommuable(dev);
         platform->disable_bigpage = platform->bypass_smmu;
 
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
 
-        platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
-        platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
+        platform->g->gr.ctx_vars.force_preemption_gfxp = false;
+        platform->g->gr.ctx_vars.force_preemption_cilp = false;
 
         gp10b_tegra_get_clocks(dev);
         nvgpu_linux_init_clk_support(platform->g);
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h
deleted file mode 100644
index 59db77c7..00000000
--- a/include/uapi/linux/nvgpu-t18x.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * NVGPU Public Interface Header
- *
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-/* This file is meant to extend nvgpu.h, not replace it
- * as such, be sure that nvgpu.h is actually the file performing the
- * inclusion, to the extent that's possible.
- */
-#ifndef _UAPI__LINUX_NVGPU_IOCTL_H
-#    error "This file is to be included within nvgpu.h only."
-#endif
-
-#ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
-#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
-
-/*
- * this flag is used in struct nvgpu_alloc_gpfifo_args
- * to enable re-playable faults for that channel
- */
-#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE   (1 << 2)
-
-/* Flags in nvgpu_alloc_obj_ctx_args.flags */
-#define NVGPU_ALLOC_OBJ_FLAGS_GFXP              (1 << 1)
-#define NVGPU_ALLOC_OBJ_FLAGS_CILP              (1 << 2)
-
-/* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */
-#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP     (1 << 1)
-/* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */
-#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP      (1 << 2)
-
-/* SM LRF ECC is enabled */
-#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
-/* SM SHM ECC is enabled */
-#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM      (1ULL << 61)
-/* TEX ECC is enabled */
-#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX         (1ULL << 62)
-/* L2 ECC is enabled */
-#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC         (1ULL << 63)
-/* All types of ECC are enabled */
-#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
-                                (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF |   \
-                                NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM |    \
-                                NVGPU_GPU_FLAGS_ECC_ENABLED_TEX    |    \
-                                NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
-
-/* Channel event_id in nvgpu_channel_events_ctrl_ext_args */
-#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED    3
-#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE   4
-
-#endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index bf711ef8..95da072c 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -94,10 +94,6 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_IMPL_GP106    0x00000006
 #define NVGPU_GPU_IMPL_GP10B    0x0000000B
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-#include <linux/nvgpu-t18x.h>
-#endif
-
 #ifdef CONFIG_TEGRA_19x_GPU
 #include <linux/nvgpu-t19x.h>
 #endif
@@ -150,6 +146,20 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL    (1ULL << 23)
 /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
 #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS      (1ULL << 24)
+/* SM LRF ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
+/* SM SHM ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM      (1ULL << 61)
+/* TEX ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX         (1ULL << 62)
+/* L2 ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC         (1ULL << 63)
+/* All types of ECC are enabled */
+#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
+                                (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF |   \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_TEX    |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
 
 struct nvgpu_gpu_characteristics {
         __u32 arch;
@@ -1388,6 +1398,9 @@ struct nvgpu_set_nvmap_fd_args {
 } __packed;
 
 #define NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO    (1 << 0)
+/* Flags in nvgpu_alloc_obj_ctx_args.flags */
+#define NVGPU_ALLOC_OBJ_FLAGS_GFXP              (1 << 1)
+#define NVGPU_ALLOC_OBJ_FLAGS_CILP              (1 << 2)
 
 struct nvgpu_alloc_obj_ctx_args {
         __u32 class_num; /* kepler3d, 2d, compute, etc       */
@@ -1398,6 +1411,11 @@ struct nvgpu_alloc_obj_ctx_args {
 struct nvgpu_alloc_gpfifo_args {
         __u32 num_entries;
 #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED    (1 << 0) /* set owner channel of this gpfifo as a vpr channel */
+/*
+ * this flag is used in struct nvgpu_alloc_gpfifo_args
+ * to enable re-playable faults for that channel
+ */
+#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE   (1 << 2)
         __u32 flags;
 };
 
@@ -1592,6 +1610,8 @@ struct nvgpu_event_id_ctrl_args {
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT            0
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE          1
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC      2
+#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED    3
+#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE   4
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN  5
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX                6
 
@@ -1600,11 +1620,14 @@ struct nvgpu_event_id_ctrl_args {
 struct nvgpu_preemption_mode_args {
 /* only one should be enabled at a time */
 #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI              (1 << 0)
+#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP             (1 << 1)
         __u32 graphics_preempt_mode; /* in */
 
 /* only one should be enabled at a time */
 #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI               (1 << 0)
 #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA               (1 << 1)
+#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP              (1 << 2)
+
         __u32 compute_preempt_mode; /* in */
 };