gpu: nvgpu: Move therm HAL to common

Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.

Bump gk20a code to gm20b.

JIRA NVGPU-955

Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

27 files changed, 261 insertions, 271 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 8c289947..4ca4b6d8 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -37,7 +37,12 @@ nvgpu-y += common/bus/bus_gk20a.o \
         common/fb/fb_gp106.o \
         common/fb/fb_gv11b.o \
         common/fb/fb_gv100.o \
-        common/xve/xve_gp106.o
+        common/xve/xve_gp106.o \
+        common/therm/therm.o \
+        common/therm/therm_gm20b.o \
+        common/therm/therm_gp10b.o \
+        common/therm/therm_gp106.o \
+        common/therm/therm_gv11b.o
 
 # Linux specific parts of nvgpu.
 nvgpu-y += \
@@ -204,7 +209,6 @@ nvgpu-y += \
         gk20a/pmu_gk20a.o \
         gk20a/flcn_gk20a.o \
         gk20a/fence_gk20a.o \
-        gk20a/therm_gk20a.o \
         gk20a/gr_ctx_gk20a_sim.o \
         gk20a/gr_ctx_gk20a.o \
         gk20a/hal.o \
@@ -221,7 +225,6 @@ nvgpu-y += \
         gm20b/pmu_gm20b.o \
         gm20b/mm_gm20b.o \
         gm20b/regops_gm20b.o \
-        gm20b/therm_gm20b.o \
         gm20b/fuse_gm20b.o \
         boardobj/boardobj.o \
         boardobj/boardobjgrp.o \
@@ -268,7 +271,6 @@ nvgpu-y += \
         gp10b/pmu_gp10b.o \
         gp10b/hal_gp10b.o \
         gp10b/regops_gp10b.o \
-        gp10b/therm_gp10b.o \
         gp10b/fecs_trace_gp10b.o \
         gp10b/gp10b.o \
         gp10b/fuse_gp10b.o \
@@ -301,7 +303,6 @@ nvgpu-y += \
         gv11b/acr_gv11b.o \
         gv11b/subctx_gv11b.o \
         gv11b/regops_gv11b.o \
-        gv11b/therm_gv11b.o \
         gv11b/ecc_gv11b.o \
         gv100/mm_gv100.o \
         gv100/gr_ctx_gv100.o \
@@ -328,7 +329,6 @@ nvgpu-y += \
         clk/clk.o \
         gp106/clk_gp106.o \
         gp106/clk_arb_gp106.o \
-        gp106/therm_gp106.o \
         pmgr/pwrdev.o \
         pmgr/pmgr.o \
         pmgr/pmgrpmu.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index e8e107ae..e4080013 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -45,6 +45,11 @@ srcs :=	common/mm/nvgpu_allocator.c \
         common/fb/fb_gv100.c \
         common/fb/fb_gv11b.c \
         common/xve/xve_gp106.c \
+        common/therm/therm.c \
+        common/therm/therm_gm20b.c \
+        common/therm/therm_gp10b.c \
+        common/therm/therm_gv11b.c \
+        common/therm/therm_gp106.c \
         common/enabled.c \
         common/pramin.c \
         common/semaphore.c \
@@ -138,7 +143,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gk20a/pmu_gk20a.c \
         gk20a/flcn_gk20a.c \
         gk20a/fence_gk20a.c \
-        gk20a/therm_gk20a.c \
         gk20a/gr_ctx_gk20a_sim.c \
         gk20a/gr_ctx_gk20a.c \
         gk20a/hal.c \
@@ -154,7 +158,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gm20b/pmu_gm20b.c \
         gm20b/mm_gm20b.c \
         gm20b/regops_gm20b.c \
-        gm20b/therm_gm20b.c \
         gm20b/fuse_gm20b.c \
         gp10b/gr_gp10b.c  \
         gp10b/gr_ctx_gp10b.c  \
@@ -166,7 +169,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gp10b/pmu_gp10b.c \
         gp10b/hal_gp10b.c \
         gp10b/regops_gp10b.c \
-        gp10b/therm_gp10b.c \
         gp10b/fecs_trace_gp10b.c \
         gp10b/gp10b.c \
         gp10b/fuse_gp10b.c \
@@ -185,7 +187,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gv11b/acr_gv11b.c \
         gv11b/subctx_gv11b.c \
         gv11b/regops_gv11b.c \
-        gv11b/therm_gv11b.c \
         gv11b/ecc_gv11b.c \
         gp106/hal_gp106.c \
         gp106/mm_gp106.c \
@@ -202,7 +203,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gp106/fuse_gp106.c \
         gp106/clk_gp106.c \
         gp106/clk_arb_gp106.c \
-        gp106/therm_gp106.c \
         gv100/mm_gv100.c \
         gv100/gr_ctx_gv100.c \
         gv100/bios_gv100.c \
diff --git a/drivers/gpu/nvgpu/common/therm/therm.c b/drivers/gpu/nvgpu/common/therm/therm.c
new file mode 100644
index 00000000..cfe8a2c1
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/log.h>
+#include <nvgpu/therm.h>
+
+#include "gk20a/gk20a.h"
+
+int nvgpu_init_therm_support(struct gk20a *g)
+{
+        u32 err = 0U;
+
+        nvgpu_log_fn(g, " ");
+
+        if (g->ops.therm.init_therm_setup_hw)
+                err = g->ops.therm.init_therm_setup_hw(g);
+        if (err)
+                return err;
+
+#ifdef CONFIG_DEBUG_FS
+        if (g->ops.therm.therm_debugfs_init)
+            g->ops.therm.therm_debugfs_init(g);
+#endif
+
+        return err;
+}
diff --git a/drivers/gpu/nvgpu/gm20b/therm_gm20b.c b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
index e2055376..023ec36a 100644
--- a/drivers/gpu/nvgpu/gm20b/therm_gm20b.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
@@ -77,3 +77,111 @@ int gm20b_init_therm_setup_hw(struct gk20a *g)
 
         return 0;
 }
+
+int gm20b_elcg_init_idle_filters(struct gk20a *g)
+{
+        u32 gate_ctrl, idle_filter;
+        u32 engine_id;
+        u32 active_engine_id = 0;
+        struct fifo_gk20a *f = &g->fifo;
+
+        nvgpu_log_fn(g, " ");
+
+        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+                active_engine_id = f->active_engines_list[engine_id];
+                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+                if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+                        gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_delay_after_m(),
+                                therm_gate_ctrl_eng_delay_after_f(4));
+                }
+
+                /* 2 * (1 << 9) = 1024 clks */
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_exp_m(),
+                        therm_gate_ctrl_eng_idle_filt_exp_f(9));
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_mant_m(),
+                        therm_gate_ctrl_eng_idle_filt_mant_f(2));
+                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
+        }
+
+        /* default fecs_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+        idle_filter &= ~therm_fecs_idle_filter_value_m();
+        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+        /* default hubmmu_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+        nvgpu_log_fn(g, "done");
+        return 0;
+}
+
+void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
+{
+        u32 gate_ctrl;
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
+        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
+
+        switch (mode) {
+        case BLCG_RUN:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_blk_clk_m(),
+                                therm_gate_ctrl_blk_clk_run_f());
+                break;
+        case BLCG_AUTO:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_blk_clk_m(),
+                                therm_gate_ctrl_blk_clk_auto_f());
+                break;
+        default:
+                nvgpu_err(g,
+                        "invalid blcg mode %d", mode);
+                return;
+        }
+
+        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
+}
+
+void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
+{
+        u32 gate_ctrl;
+
+        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
+                return;
+
+        switch (mode) {
+        case ELCG_RUN:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_run_f());
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_pwr_m(),
+                                /* set elpg to auto to meet hw expectation */
+                                therm_gate_ctrl_eng_pwr_auto_f());
+                break;
+        case ELCG_STOP:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_stop_f());
+                break;
+        case ELCG_AUTO:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_auto_f());
+                break;
+        default:
+                nvgpu_err(g,
+                        "invalid elcg mode %d", mode);
+        }
+
+        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
+}
diff --git a/drivers/gpu/nvgpu/gm20b/therm_gm20b.h b/drivers/gpu/nvgpu/common/therm/therm_gm20b.h
index df0b4219..b6dfc5b6 100644
--- a/drivers/gpu/nvgpu/gm20b/therm_gm20b.h
+++ b/drivers/gpu/nvgpu/common/therm/therm_gm20b.h
@@ -26,5 +26,8 @@
 
 struct gk20a;
 int gm20b_init_therm_setup_hw(struct gk20a *g);
+int gm20b_elcg_init_idle_filters(struct gk20a *g);
+void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
+void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
 
 #endif /* THERM_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
index 1f82aa7a..1f82aa7a 100644
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.h b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
index 5debcee7..a92c2e0f 100644
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.h
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
@@ -25,6 +25,8 @@
 #ifndef NVGPU_THERM_GP106_H
 #define NVGPU_THERM_GP106_H
 
+#include <nvgpu/types.h>
+
 struct gk20a;
 
 void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8);
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/common/therm/therm_gp10b.c
index 905ff178..905ff178 100644
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp10b.c
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h b/drivers/gpu/nvgpu/common/therm/therm_gp10b.h
index 2a40b73c..2a40b73c 100644
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp10b.h
diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/common/therm/therm_gv11b.c
index acc2c509..77edd7e1 100644
--- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gv11b.c
@@ -101,6 +101,41 @@ int gv11b_init_therm_setup_hw(struct gk20a *g)
         return 0;
 }
 
+void gv11b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
+{
+        u32 gate_ctrl;
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
+                return;
+
+        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
+
+        switch (mode) {
+        case ELCG_RUN:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_run_f());
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_idle_holdoff_m(),
+                                therm_gate_ctrl_idle_holdoff_on_f());
+                break;
+        case ELCG_STOP:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_stop_f());
+                break;
+        case ELCG_AUTO:
+                gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_clk_m(),
+                                therm_gate_ctrl_eng_clk_auto_f());
+                break;
+        default:
+                nvgpu_err(g, "invalid elcg mode %d", mode);
+        }
+
+        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
+}
+
 int gv11b_elcg_init_idle_filters(struct gk20a *g)
 {
         u32 gate_ctrl, idle_filter;
diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h b/drivers/gpu/nvgpu/common/therm/therm_gv11b.h
index bfe6231e..7058af9f 100644
--- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h
+++ b/drivers/gpu/nvgpu/common/therm/therm_gv11b.h
@@ -25,5 +25,6 @@
 struct gk20a;
 int gv11b_elcg_init_idle_filters(struct gk20a *g);
 int gv11b_init_therm_setup_hw(struct gk20a *g);
+void gv11b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
 
 #endif /* THERM_GV11B_H */
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index a257d709..65bf2976 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -36,7 +36,6 @@
 #include "dbg_gpu_gk20a.h"
 #include "regops_gk20a.h"
 
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 24cfc6ec..859a7b6a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -36,6 +36,7 @@
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/therm.h>
 
 #include <trace/events/gk20a.h>
 
@@ -323,7 +324,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
-        err = gk20a_init_therm_support(g);
+        err = nvgpu_init_therm_support(g);
         if (err) {
                 nvgpu_err(g, "failed to init gk20a therm");
                 goto done;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 204fd371..5bb91f62 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter;
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
 #include "pmu_gk20a.h"
-#include "therm_gk20a.h"
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
@@ -161,6 +160,18 @@ struct nvgpu_gpfifo_userdata {
 #define NVGPU_FB_MMU_FAULT_BUF_DISABLED                 0U
 #define NVGPU_FB_MMU_FAULT_BUF_ENABLED                  1U
 
+/* Parameters for init_elcg_mode/init_blcg_mode */
+enum {
+        ELCG_RUN,       /* clk always run, i.e. disable elcg */
+        ELCG_STOP,      /* clk is stopped */
+        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
+};
+
+enum {
+        BLCG_RUN,       /* clk always run, i.e. disable blcg */
+        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
+};
+
 struct gpu_ops {
         struct {
                 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -425,7 +436,6 @@ struct gpu_ops {
                                         struct nvgpu_mem *mem, u64 gpu_va);
                 void (*set_preemption_buffer_va)(struct gk20a *g,
                                         struct nvgpu_mem *mem, u64 gpu_va);
-                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 void (*load_tpc_mask)(struct gk20a *g);
                 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*trigger_suspend)(struct gk20a *g);
@@ -979,6 +989,8 @@ struct gpu_ops {
         } pramin;
         struct {
                 int (*init_therm_setup_hw)(struct gk20a *g);
+                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
+                void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 int (*elcg_init_idle_filters)(struct gk20a *g);
 #ifdef CONFIG_DEBUG_FS
                 void (*therm_debugfs_init)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5539b801..bb54e00e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -61,7 +61,6 @@
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
 
 #define BLK_SIZE (256)
@@ -4116,72 +4115,6 @@ int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                 gr_gk20a_add_zbc(g, gr, zbc_val));
 }
 
-void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
-{
-        u32 gate_ctrl;
-
-        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
-                return;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
-
-        switch (mode) {
-        case BLCG_RUN:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_blk_clk_m(),
-                                therm_gate_ctrl_blk_clk_run_f());
-                break;
-        case BLCG_AUTO:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_blk_clk_m(),
-                                therm_gate_ctrl_blk_clk_auto_f());
-                break;
-        default:
-                nvgpu_err(g,
-                        "invalid blcg mode %d", mode);
-                return;
-        }
-
-        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
-}
-
-void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
-{
-        u32 gate_ctrl;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
-
-        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
-                return;
-
-        switch (mode) {
-        case ELCG_RUN:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_run_f());
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_pwr_m(),
-                                /* set elpg to auto to meet hw expectation */
-                                therm_gate_ctrl_eng_pwr_auto_f());
-                break;
-        case ELCG_STOP:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_stop_f());
-                break;
-        case ELCG_AUTO:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_auto_f());
-                break;
-        default:
-                nvgpu_err(g,
-                        "invalid elcg mode %d", mode);
-        }
-
-        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
-}
-
 void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
 {
         u32 engine_idx;
@@ -4196,10 +4129,10 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
                 /* gr_engine supports both BLCG and ELCG */
                 if ((cgmode == BLCG_MODE) &&
                         (engine_info->engine_enum == ENGINE_GR_GK20A)) {
-                                gr_gk20a_init_blcg_mode(g, mode_config, active_engine_id);
+                                g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id);
                                 break;
                 } else if (cgmode == ELCG_MODE)
-                        g->ops.gr.init_elcg_mode(g, mode_config,
+                        g->ops.therm.init_elcg_mode(g, mode_config,
                                                 active_engine_id);
                 else
                         nvgpu_err(g, "invalid cg mode %d, config %d for "
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 2b31b6b6..9c9a3caa 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -126,17 +126,6 @@ enum {
 };
 
 enum {
-        ELCG_RUN,       /* clk always run, i.e. disable elcg */
-        ELCG_STOP,      /* clk is stopped */
-        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
-};
-
-enum {
-        BLCG_RUN,       /* clk always run, i.e. disable blcg */
-        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
-};
-
-enum {
         NVGPU_EVENT_ID_BPT_INT = 0,
         NVGPU_EVENT_ID_BPT_PAUSE,
         NVGPU_EVENT_ID_BLOCKING_SYNC,
@@ -609,9 +598,6 @@ int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g,
                 struct nvgpu_mem *inst_block);
 int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va);
 
-void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
-void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
-
 void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
 
 /* sm */
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
deleted file mode 100644
index b4a81aed..00000000
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * GK20A Therm
- *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-#include <nvgpu/utils.h>
-
-#include "gk20a.h"
-
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
-
-static int gk20a_init_therm_reset_enable_hw(struct gk20a *g)
-{
-        return 0;
-}
-
-static int gk20a_init_therm_setup_sw(struct gk20a *g)
-{
-        return 0;
-}
-
-int gk20a_init_therm_support(struct gk20a *g)
-{
-        u32 err;
-
-        nvgpu_log_fn(g, " ");
-
-        err = gk20a_init_therm_reset_enable_hw(g);
-        if (err)
-                return err;
-
-        err = gk20a_init_therm_setup_sw(g);
-        if (err)
-                return err;
-
-        if (g->ops.therm.init_therm_setup_hw)
-                err = g->ops.therm.init_therm_setup_hw(g);
-        if (err)
-                return err;
-
-#ifdef CONFIG_DEBUG_FS
-        if (g->ops.therm.therm_debugfs_init)
-            g->ops.therm.therm_debugfs_init(g);
-#endif
-
-        return err;
-}
-
-int gk20a_elcg_init_idle_filters(struct gk20a *g)
-{
-        u32 gate_ctrl, idle_filter;
-        u32 engine_id;
-        u32 active_engine_id = 0;
-        struct fifo_gk20a *f = &g->fifo;
-
-        nvgpu_log_fn(g, " ");
-
-        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
-                active_engine_id = f->active_engines_list[engine_id];
-                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
-
-                if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                        gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_delay_after_m(),
-                                therm_gate_ctrl_eng_delay_after_f(4));
-                }
-
-                /* 2 * (1 << 9) = 1024 clks */
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_exp_m(),
-                        therm_gate_ctrl_eng_idle_filt_exp_f(9));
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_mant_m(),
-                        therm_gate_ctrl_eng_idle_filt_mant_f(2));
-                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
-        }
-
-        /* default fecs_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
-        idle_filter &= ~therm_fecs_idle_filter_value_m();
-        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
-        /* default hubmmu_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
-        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
-        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index e6c4c8d1..05acc0cf 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -29,12 +29,13 @@
 #include "common/ptimer/ptimer_gk20a.h"
 #include "common/fb/fb_gk20a.h"
 #include "common/fb/fb_gm20b.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gm20b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ce2_gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
-#include "gk20a/therm_gk20a.h"
 #include "gk20a/mm_gk20a.h"
 #include "gk20a/css_gr_gk20a.h"
 #include "gk20a/mc_gk20a.h"
@@ -53,7 +54,6 @@
 #include "pmu_gm20b.h"
 #include "clk_gm20b.h"
 #include "regops_gm20b.h"
-#include "therm_gm20b.h"
 #include "hal_gm20b.h"
 #include "acr_gm20b.h"
 #include "fuse_gm20b.h"
@@ -291,7 +291,6 @@ static const struct gpu_ops gm20b_ops = {
                 .commit_inst = gr_gk20a_commit_inst,
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
-                .init_elcg_mode = gr_gk20a_init_elcg_mode,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
@@ -512,7 +511,9 @@ static const struct gpu_ops gm20b_ops = {
         },
         .therm = {
                 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
-                .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
+                .init_elcg_mode = gm20b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
+                .elcg_init_idle_filters = gm20b_elcg_init_idle_filters,
         },
         .pmu = {
                 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 90d25fa0..02a2f0a6 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -34,6 +34,8 @@
 #include "common/fb/fb_gm20b.h"
 #include "common/fb/fb_gp106.h"
 #include "common/xve/xve_gp106.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp106.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -76,7 +78,6 @@
 #include "gp106/clk_arb_gp106.h"
 #include "gp106/mclk_gp106.h"
 #include "gp106/bios_gp106.h"
-#include "gp106/therm_gp106.h"
 #include "gp106/fifo_gp106.h"
 #include "gp106/clk_gp106.h"
 #include "gp106/mm_gp106.h"
@@ -349,7 +350,6 @@ static const struct gpu_ops gp106_ops = {
                 .commit_inst = gr_gk20a_commit_inst,
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
-                .init_elcg_mode = gr_gk20a_init_elcg_mode,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
@@ -606,6 +606,8 @@ static const struct gpu_ops gp106_ops = {
 #ifdef CONFIG_DEBUG_FS
                 .therm_debugfs_init = gp106_therm_debugfs_init,
 #endif /* CONFIG_DEBUG_FS */
+                .init_elcg_mode = gm20b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = gp106_elcg_init_idle_filters,
                 .get_internal_sensor_curr_temp =
                         gp106_get_internal_sensor_curr_temp,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 5f55baa3..cfbdc6ce 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -32,6 +32,8 @@
 #include "common/fb/fb_gk20a.h"
 #include "common/fb/fb_gm20b.h"
 #include "common/fb/fb_gp10b.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -56,7 +58,6 @@
 #include "gp10b/gr_ctx_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/regops_gp10b.h"
-#include "gp10b/therm_gp10b.h"
 #include "gp10b/ecc_gp10b.h"
 
 #include "gm20b/ltc_gm20b.h"
@@ -308,7 +309,6 @@ static const struct gpu_ops gp10b_ops = {
                 .commit_inst = gr_gk20a_commit_inst,
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
-                .init_elcg_mode = gr_gk20a_init_elcg_mode,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
@@ -573,6 +573,8 @@ static const struct gpu_ops gp10b_ops = {
         },
         .therm = {
                 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
+                .init_elcg_mode = gm20b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
         },
         .pmu = {
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 344ad1e8..7926c35c 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -35,6 +35,10 @@
 #include "common/fb/fb_gv11b.h"
 #include "common/fb/fb_gv100.h"
 #include "common/xve/xve_gp106.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp106.h"
+#include "common/therm/therm_gp10b.h"
+#include "common/therm/therm_gv11b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -61,13 +65,11 @@
 #include "gp106/acr_gp106.h"
 #include "gp106/sec2_gp106.h"
 #include "gp106/bios_gp106.h"
-#include "gp106/therm_gp106.h"
 #include "gp106/clk_gp106.h"
 #include "gp106/flcn_gp106.h"
 
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/ltc_gp10b.h"
-#include "gp10b/therm_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
@@ -385,7 +387,6 @@ static const struct gpu_ops gv100_ops = {
                 .commit_inst = gr_gv11b_commit_inst,
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
-                .init_elcg_mode = gr_gv11b_init_elcg_mode,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
@@ -703,6 +704,8 @@ static const struct gpu_ops gv100_ops = {
                 .therm_debugfs_init = gp106_therm_debugfs_init,
 #endif /* CONFIG_DEBUG_FS */
                 /* PROD values match with H/W INIT values */
+                .init_elcg_mode = gv11b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = NULL,
                 .get_internal_sensor_curr_temp =
                         gp106_get_internal_sensor_curr_temp,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 058a21e5..c2cf909a 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -58,7 +58,6 @@
 #include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 
@@ -2915,41 +2914,6 @@ void gr_gv11b_write_pm_ptr(struct gk20a *g,
                 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
 }
 
-void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
-{
-        u32 gate_ctrl;
-
-        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
-                return;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
-
-        switch (mode) {
-        case ELCG_RUN:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_run_f());
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_idle_holdoff_m(),
-                                therm_gate_ctrl_idle_holdoff_on_f());
-                break;
-        case ELCG_STOP:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_stop_f());
-                break;
-        case ELCG_AUTO:
-                gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_clk_m(),
-                                therm_gate_ctrl_eng_clk_auto_f());
-                break;
-        default:
-                nvgpu_err(g, "invalid elcg mode %d", mode);
-        }
-
-        gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
-}
-
 void gr_gv11b_load_tpc_mask(struct gk20a *g)
 {
         u32 pes_tpc_mask = 0, fuse_tpc_mask;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 0a8a536c..0f29ea24 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -158,7 +158,6 @@ void gr_gv11b_write_zcull_ptr(struct gk20a *g,
                                 struct nvgpu_mem *mem, u64 gpu_va);
 void gr_gv11b_write_pm_ptr(struct gk20a *g,
                                 struct nvgpu_mem *mem, u64 gpu_va);
-void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
 void gr_gv11b_load_tpc_mask(struct gk20a *g);
 void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
                         struct nvgpu_mem *mem, u64 gpu_va);
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 05763cce..111a1ea2 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -33,6 +33,9 @@
 #include "common/fb/fb_gm20b.h"
 #include "common/fb/fb_gp10b.h"
 #include "common/fb/fb_gv11b.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp10b.h"
+#include "common/therm/therm_gv11b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -54,7 +57,6 @@
 #include "gm20b/pmu_gm20b.h"
 
 #include "gp10b/ltc_gp10b.h"
-#include "gp10b/therm_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
@@ -84,7 +86,6 @@
 #include "fifo_gv11b.h"
 #include "regops_gv11b.h"
 #include "subctx_gv11b.h"
-#include "therm_gv11b.h"
 #include "ecc_gv11b.h"
 
 #include <nvgpu/ptimer.h>
@@ -341,7 +342,6 @@ static const struct gpu_ops gv11b_ops = {
                 .commit_inst = gr_gv11b_commit_inst,
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
-                .init_elcg_mode = gr_gv11b_init_elcg_mode,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
@@ -664,6 +664,8 @@ static const struct gpu_ops gv11b_ops = {
         },
         .therm = {
                 .init_therm_setup_hw = gv11b_init_therm_setup_hw,
+                .init_elcg_mode = gv11b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
         },
         .pmu = {
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/therm.h
index 303c28f4..41808de8 100644
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/therm.h
@@ -19,13 +19,11 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef THERM_GK20A_H
-#define THERM_GK20A_H
+#ifndef NVGPU_THERM_H
+#define NVGPU_THERM_H
 
-struct gpu_ops;
 struct gk20a;
 
-int gk20a_elcg_init_idle_filters(struct gk20a *g);
+int nvgpu_init_therm_support(struct gk20a *g);
 
-int gk20a_init_therm_support(struct gk20a *g);
-#endif /* THERM_GK20A_H */
+#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 15e2717d..aadd17d6 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -28,6 +28,8 @@
 #include "common/fb/fb_gk20a.h"
 #include "common/fb/fb_gm20b.h"
 #include "common/fb/fb_gp10b.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp10b.h"
 
 #include "vgpu/fifo_vgpu.h"
 #include "vgpu/gr_vgpu.h"
@@ -56,7 +58,6 @@
 #include "gp10b/gr_ctx_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/regops_gp10b.h"
-#include "gp10b/therm_gp10b.h"
 #include "gp10b/fuse_gp10b.h"
 
 #include "gm20b/ltc_gm20b.h"
@@ -182,7 +183,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .commit_inst = vgpu_gr_commit_inst,
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
-                .init_elcg_mode = gr_gk20a_init_elcg_mode,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
@@ -440,6 +440,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
         },
         .therm = {
                 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
+                .init_elcg_mode = gm20b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
         },
         .pmu = {
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 995a2c2c..e2410e4e 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -29,6 +29,9 @@
 #include "common/fb/fb_gm20b.h"
 #include "common/fb/fb_gp10b.h"
 #include "common/fb/fb_gv11b.h"
+#include "common/therm/therm_gm20b.h"
+#include "common/therm/therm_gp10b.h"
+#include "common/therm/therm_gv11b.h"
 
 #include <gk20a/gk20a.h>
 #include <gv11b/hal_gv11b.h>
@@ -63,7 +66,6 @@
 #include <gp10b/ce_gp10b.h>
 #include "gp10b/gr_gp10b.h"
 #include <gp10b/fifo_gp10b.h>
-#include <gp10b/therm_gp10b.h>
 #include <gp10b/ltc_gp10b.h>
 #include <gp10b/fuse_gp10b.h>
 
@@ -76,7 +78,6 @@
 #include <gv11b/mc_gv11b.h>
 #include <gv11b/ce_gv11b.h>
 #include <gv11b/fifo_gv11b.h>
-#include <gv11b/therm_gv11b.h>
 #include <gv11b/regops_gv11b.h>
 #include <gv11b/gr_ctx_gv11b.h>
 #include <gv11b/ltc_gv11b.h>
@@ -200,7 +201,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .commit_inst = vgpu_gr_gv11b_commit_inst,
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
-                .init_elcg_mode = gr_gv11b_init_elcg_mode,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
                 .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
@@ -505,6 +505,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
         },
         .therm = {
                 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
+                .init_elcg_mode = gv11b_therm_init_elcg_mode,
+                .init_blcg_mode = gm20b_therm_init_blcg_mode,
                 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
         },
         .pmu = {