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authorNitin Kumbhar <nkumbhar@nvidia.com>2018-05-31 09:43:43 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-06-15 08:04:16 -0400
commit8f2cb85983c7cd0c913e6a06df16f929d58a10a9 (patch)
tree8b56f492d2e422104690f38606bba824ded45cff
parent19e9a791955811416729ae3a94439c09000b3952 (diff)
gpu: nvgpu: update ecc sysfs node handling
Make ecc sysfs hash table per GPU by adding it as part of nvgpu_os_linux. Using a single hash table might give incorrect results as GPUs have same filenames and a filename is used as a key for a lookup. Add device_attribute as part of struct gk20a_ecc_stat. Using a single array of pointers of device attribute for an ecc_stat results in memory leak and incorrect stats if multiple GPUs are present on the system. This array of pointers will always hold info for GPU which created sysfs nodes last. Fix this by making device attribute array per ecc stat per GPU. Fix ecc stat removal to consider zero sub-units for a given number of hwunits. The multiplication with zero results in not removing any sysfs node at all. Bug 1987855 Change-Id: Ifcacc5623cede8decfe228c02d72786337cd0876 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c2
-rw-r--r--drivers/gpu/nvgpu/common/linux/os_linux.h3
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c2
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.c90
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.h36
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c192
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c310
-rw-r--r--drivers/gpu/nvgpu/gk20a/ecc_gk20a.h1
8 files changed, 277 insertions, 359 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index a7289b66..af71cc81 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -1146,6 +1146,8 @@ static int gk20a_probe(struct platform_device *dev)
1146 return -ENOMEM; 1146 return -ENOMEM;
1147 } 1147 }
1148 1148
1149 hash_init(l->ecc_sysfs_stats_htable);
1150
1149 gk20a = &l->g; 1151 gk20a = &l->g;
1150 1152
1151 nvgpu_log_fn(gk20a, " "); 1153 nvgpu_log_fn(gk20a, " ");
diff --git a/drivers/gpu/nvgpu/common/linux/os_linux.h b/drivers/gpu/nvgpu/common/linux/os_linux.h
index ebe131de..4dcce322 100644
--- a/drivers/gpu/nvgpu/common/linux/os_linux.h
+++ b/drivers/gpu/nvgpu/common/linux/os_linux.h
@@ -19,6 +19,7 @@
19 19
20#include <linux/cdev.h> 20#include <linux/cdev.h>
21#include <linux/iommu.h> 21#include <linux/iommu.h>
22#include <linux/hashtable.h>
22 23
23#include "gk20a/gk20a.h" 24#include "gk20a/gk20a.h"
24#include "cde.h" 25#include "cde.h"
@@ -139,6 +140,8 @@ struct nvgpu_os_linux {
139 struct dentry *debugfs_force_preemption_gfxp; 140 struct dentry *debugfs_force_preemption_gfxp;
140 struct dentry *debugfs_dump_ctxsw_stats; 141 struct dentry *debugfs_dump_ctxsw_stats;
141#endif 142#endif
143 DECLARE_HASHTABLE(ecc_sysfs_stats_htable, 5);
144
142 struct gk20a_cde_app cde_app; 145 struct gk20a_cde_app cde_app;
143 146
144 struct rw_semaphore busy_lock; 147 struct rw_semaphore busy_lock;
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index 6caf5ad9..1011b441 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -646,6 +646,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
646 return -ENOMEM; 646 return -ENOMEM;
647 } 647 }
648 648
649 hash_init(l->ecc_sysfs_stats_htable);
650
649 g = &l->g; 651 g = &l->g;
650 nvgpu_init_gk20a(g); 652 nvgpu_init_gk20a(g);
651 653
diff --git a/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.c b/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.c
index ee59e5de..0fe1c8d2 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.c
@@ -14,6 +14,8 @@
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17#include <linux/hashtable.h>
18
17#include <nvgpu/kmem.h> 19#include <nvgpu/kmem.h>
18#include <nvgpu/bug.h> 20#include <nvgpu/bug.h>
19#include <nvgpu/hashtable.h> 21#include <nvgpu/hashtable.h>
@@ -28,10 +30,6 @@
28#include "platform_gp10b_tegra.h" 30#include "platform_gp10b_tegra.h"
29#include "platform_ecc_sysfs.h" 31#include "platform_ecc_sysfs.h"
30 32
31#define ECC_STAT_NAME_MAX_SIZE 100
32
33static DEFINE_HASHTABLE(ecc_hash_table, 5);
34
35static u32 gen_ecc_hash_key(char *str) 33static u32 gen_ecc_hash_key(char *str)
36{ 34{
37 int i = 0; 35 int i = 0;
@@ -57,6 +55,7 @@ static ssize_t ecc_stat_show(struct device *dev,
57 struct gk20a_ecc_stat *ecc_stat; 55 struct gk20a_ecc_stat *ecc_stat;
58 u32 hash_key; 56 u32 hash_key;
59 struct gk20a *g = get_gk20a(dev); 57 struct gk20a *g = get_gk20a(dev);
58 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
60 59
61 if (sscanf(ecc_stat_full_name, "ltc%u_lts%u", &hw_unit, 60 if (sscanf(ecc_stat_full_name, "ltc%u_lts%u", &hw_unit,
62 &subunit) == 2) { 61 &subunit) == 2) {
@@ -78,7 +77,7 @@ static ssize_t ecc_stat_show(struct device *dev,
78 77
79 hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name); 78 hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name);
80 79
81 hash_for_each_possible(ecc_hash_table, 80 hash_for_each_possible(l->ecc_sysfs_stats_htable,
82 ecc_stat, 81 ecc_stat,
83 hash_node, 82 hash_node,
84 hash_key) { 83 hash_key) {
@@ -91,11 +90,9 @@ static ssize_t ecc_stat_show(struct device *dev,
91 return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n"); 90 return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n");
92} 91}
93 92
94int gr_gp10b_ecc_stat_create(struct device *dev, 93int nvgpu_gr_ecc_stat_create(struct device *dev,
95 int is_l2, 94 int is_l2, char *ecc_stat_name,
96 char *ecc_stat_name, 95 struct gk20a_ecc_stat *ecc_stat)
97 struct gk20a_ecc_stat *ecc_stat,
98 struct device_attribute **dev_attr_array)
99{ 96{
100 struct gk20a *g = get_gk20a(dev); 97 struct gk20a *g = get_gk20a(dev);
101 char *ltc_unit_name = "ltc"; 98 char *ltc_unit_name = "ltc";
@@ -113,32 +110,29 @@ int gr_gp10b_ecc_stat_create(struct device *dev,
113 num_hw_units = g->gr.tpc_count; 110 num_hw_units = g->gr.tpc_count;
114 111
115 112
116 return gp10b_ecc_stat_create(dev, num_hw_units, num_subunits, 113 return nvgpu_ecc_stat_create(dev, num_hw_units, num_subunits,
117 is_l2 ? ltc_unit_name : gr_unit_name, 114 is_l2 ? ltc_unit_name : gr_unit_name,
118 num_subunits ? lts_unit_name: NULL, 115 num_subunits ? lts_unit_name: NULL,
119 ecc_stat_name, 116 ecc_stat_name,
120 ecc_stat, 117 ecc_stat);
121 dev_attr_array);
122} 118}
123 119
124int gp10b_ecc_stat_create(struct device *dev, 120int nvgpu_ecc_stat_create(struct device *dev,
125 int num_hw_units, 121 int num_hw_units, int num_subunits,
126 int num_subunits, 122 char *ecc_unit_name, char *ecc_subunit_name,
127 char *ecc_unit_name, 123 char *ecc_stat_name,
128 char *ecc_subunit_name, 124 struct gk20a_ecc_stat *ecc_stat)
129 char *ecc_stat_name,
130 struct gk20a_ecc_stat *ecc_stat,
131 struct device_attribute **__dev_attr_array)
132{ 125{
133 int error = 0; 126 int error = 0;
134 struct gk20a *g = get_gk20a(dev); 127 struct gk20a *g = get_gk20a(dev);
128 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
135 int hw_unit = 0; 129 int hw_unit = 0;
136 int subunit = 0; 130 int subunit = 0;
137 int element = 0; 131 int element = 0;
138 u32 hash_key = 0; 132 u32 hash_key = 0;
139 struct device_attribute *dev_attr_array; 133 struct device_attribute *dev_attr_array;
140 134
141 int num_elements = num_subunits ? num_subunits*num_hw_units : 135 int num_elements = num_subunits ? num_subunits * num_hw_units :
142 num_hw_units; 136 num_hw_units;
143 137
144 /* Allocate arrays */ 138 /* Allocate arrays */
@@ -146,6 +140,7 @@ int gp10b_ecc_stat_create(struct device *dev,
146 num_elements); 140 num_elements);
147 ecc_stat->counters = nvgpu_kzalloc(g, sizeof(u32) * num_elements); 141 ecc_stat->counters = nvgpu_kzalloc(g, sizeof(u32) * num_elements);
148 ecc_stat->names = nvgpu_kzalloc(g, sizeof(char *) * num_elements); 142 ecc_stat->names = nvgpu_kzalloc(g, sizeof(char *) * num_elements);
143
149 for (hw_unit = 0; hw_unit < num_elements; hw_unit++) { 144 for (hw_unit = 0; hw_unit < num_elements; hw_unit++) {
150 ecc_stat->names[hw_unit] = nvgpu_kzalloc(g, sizeof(char) * 145 ecc_stat->names[hw_unit] = nvgpu_kzalloc(g, sizeof(char) *
151 ECC_STAT_NAME_MAX_SIZE); 146 ECC_STAT_NAME_MAX_SIZE);
@@ -206,44 +201,58 @@ int gp10b_ecc_stat_create(struct device *dev,
206 201
207 /* Add hash table entry */ 202 /* Add hash table entry */
208 hash_key = gen_ecc_hash_key(ecc_stat_name); 203 hash_key = gen_ecc_hash_key(ecc_stat_name);
209 hash_add(ecc_hash_table, 204 hash_add(l->ecc_sysfs_stats_htable,
210 &ecc_stat->hash_node, 205 &ecc_stat->hash_node,
211 hash_key); 206 hash_key);
212 207
213 *__dev_attr_array = dev_attr_array; 208 ecc_stat->attr_array = dev_attr_array;
214 209
215 return error; 210 return error;
216} 211}
217 212
218void gr_gp10b_ecc_stat_remove(struct device *dev, 213void nvgpu_gr_ecc_stat_remove(struct device *dev,
219 int is_l2, 214 int is_l2, struct gk20a_ecc_stat *ecc_stat)
220 struct gk20a_ecc_stat *ecc_stat,
221 struct device_attribute *dev_attr_array)
222{ 215{
223 struct gk20a *g = get_gk20a(dev); 216 struct gk20a *g = get_gk20a(dev);
224 int num_hw_units = 0; 217 int num_hw_units = 0;
218 int num_subunits = 0;
225 219
226 if (is_l2 == 1) 220 if (is_l2 == 1)
227 num_hw_units = g->ltc_count; 221 num_hw_units = g->ltc_count;
228 else if (is_l2 == 2) 222 else if (is_l2 == 2) {
229 num_hw_units = g->ltc_count * g->gr.slices_per_ltc; 223 num_hw_units = g->ltc_count;
230 else 224 num_subunits = g->gr.slices_per_ltc;
225 } else
231 num_hw_units = g->gr.tpc_count; 226 num_hw_units = g->gr.tpc_count;
232 227
233 gp10b_ecc_stat_remove(dev, num_hw_units, ecc_stat, dev_attr_array); 228 nvgpu_ecc_stat_remove(dev, num_hw_units, num_subunits, ecc_stat);
234} 229}
235 230
236void gp10b_ecc_stat_remove(struct device *dev, 231void nvgpu_ecc_stat_remove(struct device *dev,
237 int num_hw_units, 232 int num_hw_units, int num_subunits,
238 struct gk20a_ecc_stat *ecc_stat, 233 struct gk20a_ecc_stat *ecc_stat)
239 struct device_attribute *dev_attr_array)
240{ 234{
241 struct gk20a *g = get_gk20a(dev); 235 struct gk20a *g = get_gk20a(dev);
236 struct device_attribute *dev_attr_array = ecc_stat->attr_array;
242 int hw_unit = 0; 237 int hw_unit = 0;
238 int subunit = 0;
239 int element = 0;
240 int num_elements = num_subunits ? num_subunits * num_hw_units :
241 num_hw_units;
243 242
244 /* Remove sysfs files */ 243 /* Remove sysfs files */
245 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { 244 if (num_subunits) {
246 device_remove_file(dev, &dev_attr_array[hw_unit]); 245 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
246 for (subunit = 0; subunit < num_subunits; subunit++) {
247 element = hw_unit * num_subunits + subunit;
248
249 device_remove_file(dev,
250 &dev_attr_array[element]);
251 }
252 }
253 } else {
254 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++)
255 device_remove_file(dev, &dev_attr_array[hw_unit]);
247 } 256 }
248 257
249 /* Remove hash table entry */ 258 /* Remove hash table entry */
@@ -251,9 +260,10 @@ void gp10b_ecc_stat_remove(struct device *dev,
251 260
252 /* Free arrays */ 261 /* Free arrays */
253 nvgpu_kfree(g, ecc_stat->counters); 262 nvgpu_kfree(g, ecc_stat->counters);
254 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { 263
264 for (hw_unit = 0; hw_unit < num_elements; hw_unit++)
255 nvgpu_kfree(g, ecc_stat->names[hw_unit]); 265 nvgpu_kfree(g, ecc_stat->names[hw_unit]);
256 } 266
257 nvgpu_kfree(g, ecc_stat->names); 267 nvgpu_kfree(g, ecc_stat->names);
258 nvgpu_kfree(g, dev_attr_array); 268 nvgpu_kfree(g, dev_attr_array);
259} 269}
diff --git a/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.h b/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.h
index d5622757..d29f7bd3 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.h
+++ b/drivers/gpu/nvgpu/common/linux/platform_ecc_sysfs.h
@@ -19,27 +19,19 @@
19 19
20#include "gp10b/gr_gp10b.h" 20#include "gp10b/gr_gp10b.h"
21 21
22int gr_gp10b_ecc_stat_create(struct device *dev, 22#define ECC_STAT_NAME_MAX_SIZE 100
23 int is_l2,
24 char *ecc_stat_name,
25 struct gk20a_ecc_stat *ecc_stat,
26 struct device_attribute **dev_attr_array);
27int gp10b_ecc_stat_create(struct device *dev,
28 int num_hw_units,
29 int num_subunits,
30 char *ecc_unit_name,
31 char *ecc_subunit_name,
32 char *ecc_stat_name,
33 struct gk20a_ecc_stat *ecc_stat,
34 struct device_attribute **__dev_attr_array);
35 23
36void gr_gp10b_ecc_stat_remove(struct device *dev, 24int nvgpu_gr_ecc_stat_create(struct device *dev,
37 int is_l2, 25 int is_l2, char *ecc_stat_name,
38 struct gk20a_ecc_stat *ecc_stat, 26 struct gk20a_ecc_stat *ecc_stat);
39 struct device_attribute *dev_attr_array); 27int nvgpu_ecc_stat_create(struct device *dev,
40 28 int num_hw_units, int num_subunits,
41void gp10b_ecc_stat_remove(struct device *dev, 29 char *ecc_unit_name, char *ecc_subunit_name,
42 int hw_units, 30 char *ecc_stat_name,
43 struct gk20a_ecc_stat *ecc_stat, 31 struct gk20a_ecc_stat *ecc_stat);
44 struct device_attribute *dev_attr_array); 32void nvgpu_gr_ecc_stat_remove(struct device *dev,
33 int is_l2, struct gk20a_ecc_stat *ecc_stat);
34void nvgpu_ecc_stat_remove(struct device *dev,
35 int num_hw_units, int num_subunits,
36 struct gk20a_ecc_stat *ecc_stat);
45#endif 37#endif
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
index 6f8cc507..fce16653 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
@@ -41,6 +41,7 @@
41#include "gk20a/gk20a.h" 41#include "gk20a/gk20a.h"
42 42
43#include "platform_gk20a.h" 43#include "platform_gk20a.h"
44#include "platform_ecc_sysfs.h"
44#include "platform_gk20a_tegra.h" 45#include "platform_gk20a_tegra.h"
45#include "gp10b/platform_gp10b.h" 46#include "gp10b/platform_gp10b.h"
46#include "platform_gp10b_tegra.h" 47#include "platform_gp10b_tegra.h"
@@ -446,25 +447,6 @@ struct gk20a_platform gp10b_tegra_platform = {
446 .secure_buffer_size = 401408, 447 .secure_buffer_size = 401408,
447}; 448};
448 449
449static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array;
450static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array;
451
452static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array;
453static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array;
454static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array;
455
456static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array;
457static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array;
458static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array;
459static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array;
460static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array;
461static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array;
462static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array;
463static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array;
464
465static struct device_attribute *dev_attr_l2_ecc_sec_count_array;
466static struct device_attribute *dev_attr_l2_ecc_ded_count_array;
467
468void gr_gp10b_create_sysfs(struct gk20a *g) 450void gr_gp10b_create_sysfs(struct gk20a *g)
469{ 451{
470 int error = 0; 452 int error = 0;
@@ -477,84 +459,80 @@ void gr_gp10b_create_sysfs(struct gk20a *g)
477 if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL) 459 if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL)
478 return; 460 return;
479 461
480 error |= gr_gp10b_ecc_stat_create(dev, 462 error |= nvgpu_gr_ecc_stat_create(dev,
481 0, 463 0,
482 "sm_lrf_ecc_single_err_count", 464 "sm_lrf_ecc_single_err_count",
483 &g->ecc.gr.sm_lrf_single_err_count, 465 &g->ecc.gr.sm_lrf_single_err_count);
484 &dev_attr_sm_lrf_ecc_single_err_count_array); 466
485 error |= gr_gp10b_ecc_stat_create(dev, 467 error |= nvgpu_gr_ecc_stat_create(dev,
486 0, 468 0,
487 "sm_lrf_ecc_double_err_count", 469 "sm_lrf_ecc_double_err_count",
488 &g->ecc.gr.sm_lrf_double_err_count, 470 &g->ecc.gr.sm_lrf_double_err_count);
489 &dev_attr_sm_lrf_ecc_double_err_count_array);
490 471
491 error |= gr_gp10b_ecc_stat_create(dev, 472 error |= nvgpu_gr_ecc_stat_create(dev,
492 0, 473 0,
493 "sm_shm_ecc_sec_count", 474 "sm_shm_ecc_sec_count",
494 &g->ecc.gr.sm_shm_sec_count, 475 &g->ecc.gr.sm_shm_sec_count);
495 &dev_attr_sm_shm_ecc_sec_count_array); 476
496 error |= gr_gp10b_ecc_stat_create(dev, 477 error |= nvgpu_gr_ecc_stat_create(dev,
497 0, 478 0,
498 "sm_shm_ecc_sed_count", 479 "sm_shm_ecc_sed_count",
499 &g->ecc.gr.sm_shm_sed_count, 480 &g->ecc.gr.sm_shm_sed_count);
500 &dev_attr_sm_shm_ecc_sed_count_array); 481
501 error |= gr_gp10b_ecc_stat_create(dev, 482 error |= nvgpu_gr_ecc_stat_create(dev,
502 0, 483 0,
503 "sm_shm_ecc_ded_count", 484 "sm_shm_ecc_ded_count",
504 &g->ecc.gr.sm_shm_ded_count, 485 &g->ecc.gr.sm_shm_ded_count);
505 &dev_attr_sm_shm_ecc_ded_count_array);
506 486
507 error |= gr_gp10b_ecc_stat_create(dev, 487 error |= nvgpu_gr_ecc_stat_create(dev,
508 0, 488 0,
509 "tex_ecc_total_sec_pipe0_count", 489 "tex_ecc_total_sec_pipe0_count",
510 &g->ecc.gr.tex_total_sec_pipe0_count, 490 &g->ecc.gr.tex_total_sec_pipe0_count);
511 &dev_attr_tex_ecc_total_sec_pipe0_count_array); 491
512 error |= gr_gp10b_ecc_stat_create(dev, 492 error |= nvgpu_gr_ecc_stat_create(dev,
513 0, 493 0,
514 "tex_ecc_total_ded_pipe0_count", 494 "tex_ecc_total_ded_pipe0_count",
515 &g->ecc.gr.tex_total_ded_pipe0_count, 495 &g->ecc.gr.tex_total_ded_pipe0_count);
516 &dev_attr_tex_ecc_total_ded_pipe0_count_array); 496
517 error |= gr_gp10b_ecc_stat_create(dev, 497 error |= nvgpu_gr_ecc_stat_create(dev,
518 0, 498 0,
519 "tex_ecc_unique_sec_pipe0_count", 499 "tex_ecc_unique_sec_pipe0_count",
520 &g->ecc.gr.tex_unique_sec_pipe0_count, 500 &g->ecc.gr.tex_unique_sec_pipe0_count);
521 &dev_attr_tex_ecc_unique_sec_pipe0_count_array); 501
522 error |= gr_gp10b_ecc_stat_create(dev, 502 error |= nvgpu_gr_ecc_stat_create(dev,
523 0, 503 0,
524 "tex_ecc_unique_ded_pipe0_count", 504 "tex_ecc_unique_ded_pipe0_count",
525 &g->ecc.gr.tex_unique_ded_pipe0_count, 505 &g->ecc.gr.tex_unique_ded_pipe0_count);
526 &dev_attr_tex_ecc_unique_ded_pipe0_count_array); 506
527 error |= gr_gp10b_ecc_stat_create(dev, 507 error |= nvgpu_gr_ecc_stat_create(dev,
528 0, 508 0,
529 "tex_ecc_total_sec_pipe1_count", 509 "tex_ecc_total_sec_pipe1_count",
530 &g->ecc.gr.tex_total_sec_pipe1_count, 510 &g->ecc.gr.tex_total_sec_pipe1_count);
531 &dev_attr_tex_ecc_total_sec_pipe1_count_array); 511
532 error |= gr_gp10b_ecc_stat_create(dev, 512 error |= nvgpu_gr_ecc_stat_create(dev,
533 0, 513 0,
534 "tex_ecc_total_ded_pipe1_count", 514 "tex_ecc_total_ded_pipe1_count",
535 &g->ecc.gr.tex_total_ded_pipe1_count, 515 &g->ecc.gr.tex_total_ded_pipe1_count);
536 &dev_attr_tex_ecc_total_ded_pipe1_count_array); 516
537 error |= gr_gp10b_ecc_stat_create(dev, 517 error |= nvgpu_gr_ecc_stat_create(dev,
538 0, 518 0,
539 "tex_ecc_unique_sec_pipe1_count", 519 "tex_ecc_unique_sec_pipe1_count",
540 &g->ecc.gr.tex_unique_sec_pipe1_count, 520 &g->ecc.gr.tex_unique_sec_pipe1_count);
541 &dev_attr_tex_ecc_unique_sec_pipe1_count_array); 521
542 error |= gr_gp10b_ecc_stat_create(dev, 522 error |= nvgpu_gr_ecc_stat_create(dev,
543 0, 523 0,
544 "tex_ecc_unique_ded_pipe1_count", 524 "tex_ecc_unique_ded_pipe1_count",
545 &g->ecc.gr.tex_unique_ded_pipe1_count, 525 &g->ecc.gr.tex_unique_ded_pipe1_count);
546 &dev_attr_tex_ecc_unique_ded_pipe1_count_array);
547 526
548 error |= gr_gp10b_ecc_stat_create(dev, 527 error |= nvgpu_gr_ecc_stat_create(dev,
549 2, 528 2,
550 "ecc_sec_count", 529 "ecc_sec_count",
551 &g->ecc.ltc.l2_sec_count, 530 &g->ecc.ltc.l2_sec_count);
552 &dev_attr_l2_ecc_sec_count_array); 531
553 error |= gr_gp10b_ecc_stat_create(dev, 532 error |= nvgpu_gr_ecc_stat_create(dev,
554 2, 533 2,
555 "ecc_ded_count", 534 "ecc_ded_count",
556 &g->ecc.ltc.l2_ded_count, 535 &g->ecc.ltc.l2_ded_count);
557 &dev_attr_l2_ecc_ded_count_array);
558 536
559 if (error) 537 if (error)
560 dev_err(dev, "Failed to create sysfs attributes!\n"); 538 dev_err(dev, "Failed to create sysfs attributes!\n");
@@ -567,67 +545,63 @@ void gr_gp10b_remove_sysfs(struct gk20a *g)
567 if (!g->ecc.gr.sm_lrf_single_err_count.counters) 545 if (!g->ecc.gr.sm_lrf_single_err_count.counters)
568 return; 546 return;
569 547
570 gr_gp10b_ecc_stat_remove(dev, 548 nvgpu_gr_ecc_stat_remove(dev,
571 0, 549 0,
572 &g->ecc.gr.sm_lrf_single_err_count, 550 &g->ecc.gr.sm_lrf_single_err_count);
573 dev_attr_sm_lrf_ecc_single_err_count_array); 551
574 gr_gp10b_ecc_stat_remove(dev, 552 nvgpu_gr_ecc_stat_remove(dev,
575 0, 553 0,
576 &g->ecc.gr.sm_lrf_double_err_count, 554 &g->ecc.gr.sm_lrf_double_err_count);
577 dev_attr_sm_lrf_ecc_double_err_count_array);
578 555
579 gr_gp10b_ecc_stat_remove(dev, 556 nvgpu_gr_ecc_stat_remove(dev,
580 0, 557 0,
581 &g->ecc.gr.sm_shm_sec_count, 558 &g->ecc.gr.sm_shm_sec_count);
582 dev_attr_sm_shm_ecc_sec_count_array); 559
583 gr_gp10b_ecc_stat_remove(dev, 560 nvgpu_gr_ecc_stat_remove(dev,
584 0, 561 0,
585 &g->ecc.gr.sm_shm_sed_count, 562 &g->ecc.gr.sm_shm_sed_count);
586 dev_attr_sm_shm_ecc_sed_count_array); 563
587 gr_gp10b_ecc_stat_remove(dev, 564 nvgpu_gr_ecc_stat_remove(dev,
588 0, 565 0,
589 &g->ecc.gr.sm_shm_ded_count, 566 &g->ecc.gr.sm_shm_ded_count);
590 dev_attr_sm_shm_ecc_ded_count_array);
591 567
592 gr_gp10b_ecc_stat_remove(dev, 568 nvgpu_gr_ecc_stat_remove(dev,
593 0, 569 0,
594 &g->ecc.gr.tex_total_sec_pipe0_count, 570 &g->ecc.gr.tex_total_sec_pipe0_count);
595 dev_attr_tex_ecc_total_sec_pipe0_count_array); 571
596 gr_gp10b_ecc_stat_remove(dev, 572 nvgpu_gr_ecc_stat_remove(dev,
597 0, 573 0,
598 &g->ecc.gr.tex_total_ded_pipe0_count, 574 &g->ecc.gr.tex_total_ded_pipe0_count);
599 dev_attr_tex_ecc_total_ded_pipe0_count_array); 575
600 gr_gp10b_ecc_stat_remove(dev, 576 nvgpu_gr_ecc_stat_remove(dev,
601 0, 577 0,
602 &g->ecc.gr.tex_unique_sec_pipe0_count, 578 &g->ecc.gr.tex_unique_sec_pipe0_count);
603 dev_attr_tex_ecc_unique_sec_pipe0_count_array); 579
604 gr_gp10b_ecc_stat_remove(dev, 580 nvgpu_gr_ecc_stat_remove(dev,
605 0, 581 0,
606 &g->ecc.gr.tex_unique_ded_pipe0_count, 582 &g->ecc.gr.tex_unique_ded_pipe0_count);
607 dev_attr_tex_ecc_unique_ded_pipe0_count_array); 583
608 gr_gp10b_ecc_stat_remove(dev, 584 nvgpu_gr_ecc_stat_remove(dev,
609 0, 585 0,
610 &g->ecc.gr.tex_total_sec_pipe1_count, 586 &g->ecc.gr.tex_total_sec_pipe1_count);
611 dev_attr_tex_ecc_total_sec_pipe1_count_array); 587
612 gr_gp10b_ecc_stat_remove(dev, 588 nvgpu_gr_ecc_stat_remove(dev,
613 0, 589 0,
614 &g->ecc.gr.tex_total_ded_pipe1_count, 590 &g->ecc.gr.tex_total_ded_pipe1_count);
615 dev_attr_tex_ecc_total_ded_pipe1_count_array); 591
616 gr_gp10b_ecc_stat_remove(dev, 592 nvgpu_gr_ecc_stat_remove(dev,
617 0, 593 0,
618 &g->ecc.gr.tex_unique_sec_pipe1_count, 594 &g->ecc.gr.tex_unique_sec_pipe1_count);
619 dev_attr_tex_ecc_unique_sec_pipe1_count_array); 595
620 gr_gp10b_ecc_stat_remove(dev, 596 nvgpu_gr_ecc_stat_remove(dev,
621 0, 597 0,
622 &g->ecc.gr.tex_unique_ded_pipe1_count, 598 &g->ecc.gr.tex_unique_ded_pipe1_count);
623 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
624 599
625 gr_gp10b_ecc_stat_remove(dev, 600 nvgpu_gr_ecc_stat_remove(dev,
626 2, 601 2,
627 &g->ecc.ltc.l2_sec_count, 602 &g->ecc.ltc.l2_sec_count);
628 dev_attr_l2_ecc_sec_count_array); 603
629 gr_gp10b_ecc_stat_remove(dev, 604 nvgpu_gr_ecc_stat_remove(dev,
630 2, 605 2,
631 &g->ecc.ltc.l2_ded_count, 606 &g->ecc.ltc.l2_ded_count);
632 dev_attr_l2_ecc_ded_count_array);
633} 607}
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
index f681fe4b..bf66762b 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
@@ -39,6 +39,7 @@
39 39
40#include "gp10b/platform_gp10b.h" 40#include "gp10b/platform_gp10b.h"
41#include "platform_gp10b_tegra.h" 41#include "platform_gp10b_tegra.h"
42#include "platform_ecc_sysfs.h"
42 43
43#include "os_linux.h" 44#include "os_linux.h"
44#include "platform_gk20a_tegra.h" 45#include "platform_gk20a_tegra.h"
@@ -261,41 +262,11 @@ struct gk20a_platform gv11b_tegra_platform = {
261 .secure_buffer_size = 667648, 262 .secure_buffer_size = 667648,
262}; 263};
263 264
264static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array;
265static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array;
266static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array;
267static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array;
268static struct device_attribute *dev_attr_sm_l1_data_ecc_corrected_err_count_array;
269static struct device_attribute *dev_attr_sm_l1_data_ecc_uncorrected_err_count_array;
270static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array;
271static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array;
272static struct device_attribute *dev_attr_gcc_l15_ecc_corrected_err_count_array;
273static struct device_attribute *dev_attr_gcc_l15_ecc_uncorrected_err_count_array;
274static struct device_attribute *dev_attr_mmu_l1tlb_ecc_corrected_err_count_array;
275static struct device_attribute *dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array;
276
277static struct device_attribute *dev_attr_fecs_ecc_corrected_err_count_array;
278static struct device_attribute *dev_attr_fecs_ecc_uncorrected_err_count_array;
279static struct device_attribute *dev_attr_gpccs_ecc_corrected_err_count_array;
280static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array;
281
282static struct device_attribute *dev_attr_l2_cache_ecc_corrected_err_count_array;
283static struct device_attribute *dev_attr_l2_cache_ecc_uncorrected_err_count_array;
284
285static struct device_attribute *dev_attr_mmu_l2tlb_ecc_corrected_err_count_array;
286static struct device_attribute *dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array;
287static struct device_attribute *dev_attr_mmu_hubtlb_ecc_corrected_err_count_array;
288static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array;
289static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array;
290static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array;
291
292static struct device_attribute *dev_attr_pmu_ecc_corrected_err_count_array;
293static struct device_attribute *dev_attr_pmu_ecc_uncorrected_err_count_array;
294
295void gr_gv11b_create_sysfs(struct gk20a *g) 265void gr_gv11b_create_sysfs(struct gk20a *g)
296{ 266{
297 struct device *dev = dev_from_gk20a(g); 267 struct device *dev = dev_from_gk20a(g);
298 int error = 0; 268 int error = 0;
269
299 /* This stat creation function is called on GR init. GR can get 270 /* This stat creation function is called on GR init. GR can get
300 initialized multiple times but we only need to create the ECC 271 initialized multiple times but we only need to create the ECC
301 stats once. Therefore, add the following check to avoid 272 stats once. Therefore, add the following check to avoid
@@ -305,210 +276,183 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
305 276
306 gr_gp10b_create_sysfs(g); 277 gr_gp10b_create_sysfs(g);
307 278
308 error |= gr_gp10b_ecc_stat_create(dev, 279 error |= nvgpu_gr_ecc_stat_create(dev,
309 0, 280 0,
310 "sm_l1_tag_ecc_corrected_err_count", 281 "sm_l1_tag_ecc_corrected_err_count",
311 &g->ecc.gr.sm_l1_tag_corrected_err_count, 282 &g->ecc.gr.sm_l1_tag_corrected_err_count);
312 &dev_attr_sm_l1_tag_ecc_corrected_err_count_array);
313 283
314 error |= gr_gp10b_ecc_stat_create(dev, 284 error |= nvgpu_gr_ecc_stat_create(dev,
315 0, 285 0,
316 "sm_l1_tag_ecc_uncorrected_err_count", 286 "sm_l1_tag_ecc_uncorrected_err_count",
317 &g->ecc.gr.sm_l1_tag_uncorrected_err_count, 287 &g->ecc.gr.sm_l1_tag_uncorrected_err_count);
318 &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array);
319 288
320 error |= gr_gp10b_ecc_stat_create(dev, 289 error |= nvgpu_gr_ecc_stat_create(dev,
321 0, 290 0,
322 "sm_cbu_ecc_corrected_err_count", 291 "sm_cbu_ecc_corrected_err_count",
323 &g->ecc.gr.sm_cbu_corrected_err_count, 292 &g->ecc.gr.sm_cbu_corrected_err_count);
324 &dev_attr_sm_cbu_ecc_corrected_err_count_array);
325 293
326 error |= gr_gp10b_ecc_stat_create(dev, 294 error |= nvgpu_gr_ecc_stat_create(dev,
327 0, 295 0,
328 "sm_cbu_ecc_uncorrected_err_count", 296 "sm_cbu_ecc_uncorrected_err_count",
329 &g->ecc.gr.sm_cbu_uncorrected_err_count, 297 &g->ecc.gr.sm_cbu_uncorrected_err_count);
330 &dev_attr_sm_cbu_ecc_uncorrected_err_count_array);
331 298
332 error |= gr_gp10b_ecc_stat_create(dev, 299 error |= nvgpu_gr_ecc_stat_create(dev,
333 0, 300 0,
334 "sm_l1_data_ecc_corrected_err_count", 301 "sm_l1_data_ecc_corrected_err_count",
335 &g->ecc.gr.sm_l1_data_corrected_err_count, 302 &g->ecc.gr.sm_l1_data_corrected_err_count);
336 &dev_attr_sm_l1_data_ecc_corrected_err_count_array);
337 303
338 error |= gr_gp10b_ecc_stat_create(dev, 304 error |= nvgpu_gr_ecc_stat_create(dev,
339 0, 305 0,
340 "sm_l1_data_ecc_uncorrected_err_count", 306 "sm_l1_data_ecc_uncorrected_err_count",
341 &g->ecc.gr.sm_l1_data_uncorrected_err_count, 307 &g->ecc.gr.sm_l1_data_uncorrected_err_count);
342 &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array);
343 308
344 error |= gr_gp10b_ecc_stat_create(dev, 309 error |= nvgpu_gr_ecc_stat_create(dev,
345 0, 310 0,
346 "sm_icache_ecc_corrected_err_count", 311 "sm_icache_ecc_corrected_err_count",
347 &g->ecc.gr.sm_icache_corrected_err_count, 312 &g->ecc.gr.sm_icache_corrected_err_count);
348 &dev_attr_sm_icache_ecc_corrected_err_count_array);
349 313
350 error |= gr_gp10b_ecc_stat_create(dev, 314 error |= nvgpu_gr_ecc_stat_create(dev,
351 0, 315 0,
352 "sm_icache_ecc_uncorrected_err_count", 316 "sm_icache_ecc_uncorrected_err_count",
353 &g->ecc.gr.sm_icache_uncorrected_err_count, 317 &g->ecc.gr.sm_icache_uncorrected_err_count);
354 &dev_attr_sm_icache_ecc_uncorrected_err_count_array);
355 318
356 error |= gr_gp10b_ecc_stat_create(dev, 319 error |= nvgpu_gr_ecc_stat_create(dev,
357 0, 320 0,
358 "gcc_l15_ecc_corrected_err_count", 321 "gcc_l15_ecc_corrected_err_count",
359 &g->ecc.gr.gcc_l15_corrected_err_count, 322 &g->ecc.gr.gcc_l15_corrected_err_count);
360 &dev_attr_gcc_l15_ecc_corrected_err_count_array);
361 323
362 error |= gr_gp10b_ecc_stat_create(dev, 324 error |= nvgpu_gr_ecc_stat_create(dev,
363 0, 325 0,
364 "gcc_l15_ecc_uncorrected_err_count", 326 "gcc_l15_ecc_uncorrected_err_count",
365 &g->ecc.gr.gcc_l15_uncorrected_err_count, 327 &g->ecc.gr.gcc_l15_uncorrected_err_count);
366 &dev_attr_gcc_l15_ecc_uncorrected_err_count_array);
367 328
368 error |= gp10b_ecc_stat_create(dev, 329 error |= nvgpu_ecc_stat_create(dev,
369 g->ltc_count, 330 g->ltc_count,
370 0, 331 0,
371 "ltc", 332 "ltc",
372 NULL, 333 NULL,
373 "l2_cache_uncorrected_err_count", 334 "l2_cache_uncorrected_err_count",
374 &g->ecc.ltc.l2_cache_uncorrected_err_count, 335 &g->ecc.ltc.l2_cache_uncorrected_err_count);
375 &dev_attr_l2_cache_ecc_uncorrected_err_count_array);
376 336
377 error |= gp10b_ecc_stat_create(dev, 337 error |= nvgpu_ecc_stat_create(dev,
378 g->ltc_count, 338 g->ltc_count,
379 0, 339 0,
380 "ltc", 340 "ltc",
381 NULL, 341 NULL,
382 "l2_cache_corrected_err_count", 342 "l2_cache_corrected_err_count",
383 &g->ecc.ltc.l2_cache_corrected_err_count, 343 &g->ecc.ltc.l2_cache_corrected_err_count);
384 &dev_attr_l2_cache_ecc_corrected_err_count_array);
385 344
386 error |= gp10b_ecc_stat_create(dev, 345 error |= nvgpu_ecc_stat_create(dev,
387 1, 346 1,
388 0, 347 0,
389 "gpc", 348 "gpc",
390 NULL, 349 NULL,
391 "fecs_ecc_uncorrected_err_count", 350 "fecs_ecc_uncorrected_err_count",
392 &g->ecc.gr.fecs_uncorrected_err_count, 351 &g->ecc.gr.fecs_uncorrected_err_count);
393 &dev_attr_fecs_ecc_uncorrected_err_count_array);
394 352
395 error |= gp10b_ecc_stat_create(dev, 353 error |= nvgpu_ecc_stat_create(dev,
396 1, 354 1,
397 0, 355 0,
398 "gpc", 356 "gpc",
399 NULL, 357 NULL,
400 "fecs_ecc_corrected_err_count", 358 "fecs_ecc_corrected_err_count",
401 &g->ecc.gr.fecs_corrected_err_count, 359 &g->ecc.gr.fecs_corrected_err_count);
402 &dev_attr_fecs_ecc_corrected_err_count_array);
403 360
404 error |= gp10b_ecc_stat_create(dev, 361 error |= nvgpu_ecc_stat_create(dev,
405 g->gr.gpc_count, 362 g->gr.gpc_count,
406 0, 363 0,
407 "gpc", 364 "gpc",
408 NULL, 365 NULL,
409 "gpccs_ecc_uncorrected_err_count", 366 "gpccs_ecc_uncorrected_err_count",
410 &g->ecc.gr.gpccs_uncorrected_err_count, 367 &g->ecc.gr.gpccs_uncorrected_err_count);
411 &dev_attr_gpccs_ecc_uncorrected_err_count_array);
412 368
413 error |= gp10b_ecc_stat_create(dev, 369 error |= nvgpu_ecc_stat_create(dev,
414 g->gr.gpc_count, 370 g->gr.gpc_count,
415 0, 371 0,
416 "gpc", 372 "gpc",
417 NULL, 373 NULL,
418 "gpccs_ecc_corrected_err_count", 374 "gpccs_ecc_corrected_err_count",
419 &g->ecc.gr.gpccs_corrected_err_count, 375 &g->ecc.gr.gpccs_corrected_err_count);
420 &dev_attr_gpccs_ecc_corrected_err_count_array);
421 376
422 error |= gp10b_ecc_stat_create(dev, 377 error |= nvgpu_ecc_stat_create(dev,
423 g->gr.gpc_count, 378 g->gr.gpc_count,
424 0, 379 0,
425 "gpc", 380 "gpc",
426 NULL, 381 NULL,
427 "mmu_l1tlb_ecc_uncorrected_err_count", 382 "mmu_l1tlb_ecc_uncorrected_err_count",
428 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, 383 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count);
429 &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array);
430 384
431 error |= gp10b_ecc_stat_create(dev, 385 error |= nvgpu_ecc_stat_create(dev,
432 g->gr.gpc_count, 386 g->gr.gpc_count,
433 0, 387 0,
434 "gpc", 388 "gpc",
435 NULL, 389 NULL,
436 "mmu_l1tlb_ecc_corrected_err_count", 390 "mmu_l1tlb_ecc_corrected_err_count",
437 &g->ecc.gr.mmu_l1tlb_corrected_err_count, 391 &g->ecc.gr.mmu_l1tlb_corrected_err_count);
438 &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array);
439 392
440 error |= gp10b_ecc_stat_create(dev, 393 error |= nvgpu_ecc_stat_create(dev,
441 1, 394 1,
442 0, 395 0,
443 "eng", 396 "eng",
444 NULL, 397 NULL,
445 "mmu_l2tlb_ecc_uncorrected_err_count", 398 "mmu_l2tlb_ecc_uncorrected_err_count",
446 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, 399 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count);
447 &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array);
448 400
449 error |= gp10b_ecc_stat_create(dev, 401 error |= nvgpu_ecc_stat_create(dev,
450 1, 402 1,
451 0, 403 0,
452 "eng", 404 "eng",
453 NULL, 405 NULL,
454 "mmu_l2tlb_ecc_corrected_err_count", 406 "mmu_l2tlb_ecc_corrected_err_count",
455 &g->ecc.fb.mmu_l2tlb_corrected_err_count, 407 &g->ecc.fb.mmu_l2tlb_corrected_err_count);
456 &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array);
457 408
458 error |= gp10b_ecc_stat_create(dev, 409 error |= nvgpu_ecc_stat_create(dev,
459 1, 410 1,
460 0, 411 0,
461 "eng", 412 "eng",
462 NULL, 413 NULL,
463 "mmu_hubtlb_ecc_uncorrected_err_count", 414 "mmu_hubtlb_ecc_uncorrected_err_count",
464 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, 415 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count);
465 &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array);
466 416
467 error |= gp10b_ecc_stat_create(dev, 417 error |= nvgpu_ecc_stat_create(dev,
468 1, 418 1,
469 0, 419 0,
470 "eng", 420 "eng",
471 NULL, 421 NULL,
472 "mmu_hubtlb_ecc_corrected_err_count", 422 "mmu_hubtlb_ecc_corrected_err_count",
473 &g->ecc.fb.mmu_hubtlb_corrected_err_count, 423 &g->ecc.fb.mmu_hubtlb_corrected_err_count);
474 &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array);
475 424
476 error |= gp10b_ecc_stat_create(dev, 425 error |= nvgpu_ecc_stat_create(dev,
477 1, 426 1,
478 0, 427 0,
479 "eng", 428 "eng",
480 NULL, 429 NULL,
481 "mmu_fillunit_ecc_uncorrected_err_count", 430 "mmu_fillunit_ecc_uncorrected_err_count",
482 &g->ecc.fb.mmu_fillunit_uncorrected_err_count, 431 &g->ecc.fb.mmu_fillunit_uncorrected_err_count);
483 &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array);
484 432
485 error |= gp10b_ecc_stat_create(dev, 433 error |= nvgpu_ecc_stat_create(dev,
486 1, 434 1,
487 0, 435 0,
488 "eng", 436 "eng",
489 NULL, 437 NULL,
490 "mmu_fillunit_ecc_corrected_err_count", 438 "mmu_fillunit_ecc_corrected_err_count",
491 &g->ecc.fb.mmu_fillunit_corrected_err_count, 439 &g->ecc.fb.mmu_fillunit_corrected_err_count);
492 &dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
493 440
494 error |= gp10b_ecc_stat_create(dev, 441 error |= nvgpu_ecc_stat_create(dev,
495 1, 442 1,
496 0, 443 0,
497 "eng", 444 "eng",
498 NULL, 445 NULL,
499 "pmu_ecc_uncorrected_err_count", 446 "pmu_ecc_uncorrected_err_count",
500 &g->ecc.pmu.pmu_uncorrected_err_count, 447 &g->ecc.pmu.pmu_uncorrected_err_count);
501 &dev_attr_pmu_ecc_uncorrected_err_count_array);
502 448
503 error |= gp10b_ecc_stat_create(dev, 449 error |= nvgpu_ecc_stat_create(dev,
504 1, 450 1,
505 0, 451 0,
506 "eng", 452 "eng",
507 NULL, 453 NULL,
508 "pmu_ecc_corrected_err_count", 454 "pmu_ecc_corrected_err_count",
509 &g->ecc.pmu.pmu_corrected_err_count, 455 &g->ecc.pmu.pmu_corrected_err_count);
510 &dev_attr_pmu_ecc_corrected_err_count_array);
511
512 456
513 if (error) 457 if (error)
514 dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); 458 dev_err(dev, "Failed to create gv11b sysfs attributes!\n");
@@ -522,133 +466,123 @@ void gr_gv11b_remove_sysfs(struct gk20a *g)
522 return; 466 return;
523 gr_gp10b_remove_sysfs(g); 467 gr_gp10b_remove_sysfs(g);
524 468
525 gr_gp10b_ecc_stat_remove(dev, 469 nvgpu_gr_ecc_stat_remove(dev,
526 0, 470 0,
527 &g->ecc.gr.sm_l1_tag_corrected_err_count, 471 &g->ecc.gr.sm_l1_tag_corrected_err_count);
528 dev_attr_sm_l1_tag_ecc_corrected_err_count_array);
529 472
530 gr_gp10b_ecc_stat_remove(dev, 473 nvgpu_gr_ecc_stat_remove(dev,
531 0, 474 0,
532 &g->ecc.gr.sm_l1_tag_uncorrected_err_count, 475 &g->ecc.gr.sm_l1_tag_uncorrected_err_count);
533 dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array);
534 476
535 gr_gp10b_ecc_stat_remove(dev, 477 nvgpu_gr_ecc_stat_remove(dev,
536 0, 478 0,
537 &g->ecc.gr.sm_cbu_corrected_err_count, 479 &g->ecc.gr.sm_cbu_corrected_err_count);
538 dev_attr_sm_cbu_ecc_corrected_err_count_array);
539 480
540 gr_gp10b_ecc_stat_remove(dev, 481 nvgpu_gr_ecc_stat_remove(dev,
541 0, 482 0,
542 &g->ecc.gr.sm_cbu_uncorrected_err_count, 483 &g->ecc.gr.sm_cbu_uncorrected_err_count);
543 dev_attr_sm_cbu_ecc_uncorrected_err_count_array);
544 484
545 gr_gp10b_ecc_stat_remove(dev, 485 nvgpu_gr_ecc_stat_remove(dev,
546 0, 486 0,
547 &g->ecc.gr.sm_l1_data_corrected_err_count, 487 &g->ecc.gr.sm_l1_data_corrected_err_count);
548 dev_attr_sm_l1_data_ecc_corrected_err_count_array);
549 488
550 gr_gp10b_ecc_stat_remove(dev, 489 nvgpu_gr_ecc_stat_remove(dev,
551 0, 490 0,
552 &g->ecc.gr.sm_l1_data_uncorrected_err_count, 491 &g->ecc.gr.sm_l1_data_uncorrected_err_count);
553 dev_attr_sm_l1_data_ecc_uncorrected_err_count_array);
554 492
555 gr_gp10b_ecc_stat_remove(dev, 493 nvgpu_gr_ecc_stat_remove(dev,
556 0, 494 0,
557 &g->ecc.gr.sm_icache_corrected_err_count, 495 &g->ecc.gr.sm_icache_corrected_err_count);
558 dev_attr_sm_icache_ecc_corrected_err_count_array);
559 496
560 gr_gp10b_ecc_stat_remove(dev, 497 nvgpu_gr_ecc_stat_remove(dev,
561 0, 498 0,
562 &g->ecc.gr.sm_icache_uncorrected_err_count, 499 &g->ecc.gr.sm_icache_uncorrected_err_count);
563 dev_attr_sm_icache_ecc_uncorrected_err_count_array);
564 500
565 gr_gp10b_ecc_stat_remove(dev, 501 nvgpu_gr_ecc_stat_remove(dev,
566 0, 502 0,
567 &g->ecc.gr.gcc_l15_corrected_err_count, 503 &g->ecc.gr.gcc_l15_corrected_err_count);
568 dev_attr_gcc_l15_ecc_corrected_err_count_array);
569 504
570 gr_gp10b_ecc_stat_remove(dev, 505 nvgpu_gr_ecc_stat_remove(dev,
571 0, 506 0,
572 &g->ecc.gr.gcc_l15_uncorrected_err_count, 507 &g->ecc.gr.gcc_l15_uncorrected_err_count);
573 dev_attr_gcc_l15_ecc_uncorrected_err_count_array);
574 508
575 gp10b_ecc_stat_remove(dev, 509 nvgpu_ecc_stat_remove(dev,
576 g->ltc_count, 510 g->ltc_count,
577 &g->ecc.ltc.l2_cache_uncorrected_err_count, 511 0,
578 dev_attr_l2_cache_ecc_uncorrected_err_count_array); 512 &g->ecc.ltc.l2_cache_uncorrected_err_count);
579 513
580 gp10b_ecc_stat_remove(dev, 514 nvgpu_ecc_stat_remove(dev,
581 g->ltc_count, 515 g->ltc_count,
582 &g->ecc.ltc.l2_cache_corrected_err_count, 516 0,
583 dev_attr_l2_cache_ecc_corrected_err_count_array); 517 &g->ecc.ltc.l2_cache_corrected_err_count);
584 518
585 gp10b_ecc_stat_remove(dev, 519 nvgpu_ecc_stat_remove(dev,
586 1, 520 1,
587 &g->ecc.gr.fecs_uncorrected_err_count, 521 0,
588 dev_attr_fecs_ecc_uncorrected_err_count_array); 522 &g->ecc.gr.fecs_uncorrected_err_count);
589 523
590 gp10b_ecc_stat_remove(dev, 524 nvgpu_ecc_stat_remove(dev,
591 1, 525 1,
592 &g->ecc.gr.fecs_corrected_err_count, 526 0,
593 dev_attr_fecs_ecc_corrected_err_count_array); 527 &g->ecc.gr.fecs_corrected_err_count);
594 528
595 gp10b_ecc_stat_remove(dev, 529 nvgpu_ecc_stat_remove(dev,
596 g->gr.gpc_count, 530 g->gr.gpc_count,
597 &g->ecc.gr.gpccs_uncorrected_err_count, 531 0,
598 dev_attr_gpccs_ecc_uncorrected_err_count_array); 532 &g->ecc.gr.gpccs_uncorrected_err_count);
599 533
600 gp10b_ecc_stat_remove(dev, 534 nvgpu_ecc_stat_remove(dev,
601 g->gr.gpc_count, 535 g->gr.gpc_count,
602 &g->ecc.gr.gpccs_corrected_err_count, 536 0,
603 dev_attr_gpccs_ecc_corrected_err_count_array); 537 &g->ecc.gr.gpccs_corrected_err_count);
604 538
605 gp10b_ecc_stat_remove(dev, 539 nvgpu_ecc_stat_remove(dev,
606 g->gr.gpc_count, 540 g->gr.gpc_count,
607 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, 541 0,
608 dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); 542 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count);
609 543
610 gp10b_ecc_stat_remove(dev, 544 nvgpu_ecc_stat_remove(dev,
611 g->gr.gpc_count, 545 g->gr.gpc_count,
612 &g->ecc.gr.mmu_l1tlb_corrected_err_count, 546 0,
613 dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); 547 &g->ecc.gr.mmu_l1tlb_corrected_err_count);
614 548
615 gp10b_ecc_stat_remove(dev, 549 nvgpu_ecc_stat_remove(dev,
616 1, 550 1,
617 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, 551 0,
618 dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); 552 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count);
619 553
620 gp10b_ecc_stat_remove(dev, 554 nvgpu_ecc_stat_remove(dev,
621 1, 555 1,
622 &g->ecc.fb.mmu_l2tlb_corrected_err_count, 556 0,
623 dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); 557 &g->ecc.fb.mmu_l2tlb_corrected_err_count);
624 558
625 gp10b_ecc_stat_remove(dev, 559 nvgpu_ecc_stat_remove(dev,
626 1, 560 1,
627 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, 561 0,
628 dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); 562 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count);
629 563
630 gp10b_ecc_stat_remove(dev, 564 nvgpu_ecc_stat_remove(dev,
631 1, 565 1,
632 &g->ecc.fb.mmu_hubtlb_corrected_err_count, 566 0,
633 dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); 567 &g->ecc.fb.mmu_hubtlb_corrected_err_count);
634 568
635 gp10b_ecc_stat_remove(dev, 569 nvgpu_ecc_stat_remove(dev,
636 1, 570 1,
637 &g->ecc.fb.mmu_fillunit_uncorrected_err_count, 571 0,
638 dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); 572 &g->ecc.fb.mmu_fillunit_uncorrected_err_count);
639 573
640 gp10b_ecc_stat_remove(dev, 574 nvgpu_ecc_stat_remove(dev,
641 1, 575 1,
642 &g->ecc.fb.mmu_fillunit_corrected_err_count, 576 0,
643 dev_attr_mmu_fillunit_ecc_corrected_err_count_array); 577 &g->ecc.fb.mmu_fillunit_corrected_err_count);
644 578
645 gp10b_ecc_stat_remove(dev, 579 nvgpu_ecc_stat_remove(dev,
646 1, 580 1,
647 &g->ecc.pmu.pmu_uncorrected_err_count, 581 0,
648 dev_attr_pmu_ecc_uncorrected_err_count_array); 582 &g->ecc.pmu.pmu_uncorrected_err_count);
649 583
650 gp10b_ecc_stat_remove(dev, 584 nvgpu_ecc_stat_remove(dev,
651 1, 585 1,
652 &g->ecc.pmu.pmu_corrected_err_count, 586 0,
653 dev_attr_pmu_ecc_corrected_err_count_array); 587 &g->ecc.pmu.pmu_corrected_err_count);
654} 588}
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
index af10f828..9c50a809 100644
--- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -30,6 +30,7 @@ struct gk20a_ecc_stat {
30 u32 count; 30 u32 count;
31#ifdef CONFIG_SYSFS 31#ifdef CONFIG_SYSFS
32 struct hlist_node hash_node; 32 struct hlist_node hash_node;
33 struct device_attribute *attr_array;
33#endif 34#endif
34}; 35};
35 36
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:25:34 -0400