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authorThomas Fleury <tfleury@nvidia.com>2018-03-26 14:42:42 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-28 16:32:18 -0400
commit8a64eea483d18ce603b049d5485e9f7a742da30b (patch)
treef2902bca25b7766fb159779721ecae6dddaf2b29
parent1557ee63edabe64c32226ce3f086dffbe2610c2a (diff)
gpu: nvgpu: fix priv error register reads
Current code does not compute priv error register offsets properly. This leads to invalid decoding of priv errors, and can also trigger additional priv errors. - add GPU_LIT_GPC_PRIV_STRIDE define - return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals - use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in g->ops.priv_ring.isr() to compute priv error register offsets. Bug 2093058 Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682118 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c3
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c3
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c4
-rw-r--r--drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c3
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c4
8 files changed, 22 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f64a2b96..95736d30 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -141,6 +141,7 @@ enum gk20a_cbc_op {
141#define GPU_LIT_GPFIFO_CLASS 34 141#define GPU_LIT_GPFIFO_CLASS 34
142#define GPU_LIT_I2M_CLASS 35 142#define GPU_LIT_I2M_CLASS 35
143#define GPU_LIT_DMA_COPY_CLASS 36 143#define GPU_LIT_DMA_COPY_CLASS 36
144#define GPU_LIT_GPC_PRIV_STRIDE 37
144 145
145#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) 146#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
146 147
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index 1d764ad2..ed5327cb 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -58,7 +58,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
58 u32 cmd; 58 u32 cmd;
59 s32 retry = 100; 59 s32 retry = 100;
60 u32 gpc; 60 u32 gpc;
61 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 61 u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
62 62
63 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) 63 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
64 return; 64 return;
@@ -80,10 +80,10 @@ void gk20a_priv_ring_isr(struct gk20a *g)
80 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { 80 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
81 if (status1 & BIT(gpc)) { 81 if (status1 & BIT(gpc)) {
82 gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, 82 gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
83 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), 83 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride),
84 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), 84 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride),
85 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), 85 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride),
86 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride)); 86 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride));
87 } 87 }
88 } 88 }
89 /* clear interrupt */ 89 /* clear interrupt */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 3c1970eb..b91795fa 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -172,6 +172,9 @@ int gm20b_get_litter_value(struct gk20a *g, int value)
172 case GPU_LIT_DMA_COPY_CLASS: 172 case GPU_LIT_DMA_COPY_CLASS:
173 ret = MAXWELL_DMA_COPY_A; 173 ret = MAXWELL_DMA_COPY_A;
174 break; 174 break;
175 case GPU_LIT_GPC_PRIV_STRIDE:
176 ret = proj_gpc_priv_stride_v();
177 break;
175 default: 178 default:
176 nvgpu_err(g, "Missing definition %d", value); 179 nvgpu_err(g, "Missing definition %d", value);
177 BUG(); 180 BUG();
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 84e72e98..dbea8033 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -198,6 +198,9 @@ static int gp106_get_litter_value(struct gk20a *g, int value)
198 case GPU_LIT_DMA_COPY_CLASS: 198 case GPU_LIT_DMA_COPY_CLASS:
199 ret = PASCAL_DMA_COPY_A; 199 ret = PASCAL_DMA_COPY_A;
200 break; 200 break;
201 case GPU_LIT_GPC_PRIV_STRIDE:
202 ret = proj_gpc_priv_stride_v();
203 break;
201 default: 204 default:
202 BUG(); 205 BUG();
203 break; 206 break;
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 825d11e5..dd413c5a 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -181,7 +181,9 @@ int gp10b_get_litter_value(struct gk20a *g, int value)
181 case GPU_LIT_DMA_COPY_CLASS: 181 case GPU_LIT_DMA_COPY_CLASS:
182 ret = PASCAL_DMA_COPY_A; 182 ret = PASCAL_DMA_COPY_A;
183 break; 183 break;
184 184 case GPU_LIT_GPC_PRIV_STRIDE:
185 ret = proj_gpc_priv_stride_v();
186 break;
185 default: 187 default:
186 nvgpu_err(g, "Missing definition %d", value); 188 nvgpu_err(g, "Missing definition %d", value);
187 BUG(); 189 BUG();
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
index e7777871..0fac76f2 100644
--- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
@@ -145,7 +145,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
145 } 145 }
146 146
147 if (status1) { 147 if (status1) {
148 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 148 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
149 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { 149 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
150 offset = gpc * gpc_stride; 150 offset = gpc * gpc_stride;
151 if (status1 & BIT(gpc)) { 151 if (status1 & BIT(gpc)) {
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index cb7bca3f..b0caf9a6 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -232,6 +232,9 @@ static int gv100_get_litter_value(struct gk20a *g, int value)
232 case GPU_LIT_DMA_COPY_CLASS: 232 case GPU_LIT_DMA_COPY_CLASS:
233 ret = VOLTA_DMA_COPY_A; 233 ret = VOLTA_DMA_COPY_A;
234 break; 234 break;
235 case GPU_LIT_GPC_PRIV_STRIDE:
236 ret = proj_gpc_priv_stride_v();
237 break;
235 default: 238 default:
236 break; 239 break;
237 } 240 }
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 94aa2dc4..ee3fc3de 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -209,7 +209,9 @@ int gv11b_get_litter_value(struct gk20a *g, int value)
209 case GPU_LIT_DMA_COPY_CLASS: 209 case GPU_LIT_DMA_COPY_CLASS:
210 ret = VOLTA_DMA_COPY_A; 210 ret = VOLTA_DMA_COPY_A;
211 break; 211 break;
212 212 case GPU_LIT_GPC_PRIV_STRIDE:
213 ret = proj_gpc_priv_stride_v();
214 break;
213 default: 215 default:
214 nvgpu_err(g, "Missing definition %d", value); 216 nvgpu_err(g, "Missing definition %d", value);
215 BUG(); 217 BUG();