gpu: nvgpu: Add nvdec falcon support

 - Added "nvgpu_flacon  nvdec_flcn" member to gk20a
 - Added base address & flacon id of NVDEC falcon
 - Included nvdec falcon to access common falcon code
 - Enabled nvdec falcon support for GP106
 - Disabled nvdec falcon support for iGPU
 - Made call to enable nvdec falcon support if supported

Change-Id: Ia928d082275a720e4e8c6852384e489c8ec444f8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 3d80aeff295bad8365af6022555ad151f1a32cf6)
Reviewed-on: https://git-master.nvidia.com/r/1564305
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 18 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index e0b5554d..99b2c249 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -321,6 +321,10 @@ void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id)
                 flcn = &g->gpccs_flcn;
                 flcn->flcn_id = flcn_id;
                 break;
+        case FALCON_ID_NVDEC:
+                flcn = &g->nvdec_flcn;
+                flcn->flcn_id = flcn_id;
+                break;
         default:
                 nvgpu_err(g, "Invalid/Unsupported falcon ID %x", flcn_id);
                 break;
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index b83d2dc0..8d459903 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -641,6 +641,11 @@ void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
                 flcn->is_falcon_supported = true;
                 flcn->is_interrupt_enabled = false;
         break;
+        case FALCON_ID_NVDEC:
+                flcn->flcn_base = FALCON_NVDEC_BASE;
+                flcn->is_falcon_supported = false;
+                flcn->is_interrupt_enabled = false;
+        break;
         default:
                 flcn->is_falcon_supported = false;
                 nvgpu_err(g, "Invalid flcn request");
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 02baf683..d203a335 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -164,6 +164,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
         /* init interface layer support for PMU falcon */
         nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
         nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
+        nvgpu_flcn_sw_init(g, FALCON_ID_NVDEC);
 
         if (g->ops.bios.init)
                 err = g->ops.bios.init(g);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 1efa920c..3fcad1cf 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1075,6 +1075,7 @@ struct gk20a {
         struct nvgpu_falcon sec2_flcn;
         struct nvgpu_falcon fecs_flcn;
         struct nvgpu_falcon gpccs_flcn;
+        struct nvgpu_falcon nvdec_flcn;
         struct clk_gk20a clk;
         struct fifo_gk20a fifo;
         struct gr_gk20a gr;
diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.c b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
index 889cf324..7949edb7 100644
--- a/drivers/gpu/nvgpu/gp106/flcn_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
@@ -74,6 +74,11 @@ void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
                 flcn->is_falcon_supported = true;
                 flcn->is_interrupt_enabled = false;
         break;
+        case FALCON_ID_NVDEC:
+                flcn->flcn_base = FALCON_NVDEC_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = true;
+        break;
         default:
                 flcn->is_falcon_supported = false;
                 nvgpu_err(g, "Invalid flcn request");
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 72c74784..888d8e70 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -32,11 +32,13 @@
 #define FALCON_ID_PMU       (0)
 #define FALCON_ID_FECS      (2)
 #define FALCON_ID_GPCCS     (3)
+#define FALCON_ID_NVDEC     (4)
 #define FALCON_ID_SEC2      (7)
 
 /*
  * Falcon Base address Defines
  */
+#define FALCON_NVDEC_BASE  0x00084000
 #define FALCON_PWR_BASE    0x0010a000
 #define FALCON_SEC_BASE    0x00087000
 #define FALCON_FECS_BASE   0x00409000