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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-06 15:37:10 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 20:45:30 -0400
commit876953fbb85f9440bbcc1d7d59435593886b53c4 (patch)
tree9690ee5598b83fcfa222592eeb2e3bb45389f3a6
parentda03aa782535e77e221a3c27b0676fe9c1c7980c (diff)
gpu: nvgpu: Move FB MMU query to FB HAL
Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/gm20b/fb_gm20b.c20
-rw-r--r--drivers/gpu/nvgpu/gm20b/fb_gm20b.h4
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c12
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c4
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c4
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c4
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c9
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c4
10 files changed, 57 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 4f02ce23..23ed2f15 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -505,6 +505,10 @@ struct gpu_ops {
505 void (*init_kind_attr)(struct gk20a *g); 505 void (*init_kind_attr)(struct gk20a *g);
506 void (*set_mmu_page_size)(struct gk20a *g); 506 void (*set_mmu_page_size)(struct gk20a *g);
507 bool (*set_use_full_comp_tag_line)(struct gk20a *g); 507 bool (*set_use_full_comp_tag_line)(struct gk20a *g);
508 u32 (*mmu_ctrl)(struct gk20a *g);
509 u32 (*mmu_debug_ctrl)(struct gk20a *g);
510 u32 (*mmu_debug_wr)(struct gk20a *g);
511 u32 (*mmu_debug_rd)(struct gk20a *g);
508 512
509 /* 513 /*
510 * Compression tag line coverage. When mapping a compressible 514 * Compression tag line coverage. When mapping a compressible
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
index 2ca8d86c..37a7944b 100644
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
@@ -68,6 +68,26 @@ bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
68 return true; 68 return true;
69} 69}
70 70
71u32 gm20b_fb_mmu_ctrl(struct gk20a *g)
72{
73 return gk20a_readl(g, fb_mmu_ctrl_r());
74}
75
76u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g)
77{
78 return gk20a_readl(g, fb_mmu_debug_ctrl_r());
79}
80
81u32 gm20b_fb_mmu_debug_wr(struct gk20a *g)
82{
83 return gk20a_readl(g, fb_mmu_debug_wr_r());
84}
85
86u32 gm20b_fb_mmu_debug_rd(struct gk20a *g)
87{
88 return gk20a_readl(g, fb_mmu_debug_rd_r());
89}
90
71unsigned int gm20b_fb_compression_page_size(struct gk20a *g) 91unsigned int gm20b_fb_compression_page_size(struct gk20a *g)
72{ 92{
73 return SZ_128K; 93 return SZ_128K;
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h
index 1d1d5899..1a5e9187 100644
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h
@@ -29,6 +29,10 @@ struct gk20a;
29void fb_gm20b_init_fs_state(struct gk20a *g); 29void fb_gm20b_init_fs_state(struct gk20a *g);
30void gm20b_fb_set_mmu_page_size(struct gk20a *g); 30void gm20b_fb_set_mmu_page_size(struct gk20a *g);
31bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g); 31bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g);
32u32 gm20b_fb_mmu_ctrl(struct gk20a *g);
33u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g);
34u32 gm20b_fb_mmu_debug_wr(struct gk20a *g);
35u32 gm20b_fb_mmu_debug_rd(struct gk20a *g);
32unsigned int gm20b_fb_compression_page_size(struct gk20a *g); 36unsigned int gm20b_fb_compression_page_size(struct gk20a *g);
33unsigned int gm20b_fb_compressible_page_size(struct gk20a *g); 37unsigned int gm20b_fb_compressible_page_size(struct gk20a *g);
34u32 gm20b_fb_compression_align_mask(struct gk20a *g); 38u32 gm20b_fb_compression_align_mask(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 85da0d35..32ab58c1 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -36,7 +36,6 @@
36 36
37#include <nvgpu/hw/gm20b/hw_gr_gm20b.h> 37#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
38#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> 38#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
39#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
40#include <nvgpu/hw/gm20b/hw_top_gm20b.h> 39#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
41#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h> 40#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h>
42#include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> 41#include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h>
@@ -49,7 +48,7 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
49 48
50 nvgpu_log_info(g, "initialize gpc mmu"); 49 nvgpu_log_info(g, "initialize gpc mmu");
51 50
52 temp = gk20a_readl(g, fb_mmu_ctrl_r()); 51 temp = g->ops.fb.mmu_ctrl(g);
53 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | 52 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
54 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | 53 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
55 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() | 54 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
@@ -65,14 +64,13 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
65 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); 64 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
66 65
67 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), 66 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
68 gk20a_readl(g, fb_mmu_debug_ctrl_r())); 67 g->ops.fb.mmu_debug_ctrl(g));
69 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), 68 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
70 gk20a_readl(g, fb_mmu_debug_wr_r())); 69 g->ops.fb.mmu_debug_wr(g));
71 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), 70 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
72 gk20a_readl(g, fb_mmu_debug_rd_r())); 71 g->ops.fb.mmu_debug_rd(g));
73 72
74 gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), 73 gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), g->ltc_count);
75 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
76} 74}
77 75
78void gr_gm20b_bundle_cb_defaults(struct gk20a *g) 76void gr_gm20b_bundle_cb_defaults(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 798b5f06..02355450 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -340,6 +340,10 @@ static const struct gpu_ops gm20b_ops = {
340 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 340 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
341 .set_use_full_comp_tag_line = 341 .set_use_full_comp_tag_line =
342 gm20b_fb_set_use_full_comp_tag_line, 342 gm20b_fb_set_use_full_comp_tag_line,
343 .mmu_ctrl = gm20b_fb_mmu_ctrl,
344 .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
345 .mmu_debug_wr = gm20b_fb_mmu_debug_wr,
346 .mmu_debug_rd = gm20b_fb_mmu_debug_rd,
343 .compression_page_size = gm20b_fb_compression_page_size, 347 .compression_page_size = gm20b_fb_compression_page_size,
344 .compressible_page_size = gm20b_fb_compressible_page_size, 348 .compressible_page_size = gm20b_fb_compressible_page_size,
345 .compression_align_mask = gm20b_fb_compression_align_mask, 349 .compression_align_mask = gm20b_fb_compression_align_mask,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 9427d3bf..75e2f5a1 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -411,6 +411,10 @@ static const struct gpu_ops gp106_ops = {
411 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 411 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
412 .set_use_full_comp_tag_line = 412 .set_use_full_comp_tag_line =
413 gm20b_fb_set_use_full_comp_tag_line, 413 gm20b_fb_set_use_full_comp_tag_line,
414 .mmu_ctrl = gm20b_fb_mmu_ctrl,
415 .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
416 .mmu_debug_wr = gm20b_fb_mmu_debug_wr,
417 .mmu_debug_rd = gm20b_fb_mmu_debug_rd,
414 .compression_page_size = gp10b_fb_compression_page_size, 418 .compression_page_size = gp10b_fb_compression_page_size,
415 .compressible_page_size = gp10b_fb_compressible_page_size, 419 .compressible_page_size = gp10b_fb_compressible_page_size,
416 .compression_align_mask = gm20b_fb_compression_align_mask, 420 .compression_align_mask = gm20b_fb_compression_align_mask,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a1c32a5f..a40608df 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -374,6 +374,10 @@ static const struct gpu_ops gp10b_ops = {
374 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 374 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
375 .set_use_full_comp_tag_line = 375 .set_use_full_comp_tag_line =
376 gm20b_fb_set_use_full_comp_tag_line, 376 gm20b_fb_set_use_full_comp_tag_line,
377 .mmu_ctrl = gm20b_fb_mmu_ctrl,
378 .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
379 .mmu_debug_wr = gm20b_fb_mmu_debug_wr,
380 .mmu_debug_rd = gm20b_fb_mmu_debug_rd,
377 .compression_page_size = gp10b_fb_compression_page_size, 381 .compression_page_size = gp10b_fb_compression_page_size,
378 .compressible_page_size = gp10b_fb_compressible_page_size, 382 .compressible_page_size = gp10b_fb_compressible_page_size,
379 .compression_align_mask = gm20b_fb_compression_align_mask, 383 .compression_align_mask = gm20b_fb_compression_align_mask,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 00007044..07c71a04 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -461,6 +461,10 @@ static const struct gpu_ops gv100_ops = {
461 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 461 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
462 .set_use_full_comp_tag_line = 462 .set_use_full_comp_tag_line =
463 gm20b_fb_set_use_full_comp_tag_line, 463 gm20b_fb_set_use_full_comp_tag_line,
464 .mmu_ctrl = gm20b_fb_mmu_ctrl,
465 .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
466 .mmu_debug_wr = gm20b_fb_mmu_debug_wr,
467 .mmu_debug_rd = gm20b_fb_mmu_debug_rd,
464 .compression_page_size = gp10b_fb_compression_page_size, 468 .compression_page_size = gp10b_fb_compression_page_size,
465 .compressible_page_size = gp10b_fb_compressible_page_size, 469 .compressible_page_size = gp10b_fb_compressible_page_size,
466 .compression_align_mask = gm20b_fb_compression_align_mask, 470 .compression_align_mask = gm20b_fb_compression_align_mask,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index ef482ba8..6ceaa47a 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -57,7 +57,6 @@
57#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 57#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
58#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> 58#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
59#include <nvgpu/hw/gv11b/hw_therm_gv11b.h> 59#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
60#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
61#include <nvgpu/hw/gv11b/hw_perf_gv11b.h> 60#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
62 61
63#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 62#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100
@@ -4248,7 +4247,7 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
4248 4247
4249 nvgpu_log_info(g, "initialize gpc mmu"); 4248 nvgpu_log_info(g, "initialize gpc mmu");
4250 4249
4251 temp = gk20a_readl(g, fb_mmu_ctrl_r()); 4250 temp = g->ops.fb.mmu_ctrl(g);
4252 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | 4251 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
4253 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | 4252 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
4254 gr_gpcs_pri_mmu_ctrl_vol_fault_m() | 4253 gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
@@ -4269,11 +4268,11 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
4269 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); 4268 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
4270 4269
4271 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), 4270 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
4272 gk20a_readl(g, fb_mmu_debug_ctrl_r())); 4271 g->ops.fb.mmu_debug_ctrl(g));
4273 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), 4272 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
4274 gk20a_readl(g, fb_mmu_debug_wr_r())); 4273 g->ops.fb.mmu_debug_wr(g));
4275 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), 4274 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
4276 gk20a_readl(g, fb_mmu_debug_rd_r())); 4275 g->ops.fb.mmu_debug_rd(g));
4277} 4276}
4278 4277
4279int gr_gv11b_init_preemption_state(struct gk20a *g) 4278int gr_gv11b_init_preemption_state(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 5bfa85da..6132a2dd 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -429,6 +429,10 @@ static const struct gpu_ops gv11b_ops = {
429 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 429 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
430 .set_use_full_comp_tag_line = 430 .set_use_full_comp_tag_line =
431 gm20b_fb_set_use_full_comp_tag_line, 431 gm20b_fb_set_use_full_comp_tag_line,
432 .mmu_ctrl = gm20b_fb_mmu_ctrl,
433 .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
434 .mmu_debug_wr = gm20b_fb_mmu_debug_wr,
435 .mmu_debug_rd = gm20b_fb_mmu_debug_rd,
432 .compression_page_size = gp10b_fb_compression_page_size, 436 .compression_page_size = gp10b_fb_compression_page_size,
433 .compressible_page_size = gp10b_fb_compressible_page_size, 437 .compressible_page_size = gp10b_fb_compressible_page_size,
434 .compression_align_mask = gm20b_fb_compression_align_mask, 438 .compression_align_mask = gm20b_fb_compression_align_mask,