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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 15:09:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-07 16:48:24 -0400
commit86ecddf68734e4a938eda351f4dde11ab507de3f (patch)
tree3a8d89ace77fc3427da6243c81f224883954e8e9
parentbb72b7e2ed215b26e1d9b94534c24ab4cfa52801 (diff)
gpu: nvgpu: gp106: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I18955b4c46c082883ee0bf589ab17cd66ab0add2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457346 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gp106/acr_gp106.c21
-rw-r--r--drivers/gpu/nvgpu/gp106/clk_gp106.c3
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c2
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c12
-rw-r--r--drivers/gpu/nvgpu/gp106/pmu_gp106.c9
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.c14
-rw-r--r--drivers/gpu/nvgpu/gp106/therm_gp106.c9
-rw-r--r--drivers/gpu/nvgpu/gp106/xve_gp106.c2
8 files changed, 30 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 631f9891..26c8ab53 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -150,7 +150,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
150 pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE, 150 pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE,
151 NVGPU_REQUEST_FIRMWARE_NO_SOC); 151 NVGPU_REQUEST_FIRMWARE_NO_SOC);
152 if (!pmu_fw) { 152 if (!pmu_fw) {
153 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!"); 153 nvgpu_err(g, "failed to load pmu ucode!!");
154 return -ENOENT; 154 return -ENOENT;
155 } 155 }
156 g->acr.pmu_fw = pmu_fw; 156 g->acr.pmu_fw = pmu_fw;
@@ -160,14 +160,14 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
160 pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC, 160 pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC,
161 NVGPU_REQUEST_FIRMWARE_NO_SOC); 161 NVGPU_REQUEST_FIRMWARE_NO_SOC);
162 if (!pmu_desc) { 162 if (!pmu_desc) {
163 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!"); 163 nvgpu_err(g, "failed to load pmu ucode desc!!");
164 err = -ENOENT; 164 err = -ENOENT;
165 goto release_img_fw; 165 goto release_img_fw;
166 } 166 }
167 pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG, 167 pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG,
168 NVGPU_REQUEST_FIRMWARE_NO_SOC); 168 NVGPU_REQUEST_FIRMWARE_NO_SOC);
169 if (!pmu_sig) { 169 if (!pmu_sig) {
170 gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!"); 170 nvgpu_err(g, "failed to load pmu sig!!");
171 err = -ENOENT; 171 err = -ENOENT;
172 goto release_desc; 172 goto release_desc;
173 } 173 }
@@ -177,8 +177,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
177 177
178 err = gk20a_init_pmu(pmu); 178 err = gk20a_init_pmu(pmu);
179 if (err) { 179 if (err) {
180 gk20a_err(dev_from_gk20a(g), 180 nvgpu_err(g, "failed to set function pointers");
181 "failed to set function pointers\n");
182 goto release_sig; 181 goto release_sig;
183 } 182 }
184 183
@@ -229,11 +228,11 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
229 NVGPU_REQUEST_FIRMWARE_NO_SOC); 228 NVGPU_REQUEST_FIRMWARE_NO_SOC);
230 break; 229 break;
231 default: 230 default:
232 gk20a_err(g->dev, "no support for GPUID %x", ver); 231 nvgpu_err(g, "no support for GPUID %x", ver);
233 } 232 }
234 233
235 if (!fecs_sig) { 234 if (!fecs_sig) {
236 gk20a_err(dev_from_gk20a(g), "failed to load fecs sig"); 235 nvgpu_err(g, "failed to load fecs sig");
237 return -ENOENT; 236 return -ENOENT;
238 } 237 }
239 lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1)); 238 lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
@@ -315,11 +314,11 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
315 NVGPU_REQUEST_FIRMWARE_NO_SOC); 314 NVGPU_REQUEST_FIRMWARE_NO_SOC);
316 break; 315 break;
317 default: 316 default:
318 gk20a_err(g->dev, "no support for GPUID %x", ver); 317 nvgpu_err(g, "no support for GPUID %x", ver);
319 } 318 }
320 319
321 if (!gpccs_sig) { 320 if (!gpccs_sig) {
322 gk20a_err(dev_from_gk20a(g), "failed to load gpccs sig"); 321 nvgpu_err(g, "failed to load gpccs sig");
323 return -ENOENT; 322 return -ENOENT;
324 } 323 }
325 lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1)); 324 lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
@@ -1067,7 +1066,7 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g)
1067 GM20B_HSBIN_PMU_UCODE_IMAGE, 1066 GM20B_HSBIN_PMU_UCODE_IMAGE,
1068 NVGPU_REQUEST_FIRMWARE_NO_SOC); 1067 NVGPU_REQUEST_FIRMWARE_NO_SOC);
1069 if (!acr_fw) { 1068 if (!acr_fw) {
1070 gk20a_err(dev_from_gk20a(g), "pmu ucode get fail"); 1069 nvgpu_err(g, "pmu ucode get fail");
1071 return -ENOENT; 1070 return -ENOENT;
1072 } 1071 }
1073 acr->acr_fw = acr_fw; 1072 acr->acr_fw = acr_fw;
@@ -1090,7 +1089,7 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g)
1090 acr->fw_hdr->patch_loc), 1089 acr->fw_hdr->patch_loc),
1091 (u32 *)(acr_fw->data + 1090 (u32 *)(acr_fw->data +
1092 acr->fw_hdr->patch_sig)) < 0) { 1091 acr->fw_hdr->patch_sig)) < 0) {
1093 gk20a_err(dev_from_gk20a(g), "patch signatures fail"); 1092 nvgpu_err(g, "patch signatures fail");
1094 err = -1; 1093 err = -1;
1095 goto err_release_acr_fw; 1094 goto err_release_acr_fw;
1096 } 1095 }
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index 8bc47ead..262fd63c 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -192,8 +192,7 @@ static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
192 } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr))); 192 } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr)));
193 193
194 if (!retries) { 194 if (!retries) {
195 gk20a_err(dev_from_gk20a(g), 195 nvgpu_err(g, "unable to settle counter reset, bailing");
196 "unable to settle counter reset, bailing");
197 goto read_err; 196 goto read_err;
198 } 197 }
199 /* Program counter */ 198 /* Program counter */
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
index 419c71df..3a49cc60 100644
--- a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
@@ -30,7 +30,7 @@ static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name)
30 GP106_NETLIST_IMAGE_FW_NAME); 30 GP106_NETLIST_IMAGE_FW_NAME);
31 break; 31 break;
32 default: 32 default:
33 gk20a_err(g->dev, "no support for GPUID %x", ver); 33 nvgpu_err(g, "no support for GPUID %x", ver);
34 } 34 }
35 35
36 return 0; 36 return 0;
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index a804f9bb..08d6ec28 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -167,8 +167,7 @@ static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
167 g->gr.t18x.ctx_vars.preempt_image_size, 167 g->gr.t18x.ctx_vars.preempt_image_size,
168 &gr_ctx->t18x.preempt_ctxsw_buffer); 168 &gr_ctx->t18x.preempt_ctxsw_buffer);
169 if (err) { 169 if (err) {
170 gk20a_err(dev_from_gk20a(g), 170 nvgpu_err(g, "cannot allocate preempt buffer");
171 "cannot allocate preempt buffer");
172 goto fail; 171 goto fail;
173 } 172 }
174 173
@@ -176,8 +175,7 @@ static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
176 spill_size, 175 spill_size,
177 &gr_ctx->t18x.spill_ctxsw_buffer); 176 &gr_ctx->t18x.spill_ctxsw_buffer);
178 if (err) { 177 if (err) {
179 gk20a_err(dev_from_gk20a(g), 178 nvgpu_err(g, "cannot allocate spill buffer");
180 "cannot allocate spill buffer");
181 goto fail_free_preempt; 179 goto fail_free_preempt;
182 } 180 }
183 181
@@ -185,8 +183,7 @@ static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
185 attrib_cb_size, 183 attrib_cb_size,
186 &gr_ctx->t18x.betacb_ctxsw_buffer); 184 &gr_ctx->t18x.betacb_ctxsw_buffer);
187 if (err) { 185 if (err) {
188 gk20a_err(dev_from_gk20a(g), 186 nvgpu_err(g, "cannot allocate beta buffer");
189 "cannot allocate beta buffer");
190 goto fail_free_spill; 187 goto fail_free_spill;
191 } 188 }
192 189
@@ -194,8 +191,7 @@ static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
194 pagepool_size, 191 pagepool_size,
195 &gr_ctx->t18x.pagepool_ctxsw_buffer); 192 &gr_ctx->t18x.pagepool_ctxsw_buffer);
196 if (err) { 193 if (err) {
197 gk20a_err(dev_from_gk20a(g), 194 nvgpu_err(g, "cannot allocate page pool");
198 "cannot allocate page pool");
199 goto fail_free_betacb; 195 goto fail_free_betacb;
200 } 196 }
201 197
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index a2eef6ff..cadbd308 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -77,7 +77,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
77 gk20a_writel(g, pwr_falcon_engine_r(), 77 gk20a_writel(g, pwr_falcon_engine_r(),
78 pwr_falcon_engine_reset_true_f()); 78 pwr_falcon_engine_reset_true_f());
79 gk20a_readl(g, pwr_falcon_engine_r()); 79 gk20a_readl(g, pwr_falcon_engine_r());
80 gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); 80 nvgpu_err(g, "Falcon mem scrubbing timeout");
81 return -ETIMEDOUT; 81 return -ETIMEDOUT;
82 } else { 82 } else {
83 /* DISBALE */ 83 /* DISBALE */
@@ -202,7 +202,7 @@ static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg,
202 gk20a_dbg_fn(""); 202 gk20a_dbg_fn("");
203 203
204 if (status != 0) { 204 if (status != 0) {
205 gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted"); 205 nvgpu_err(g, "PG PARAM cmd aborted");
206 return; 206 return;
207 } 207 }
208 208
@@ -222,7 +222,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
222 222
223 status = init_rppg(g); 223 status = init_rppg(g);
224 if (status != 0) { 224 if (status != 0) {
225 gk20a_err(dev_from_gk20a(g), "RPPG init Failed"); 225 nvgpu_err(g, "RPPG init Failed");
226 return -1; 226 return -1;
227 } 227 }
228 228
@@ -386,8 +386,7 @@ static int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
386 &g->ops.pmu.lspmuwprinitdone, 1); 386 &g->ops.pmu.lspmuwprinitdone, 1);
387 /* check again if it still not ready indicate an error */ 387 /* check again if it still not ready indicate an error */
388 if (!g->ops.pmu.lspmuwprinitdone) { 388 if (!g->ops.pmu.lspmuwprinitdone) {
389 gk20a_err(dev_from_gk20a(g), 389 nvgpu_err(g, "PMU not ready to load LSF");
390 "PMU not ready to load LSF");
391 return -ETIMEDOUT; 390 return -ETIMEDOUT;
392 } 391 }
393 } 392 }
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 5a331480..cc1e91f6 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -72,7 +72,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
72 } while (!nvgpu_timeout_expired(&to)); 72 } while (!nvgpu_timeout_expired(&to));
73 73
74 if (completion) { 74 if (completion) {
75 gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); 75 nvgpu_err(g, "ACR boot timed out");
76 return completion; 76 return completion;
77 } 77 }
78 78
@@ -81,8 +81,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
81 data = gk20a_readl(g, psec_falcon_mailbox0_r()); 81 data = gk20a_readl(g, psec_falcon_mailbox0_r());
82 if (data) { 82 if (data) {
83 83
84 gk20a_err(dev_from_gk20a(g), 84 nvgpu_err(g, "ACR boot failed, err %x", data);
85 "ACR boot failed, err %x", data);
86 completion = -EAGAIN; 85 completion = -EAGAIN;
87 } 86 }
88 87
@@ -100,14 +99,12 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
100 u32 *src_u32 = (u32*)src; 99 u32 *src_u32 = (u32*)src;
101 100
102 if (size == 0) { 101 if (size == 0) {
103 gk20a_err(dev_from_gk20a(g), 102 nvgpu_err(g, "size is zero");
104 "size is zero");
105 return; 103 return;
106 } 104 }
107 105
108 if (dst & 0x3) { 106 if (dst & 0x3) {
109 gk20a_err(dev_from_gk20a(g), 107 nvgpu_err(g, "dst (0x%08x) not 4-byte aligned", dst);
110 "dst (0x%08x) not 4-byte aligned", dst);
111 return; 108 return;
112 } 109 }
113 110
@@ -137,8 +134,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
137 data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask; 134 data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask;
138 size = ALIGN(size, 4); 135 size = ALIGN(size, 4);
139 if (data != dst + size) { 136 if (data != dst + size) {
140 gk20a_err(dev_from_gk20a(g), 137 nvgpu_err(g, "copy failed. bytes written %d, expected %d",
141 "copy failed. bytes written %d, expected %d",
142 data - dst, size); 138 data - dst, size);
143 } 139 }
144 nvgpu_mutex_release(&pmu->pmu_copy_lock); 140 nvgpu_mutex_release(&pmu->pmu_copy_lock);
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/gp106/therm_gp106.c
index c6ce6467..bf8fbfe7 100644
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/therm_gp106.c
@@ -32,13 +32,12 @@ static int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
32 32
33 if (!(therm_temp_sensor_tsense_state_v(readval) & 33 if (!(therm_temp_sensor_tsense_state_v(readval) &
34 therm_temp_sensor_tsense_state_valid_v())) { 34 therm_temp_sensor_tsense_state_valid_v())) {
35 gk20a_err(dev_from_gk20a(g), 35 nvgpu_err(g,
36 "Attempt to read temperature while sensor is OFF!\n"); 36 "Attempt to read temperature while sensor is OFF!");
37 err = -EINVAL; 37 err = -EINVAL;
38 } else if (therm_temp_sensor_tsense_state_v(readval) & 38 } else if (therm_temp_sensor_tsense_state_v(readval) &
39 therm_temp_sensor_tsense_state_shadow_v()) { 39 therm_temp_sensor_tsense_state_shadow_v()) {
40 gk20a_err(dev_from_gk20a(g), 40 nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
41 "Reading temperature from SHADOWed sensor!\n");
42 } 41 }
43 42
44 // Convert from F9.5 -> F27.5 -> F24.8. 43 // Convert from F9.5 -> F27.5 -> F24.8.
@@ -71,7 +70,7 @@ static void gp106_therm_debugfs_init(struct gk20a *g) {
71 dbgentry = debugfs_create_file( 70 dbgentry = debugfs_create_file(
72 "temp", S_IRUGO, platform->debugfs, g, &therm_ctrl_fops); 71 "temp", S_IRUGO, platform->debugfs, g, &therm_ctrl_fops);
73 if (!dbgentry) 72 if (!dbgentry)
74 gk20a_err(dev_from_gk20a(g), "debugfs entry create failed for therm_curr_temp"); 73 nvgpu_err(g, "debugfs entry create failed for therm_curr_temp");
75} 74}
76#endif 75#endif
77 76
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c
index 64d60794..077409c5 100644
--- a/drivers/gpu/nvgpu/gp106/xve_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c
@@ -522,7 +522,7 @@ static ssize_t xve_link_speed_write(struct file *filp,
522 else if (strncmp(kbuff, "Gen3", check_len) == 0) 522 else if (strncmp(kbuff, "Gen3", check_len) == 0)
523 link_speed = GPU_XVE_SPEED_8P0; 523 link_speed = GPU_XVE_SPEED_8P0;
524 else 524 else
525 gk20a_err(g->dev, "%s: Unknown PCIe speed: %s\n", 525 nvgpu_err(g, "%s: Unknown PCIe speed: %s\n",
526 __func__, kbuff); 526 __func__, kbuff);
527 527
528 if (!link_speed) 528 if (!link_speed)