gpu: nvgpu: enable pbus intr for si/fpga

Enable pri squash, fecs err and pri_timeout pbus
interrupt for si and fpga platforms only.

Bug 200350539

Change-Id: Id452edf92eac0209d3b43d98b3ff6efd0764e40a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
index ba4cfcbe..7f0cfe58 100644
--- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
@@ -36,28 +36,30 @@
 
 void gk20a_bus_init_hw(struct gk20a *g)
 {
-        /* enable pri timeout only on silicon */
-        if (nvgpu_platform_is_silicon(g)) {
+        u32 timeout_period, intr_en_mask = 0;
+
+        if (nvgpu_platform_is_silicon(g))
+                timeout_period = g->default_pri_timeout ?
+                                        g->default_pri_timeout : 0x186A0;
+        else
+                timeout_period = 0x186A0;
+
+        if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
+                intr_en_mask = bus_intr_en_0_pri_squash_m() |
+                                bus_intr_en_0_pri_fecserr_m() |
+                                bus_intr_en_0_pri_timeout_m();
                 gk20a_writel(g,
                         timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(
-                                g->default_pri_timeout ?
-                                        g->default_pri_timeout : 0x186A0) |
+                        timer_pri_timeout_period_f(timeout_period) |
                         timer_pri_timeout_en_en_enabled_f());
+
         } else {
                 gk20a_writel(g,
                         timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(0x186A0) |
+                        timer_pri_timeout_period_f(timeout_period) |
                         timer_pri_timeout_en_en_disabled_f());
         }
-
-        if (!nvgpu_platform_is_silicon(g))
-                gk20a_writel(g, bus_intr_en_0_r(), 0x0);
-        else
-                gk20a_writel(g, bus_intr_en_0_r(),
-                                bus_intr_en_0_pri_squash_m() |
-                                bus_intr_en_0_pri_fecserr_m() |
-                                bus_intr_en_0_pri_timeout_m());
+        gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask);
 }
 
 void gk20a_bus_isr(struct gk20a *g)