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authorLakshmanan M <lm@nvidia.com>2016-10-21 07:30:50 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-11-03 12:15:30 -0400
commit8531eb6df14ac0a92d3ed44a4dedd5d283f24c5b (patch)
treedb0677e5b063cd99d7496533867c0a3fae308177
parentd37a573c4536c153877b201e7b98f5247a16cfed (diff)
gpu: nvgpu: Add thermal module support
The following CL contains the following VBIOS thermal table parsing and PMU interface support. 1) Thermal device table 2) Thermal channel table JIRA DNVGPU-130 Change-Id: I3c1baca3fec2727b6d20aa6c007096372a6a3efe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1240631 (cherry picked from commit 1d6fa9ab49b1c84e7f845de206821d879cbda356) Reviewed-on: http://git-master/r/1246204 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrltherm.h24
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.h1
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h77
5 files changed, 105 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrltherm.h b/drivers/gpu/nvgpu/ctrl/ctrltherm.h
new file mode 100644
index 00000000..af6984c1
--- /dev/null
+++ b/drivers/gpu/nvgpu/ctrl/ctrltherm.h
@@ -0,0 +1,24 @@
1/*
2 * Control thermal infrastructure
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15#ifndef _ctrltherm_h_
16#define _ctrltherm_h_
17
18#include "ctrlboardobj.h"
19
20#define CTRL_THERMAL_THERM_DEVICE_CLASS_GPU 0x01
21
22#define CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE 0x01
23
24#endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ec4597a8..43f673f5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -58,6 +58,7 @@ struct acr_desc;
58#include "clk/clk.h" 58#include "clk/clk.h"
59#include "perf/perf.h" 59#include "perf/perf.h"
60#include "pmgr/pmgr.h" 60#include "pmgr/pmgr.h"
61#include "therm/thrm.h"
61#endif 62#endif
62#include "gm206/bios_gm206.h" 63#include "gm206/bios_gm206.h"
63 64
@@ -793,6 +794,7 @@ struct gk20a {
793 struct clk_pmupstate clk_pmu; 794 struct clk_pmupstate clk_pmu;
794 struct perf_pmupstate perf_pmu; 795 struct perf_pmupstate perf_pmu;
795 struct pmgr_pmupstate pmgr_pmu; 796 struct pmgr_pmupstate pmgr_pmu;
797 struct therm_pmupstate therm_pmu;
796#endif 798#endif
797 799
798#ifdef CONFIG_DEBUG_FS 800#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 18f68558..c31bd187 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -181,6 +181,7 @@ struct pmu_ucode_desc_v1 {
181#define PMU_UNIT_RC (0x1F) 181#define PMU_UNIT_RC (0x1F)
182#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) 182#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E)
183#define PMU_UNIT_CLK (0x0D) 183#define PMU_UNIT_CLK (0x0D)
184#define PMU_UNIT_THERM (0x14)
184#define PMU_UNIT_PMGR (0x18) 185#define PMU_UNIT_PMGR (0x18)
185#define PMU_UNIT_VOLT (0x0E) 186#define PMU_UNIT_VOLT (0x0E)
186 187
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h
index 53b82485..1d813df5 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.h
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h
@@ -40,6 +40,7 @@ enum {
40 POWER_SENSORS_TABLE = 0xA, 40 POWER_SENSORS_TABLE = 0xA,
41 POWER_CAPPING_TABLE = 0xB, 41 POWER_CAPPING_TABLE = 0xB,
42 POWER_TOPOLOGY_TABLE = 0xF, 42 POWER_TOPOLOGY_TABLE = 0xF,
43 THERMAL_CHANNEL_TABLE = 0x12,
43 VOLTAGE_RAIL_TABLE = 26, 44 VOLTAGE_RAIL_TABLE = 26,
44 VOLTAGE_DEVICE_TABLE, 45 VOLTAGE_DEVICE_TABLE,
45 VOLTAGE_POLICY_TABLE, 46 VOLTAGE_POLICY_TABLE,
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h
new file mode 100644
index 00000000..498661b3
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h
@@ -0,0 +1,77 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _GPMUIFTHERMSENSOR_H_
15#define _GPMUIFTHERMSENSOR_H_
16
17#include "gk20a/gk20a.h"
18#include "gk20a/pmu_gk20a.h"
19#include "ctrl/ctrltherm.h"
20#include "pmuif/gpmuifboardobj.h"
21#include "gk20a/pmu_common.h"
22
23#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00
24#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01
25
26#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B
27#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008
28
29struct nv_pmu_therm_therm_device_boardobjgrp_set_header {
30 struct nv_pmu_boardobjgrp_e32 super;
31};
32
33struct nv_pmu_therm_therm_device_boardobj_set {
34 struct nv_pmu_boardobj super;
35};
36
37struct nv_pmu_therm_therm_device_i2c_boardobj_set {
38 struct nv_pmu_therm_therm_device_boardobj_set super;
39 u8 i2c_dev_idx;
40};
41
42union nv_pmu_therm_therm_device_boardobj_set_union {
43 struct nv_pmu_boardobj board_obj;
44 struct nv_pmu_therm_therm_device_boardobj_set therm_device;
45 struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
46};
47
48NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);
49
50struct nv_pmu_therm_therm_channel_boardobjgrp_set_header {
51 struct nv_pmu_boardobjgrp_e32 super;
52};
53
54struct nv_pmu_therm_therm_channel_boardobj_set {
55 struct nv_pmu_boardobj super;
56 s16 scaling;
57 s16 offset;
58 s32 temp_min;
59 s32 temp_max;
60};
61
62struct nv_pmu_therm_therm_channel_device_boardobj_set {
63 struct nv_pmu_therm_therm_channel_boardobj_set super;
64 u8 therm_dev_idx;
65 u8 therm_dev_prov_idx;
66};
67
68union nv_pmu_therm_therm_channel_boardobj_set_union {
69 struct nv_pmu_boardobj board_obj;
70 struct nv_pmu_therm_therm_channel_boardobj_set therm_channel;
71 struct nv_pmu_therm_therm_channel_device_boardobj_set device;
72};
73
74NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);
75
76#endif
77