diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-09-02 03:38:55 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:07 -0400 |
commit | 7f6bf042d8c7e3ffb97f4ff7ddb4b9b4b5b8a4b8 (patch) | |
tree | 30f8c080581c88ef920159092a5fd73661929b84 | |
parent | 878560a549cca2c0b67ebe074cd485b8df7db64f (diff) |
gpu: nvgpu: Fix and enable L2 error processing
Fix L2 error processing to look into interrupts in each L2 and slice.
Enable L2 error interrupts.
Bug 1549451
Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/494656
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 31 |
3 files changed, 40 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h index 1bc024be..8cef53d6 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h | |||
@@ -122,10 +122,6 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | |||
122 | { | 122 | { |
123 | return (v & 0x1ffff) << 0; | 123 | return (v & 0x1ffff) << 0; |
124 | } | 124 | } |
125 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
126 | { | ||
127 | return 0x0017e20c; | ||
128 | } | ||
129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | 125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) |
130 | { | 126 | { |
131 | return 0x0017e274; | 127 | return 0x0017e274; |
@@ -274,9 +270,17 @@ static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) | |||
274 | { | 270 | { |
275 | return 0x1; | 271 | return 0x1; |
276 | } | 272 | } |
277 | static inline u32 ltc_ltc0_ltss_intr_r(void) | 273 | static inline u32 ltc_ltcs_ltss_intr_r(void) |
274 | { | ||
275 | return 0x0017e20c; | ||
276 | } | ||
277 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
278 | { | ||
279 | return 0x1 << 20; | ||
280 | } | ||
281 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
278 | { | 282 | { |
279 | return 0x0014020c; | 283 | return 0x0014040c; |
280 | } | 284 | } |
281 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | 285 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) |
282 | { | 286 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h index e978adf2..1b741677 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | |||
@@ -186,6 +186,10 @@ static inline u32 mc_enable_hub_enabled_f(void) | |||
186 | { | 186 | { |
187 | return 0x20000000; | 187 | return 0x20000000; |
188 | } | 188 | } |
189 | static inline u32 mc_intr_ltc_r(void) | ||
190 | { | ||
191 | return 0x0000017c; | ||
192 | } | ||
189 | static inline u32 mc_enable_pb_r(void) | 193 | static inline u32 mc_enable_pb_r(void) |
190 | { | 194 | { |
191 | return 0x00000204; | 195 | return 0x00000204; |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index c265df02..0548105f 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/jiffies.h> | 17 | #include <linux/jiffies.h> |
18 | 18 | ||
19 | #include "hw_mc_gm20b.h" | ||
19 | #include "hw_ltc_gm20b.h" | 20 | #include "hw_ltc_gm20b.h" |
20 | #include "hw_top_gm20b.h" | 21 | #include "hw_top_gm20b.h" |
21 | #include "hw_proj_gm20b.h" | 22 | #include "hw_proj_gm20b.h" |
@@ -172,6 +173,8 @@ out: | |||
172 | 173 | ||
173 | static void gm20b_ltc_init_fs_state(struct gk20a *g) | 174 | static void gm20b_ltc_init_fs_state(struct gk20a *g) |
174 | { | 175 | { |
176 | u32 reg; | ||
177 | |||
175 | gk20a_dbg_info("initialize gm20b l2"); | 178 | gk20a_dbg_info("initialize gm20b l2"); |
176 | 179 | ||
177 | g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); | 180 | g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); |
@@ -188,16 +191,34 @@ static void gm20b_ltc_init_fs_state(struct gk20a *g) | |||
188 | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); | 191 | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); |
189 | 192 | ||
190 | /* Disable LTC interrupts */ | 193 | /* Disable LTC interrupts */ |
191 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), 0); | 194 | reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); |
195 | reg &= ~(1<<20); | ||
196 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); | ||
192 | } | 197 | } |
193 | 198 | ||
194 | void gm20b_ltc_isr(struct gk20a *g) | 199 | void gm20b_ltc_isr(struct gk20a *g) |
195 | { | 200 | { |
196 | u32 intr; | 201 | u32 mc_intr, ltc_intr; |
202 | int ltc, slice; | ||
197 | 203 | ||
198 | intr = gk20a_readl(g, ltc_ltc0_ltss_intr_r()); | 204 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); |
199 | gk20a_err(dev_from_gk20a(g), "ltc: %08x\n", intr); | 205 | gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x", |
200 | gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr); | 206 | mc_intr); |
207 | for (ltc = 0; ltc < g->ltc_count; ltc++) { | ||
208 | if ((mc_intr & 1 << ltc) == 0) | ||
209 | continue; | ||
210 | for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { | ||
211 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + | ||
212 | proj_ltc_stride_v() * ltc + | ||
213 | proj_lts_stride_v() * slice); | ||
214 | gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", | ||
215 | ltc, slice, ltc_intr); | ||
216 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | ||
217 | proj_ltc_stride_v() * ltc + | ||
218 | proj_lts_stride_v() * slice, | ||
219 | ltc_intr); | ||
220 | } | ||
221 | } | ||
201 | } | 222 | } |
202 | 223 | ||
203 | static void gm20b_ltc_g_elpg_flush_locked(struct gk20a *g) | 224 | static void gm20b_ltc_g_elpg_flush_locked(struct gk20a *g) |