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authorKonsta Holtta <kholtta@nvidia.com>2017-10-31 07:07:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-07 20:10:57 -0500
commit760f8dd7fbbfaee7607d10c38fe013f9cb069cd7 (patch)
tree34239151105624cefd782798785fd442c67833fa
parent295ade2f1ea76f2cf61ab93465d251cabb681f49 (diff)
gpu: nvgpu: drop user callback support in CE
Simplify the copyengine code by deleting support for the ce_event_callback feature that has never been used. Similarly, create a channel without the finish callback to get rid of that Linux dependency, and delete the finish callback function as it now serves no purpose. Delete also the submitted_seq_number and completed_seq_number fields that are only written to. Jira NVGPU-259 Change-Id: I02d15bdcb546f4dd8895a6bfb5130caf88a104e2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589320 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/linux/ce2.c1
-rw-r--r--drivers/gpu/nvgpu/common/mm/mm.c5
-rw-r--r--drivers/gpu/nvgpu/gk20a/ce2_gk20a.c66
-rw-r--r--drivers/gpu/nvgpu/gk20a/ce2_gk20a.h19
4 files changed, 8 insertions, 83 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ce2.c b/drivers/gpu/nvgpu/common/linux/ce2.c
index 3fee23e5..5127a32b 100644
--- a/drivers/gpu/nvgpu/common/linux/ce2.c
+++ b/drivers/gpu/nvgpu/common/linux/ce2.c
@@ -173,7 +173,6 @@ int gk20a_ce_execute_ops(struct gk20a *g,
173 173
174 /* Next available command buffer queue Index */ 174 /* Next available command buffer queue Index */
175 ++ce_ctx->cmd_buf_read_queue_offset; 175 ++ce_ctx->cmd_buf_read_queue_offset;
176 ++ce_ctx->submitted_seq_number;
177 } 176 }
178 } else { 177 } else {
179 ret = -ENOMEM; 178 ret = -ENOMEM;
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index cb7c443d..73af31c9 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -259,12 +259,11 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
259#if defined(CONFIG_GK20A_VIDMEM) 259#if defined(CONFIG_GK20A_VIDMEM)
260 if (g->mm.vidmem.size && (g->mm.vidmem.ce_ctx_id == (u32)~0)) { 260 if (g->mm.vidmem.size && (g->mm.vidmem.ce_ctx_id == (u32)~0)) {
261 g->mm.vidmem.ce_ctx_id = 261 g->mm.vidmem.ce_ctx_id =
262 gk20a_ce_create_context_with_cb(g, 262 gk20a_ce_create_context(g,
263 gk20a_fifo_get_fast_ce_runlist_id(g), 263 gk20a_fifo_get_fast_ce_runlist_id(g),
264 -1, 264 -1,
265 -1, 265 -1,
266 -1, 266 -1);
267 NULL);
268 267
269 if (g->mm.vidmem.ce_ctx_id == (u32)~0) 268 if (g->mm.vidmem.ce_ctx_id == (u32)~0)
270 nvgpu_err(g, 269 nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 9ff6c792..04ee84f4 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -103,54 +103,6 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
103} 103}
104 104
105/* static CE app api */ 105/* static CE app api */
106static void gk20a_ce_notify_all_user(struct gk20a *g, u32 event)
107{
108 struct gk20a_ce_app *ce_app = &g->ce_app;
109 struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
110
111 if (!ce_app->initialised)
112 return;
113
114 nvgpu_mutex_acquire(&ce_app->app_mutex);
115
116 nvgpu_list_for_each_entry_safe(ce_ctx, ce_ctx_save,
117 &ce_app->allocated_contexts, gk20a_gpu_ctx, list) {
118 if (ce_ctx->user_event_callback) {
119 ce_ctx->user_event_callback(ce_ctx->ctx_id,
120 event);
121 }
122 }
123
124 nvgpu_mutex_release(&ce_app->app_mutex);
125}
126
127static void gk20a_ce_finished_ctx_cb(struct channel_gk20a *ch, void *data)
128{
129 struct gk20a_gpu_ctx *ce_ctx = data;
130 bool channel_idle;
131 u32 event;
132
133 channel_gk20a_joblist_lock(ch);
134 channel_idle = channel_gk20a_joblist_is_empty(ch);
135 channel_gk20a_joblist_unlock(ch);
136
137 if (!channel_idle)
138 return;
139
140 gk20a_dbg(gpu_dbg_fn, "ce: finished %p", ce_ctx);
141
142 if (ch->has_timedout)
143 event = NVGPU_CE_CONTEXT_JOB_TIMEDOUT;
144 else
145 event = NVGPU_CE_CONTEXT_JOB_COMPLETED;
146
147 if (ce_ctx->user_event_callback)
148 ce_ctx->user_event_callback(ce_ctx->ctx_id,
149 event);
150
151 ++ce_ctx->completed_seq_number;
152}
153
154static void gk20a_ce_free_command_buffer_stored_fence(struct gk20a_gpu_ctx *ce_ctx) 106static void gk20a_ce_free_command_buffer_stored_fence(struct gk20a_gpu_ctx *ce_ctx)
155{ 107{
156 u32 cmd_buf_index; 108 u32 cmd_buf_index;
@@ -410,7 +362,6 @@ int gk20a_init_ce_support(struct gk20a *g)
410 if (ce_app->initialised) { 362 if (ce_app->initialised) {
411 /* assume this happen during poweron/poweroff GPU sequence */ 363 /* assume this happen during poweron/poweroff GPU sequence */
412 ce_app->app_state = NVGPU_CE_ACTIVE; 364 ce_app->app_state = NVGPU_CE_ACTIVE;
413 gk20a_ce_notify_all_user(g, NVGPU_CE_CONTEXT_RESUME);
414 return 0; 365 return 0;
415 } 366 }
416 367
@@ -469,18 +420,16 @@ void gk20a_ce_suspend(struct gk20a *g)
469 return; 420 return;
470 421
471 ce_app->app_state = NVGPU_CE_SUSPEND; 422 ce_app->app_state = NVGPU_CE_SUSPEND;
472 gk20a_ce_notify_all_user(g, NVGPU_CE_CONTEXT_SUSPEND);
473 423
474 return; 424 return;
475} 425}
476 426
477/* CE app utility functions */ 427/* CE app utility functions */
478u32 gk20a_ce_create_context_with_cb(struct gk20a *g, 428u32 gk20a_ce_create_context(struct gk20a *g,
479 int runlist_id, 429 int runlist_id,
480 int priority, 430 int priority,
481 int timeslice, 431 int timeslice,
482 int runlist_level, 432 int runlist_level)
483 ce_event_callback user_event_callback)
484{ 433{
485 struct gk20a_gpu_ctx *ce_ctx; 434 struct gk20a_gpu_ctx *ce_ctx;
486 struct gk20a_ce_app *ce_app = &g->ce_app; 435 struct gk20a_ce_app *ce_app = &g->ce_app;
@@ -501,15 +450,11 @@ u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
501 } 450 }
502 451
503 ce_ctx->g = g; 452 ce_ctx->g = g;
504 ce_ctx->user_event_callback = user_event_callback;
505 453
506 ce_ctx->cmd_buf_read_queue_offset = 0; 454 ce_ctx->cmd_buf_read_queue_offset = 0;
507 ce_ctx->cmd_buf_end_queue_offset = 455 ce_ctx->cmd_buf_end_queue_offset =
508 (NVGPU_CE_COMMAND_BUF_SIZE / NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF); 456 (NVGPU_CE_COMMAND_BUF_SIZE / NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF);
509 457
510 ce_ctx->submitted_seq_number = 0;
511 ce_ctx->completed_seq_number = 0;
512
513 ce_ctx->vm = g->mm.ce.vm; 458 ce_ctx->vm = g->mm.ce.vm;
514 459
515 if (nvgpu_is_enabled(g, NVGPU_MM_CE_TSG_REQUIRED)) { 460 if (nvgpu_is_enabled(g, NVGPU_MM_CE_TSG_REQUIRED)) {
@@ -523,10 +468,7 @@ u32 gk20a_ce_create_context_with_cb(struct gk20a *g,
523 } 468 }
524 469
525 /* always kernel client needs privileged channel */ 470 /* always kernel client needs privileged channel */
526 ce_ctx->ch = gk20a_open_new_channel_with_cb(g, gk20a_ce_finished_ctx_cb, 471 ce_ctx->ch = gk20a_open_new_channel(g, runlist_id, true);
527 ce_ctx,
528 runlist_id,
529 true);
530 if (!ce_ctx->ch) { 472 if (!ce_ctx->ch) {
531 nvgpu_err(g, "ce: gk20a channel not available"); 473 nvgpu_err(g, "ce: gk20a channel not available");
532 goto end; 474 goto end;
@@ -613,7 +555,7 @@ end:
613 return ctx_id; 555 return ctx_id;
614 556
615} 557}
616EXPORT_SYMBOL(gk20a_ce_create_context_with_cb); 558EXPORT_SYMBOL(gk20a_ce_create_context);
617 559
618void gk20a_ce_delete_context(struct gk20a *g, 560void gk20a_ce_delete_context(struct gk20a *g,
619 u32 ce_ctx_id) 561 u32 ce_ctx_id)
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
index 8d3a4ca3..5c3a1cfc 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -40,8 +40,6 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
40#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256 40#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256
41#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8 41#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
42 42
43typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag);
44
45/* dma launch_flags */ 43/* dma launch_flags */
46enum { 44enum {
47 /* location */ 45 /* location */
@@ -69,14 +67,6 @@ enum {
69 NVGPU_CE_MEMSET = (1 << 1), 67 NVGPU_CE_MEMSET = (1 << 1),
70}; 68};
71 69
72/* CE event flags */
73enum {
74 NVGPU_CE_CONTEXT_JOB_COMPLETED = (1 << 0),
75 NVGPU_CE_CONTEXT_JOB_TIMEDOUT = (1 << 1),
76 NVGPU_CE_CONTEXT_SUSPEND = (1 << 2),
77 NVGPU_CE_CONTEXT_RESUME = (1 << 3),
78};
79
80/* CE app state machine flags */ 70/* CE app state machine flags */
81enum { 71enum {
82 NVGPU_CE_ACTIVE = (1 << 0), 72 NVGPU_CE_ACTIVE = (1 << 0),
@@ -106,7 +96,6 @@ struct gk20a_gpu_ctx {
106 u32 ctx_id; 96 u32 ctx_id;
107 struct nvgpu_mutex gpu_ctx_mutex; 97 struct nvgpu_mutex gpu_ctx_mutex;
108 int gpu_ctx_state; 98 int gpu_ctx_state;
109 ce_event_callback user_event_callback;
110 99
111 /* tsg related data */ 100 /* tsg related data */
112 struct tsg_gk20a *tsg; 101 struct tsg_gk20a *tsg;
@@ -120,9 +109,6 @@ struct gk20a_gpu_ctx {
120 109
121 struct nvgpu_list_node list; 110 struct nvgpu_list_node list;
122 111
123 u64 submitted_seq_number;
124 u64 completed_seq_number;
125
126 u32 cmd_buf_read_queue_offset; 112 u32 cmd_buf_read_queue_offset;
127 u32 cmd_buf_end_queue_offset; 113 u32 cmd_buf_end_queue_offset;
128}; 114};
@@ -140,12 +126,11 @@ void gk20a_ce_suspend(struct gk20a *g);
140void gk20a_ce_destroy(struct gk20a *g); 126void gk20a_ce_destroy(struct gk20a *g);
141 127
142/* CE app utility functions */ 128/* CE app utility functions */
143u32 gk20a_ce_create_context_with_cb(struct gk20a *g, 129u32 gk20a_ce_create_context(struct gk20a *g,
144 int runlist_id, 130 int runlist_id,
145 int priority, 131 int priority,
146 int timeslice, 132 int timeslice,
147 int runlist_level, 133 int runlist_level);
148 ce_event_callback user_event_callback);
149int gk20a_ce_execute_ops(struct gk20a *g, 134int gk20a_ce_execute_ops(struct gk20a *g,
150 u32 ce_ctx_id, 135 u32 ce_ctx_id,
151 u64 src_buf, 136 u64 src_buf,