gpu: nvgpu: gv100: PMU f/w update

-Added new version of pmu init msg "pmu_init_msg_pmu_v5"
-created methods to support new pmu init message parameter
read based on f/w version for below ops.
  .get_pmu_msg_pmu_init_msg_ptr
  .get_pmu_init_msg_pmu_sw_mg_off
  .get_pmu_init_msg_pmu_sw_mg_size
-Corrected PMU_DMEM_ALLOC_ALIGNMENT value to 32 bit
to allocate PMU DMEM space for nvgpu
-Updated PMU version of GV100/APP_VERSION_BIGGPU
to 23440730 & PMU ucode CL is
https://git-master.nvidia.com/r/#/c/1642432/

Change-Id: Ib1e0197b5f3a229a601e810c9c0d93f05b9d69e7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 61 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 1c1a3c82..ec5c5b7d 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,7 +37,7 @@
 
 /* PMU F/W version */
 #define APP_VERSION_GV11B       23355380
-#define APP_VERSION_GV10X       22836594
+#define APP_VERSION_GV10X       23440730
 #define APP_VERSION_GP10X       21308030
 #define APP_VERSION_GP10B       20429989
 #define APP_VERSION_GM20B       20490253
@@ -389,6 +389,11 @@ static void pmu_allocation_set_dmem_offset_v1(struct nvgpu_pmu *pmu,
         pmu_a_ptr->alloc.dmem.offset = offset;
 }
 
+static void *get_pmu_msg_pmu_init_msg_ptr_v5(struct pmu_init_msg *init)
+{
+        return (void *)(&(init->pmu_init_v5));
+}
+
 static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init)
 {
         return (void *)(&(init->pmu_init_v4));
@@ -399,6 +404,14 @@ static void *get_pmu_msg_pmu_init_msg_ptr_v3(struct pmu_init_msg *init)
         return (void *)(&(init->pmu_init_v3));
 }
 
+static u16 get_pmu_init_msg_pmu_sw_mg_off_v5(union pmu_init_msg_pmu *init_msg)
+{
+        struct pmu_init_msg_pmu_v5 *init =
+                (struct pmu_init_msg_pmu_v5 *)(&init_msg->v5);
+
+        return init->sw_managed_area_offset;
+}
+
 static u16 get_pmu_init_msg_pmu_sw_mg_off_v4(union pmu_init_msg_pmu *init_msg)
 {
         struct pmu_init_msg_pmu_v4 *init =
@@ -415,6 +428,14 @@ static u16 get_pmu_init_msg_pmu_sw_mg_off_v3(union pmu_init_msg_pmu *init_msg)
         return init->sw_managed_area_offset;
 }
 
+static u16 get_pmu_init_msg_pmu_sw_mg_size_v5(union pmu_init_msg_pmu *init_msg)
+{
+        struct pmu_init_msg_pmu_v5 *init =
+                (struct pmu_init_msg_pmu_v5 *)(&init_msg->v5);
+
+        return init->sw_managed_area_size;
+}
+
 static u16 get_pmu_init_msg_pmu_sw_mg_size_v4(union pmu_init_msg_pmu *init_msg)
 {
         struct pmu_init_msg_pmu_v4 *init =
@@ -856,7 +877,7 @@ static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue,
 static void get_pmu_init_msg_pmu_queue_params_v5(struct pmu_queue *queue,
         u32 id, void *pmu_init_msg)
 {
-        struct pmu_init_msg_pmu_v4 *init = pmu_init_msg;
+        struct pmu_init_msg_pmu_v5 *init = pmu_init_msg;
         u32 current_ptr = 0;
         u8 i;
         u8 tmp_id = id;
@@ -1249,18 +1270,26 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                 pmu_allocation_get_fb_addr_v3;
                 g->ops.pmu_ver.pmu_allocation_get_fb_size =
                                 pmu_allocation_get_fb_size_v3;
-                if (pmu->desc->app_version == APP_VERSION_GV10X)
+                if (pmu->desc->app_version == APP_VERSION_GV10X) {
                         g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
                                 get_pmu_init_msg_pmu_queue_params_v5;
-                else
+                        g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
+                                get_pmu_msg_pmu_init_msg_ptr_v5;
+                        g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
+                                get_pmu_init_msg_pmu_sw_mg_off_v5;
+                        g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
+                                get_pmu_init_msg_pmu_sw_mg_size_v5;
+                } else {
                         g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
                                 get_pmu_init_msg_pmu_queue_params_v4;
-                g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
-                        get_pmu_msg_pmu_init_msg_ptr_v4;
-                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
-                        get_pmu_init_msg_pmu_sw_mg_off_v4;
-                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
-                        get_pmu_init_msg_pmu_sw_mg_size_v4;
+                        g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
+                                get_pmu_msg_pmu_init_msg_ptr_v4;
+                        g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
+                                get_pmu_init_msg_pmu_sw_mg_off_v4;
+                        g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
+                                get_pmu_init_msg_pmu_sw_mg_size_v4;
+                }
+
                 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
                         get_pmu_perfmon_cmd_start_size_v3;
                 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
index 71ecc24a..d146cac7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -102,7 +102,7 @@ struct pmu_hdr {
 #define nv_pmu_hdr pmu_hdr
 typedef u8 flcn_status;
 
-#define PMU_DMEM_ALLOC_ALIGNMENT        (4)
+#define PMU_DMEM_ALLOC_ALIGNMENT        (32)
 #define PMU_DMEM_ALIGNMENT              (4)
 
 #define PMU_CMD_FLAGS_PMU_MASK          (0xF0)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
index 8e38db31..5f718dc6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -141,10 +141,27 @@ struct pmu_init_msg_pmu_v4 {
         u8 dummy[18];
 };
 
+struct pmu_init_msg_pmu_v5 {
+        u8 msg_type;
+        u8 flcn_status;
+        u8  queue_index[PMU_QUEUE_COUNT_FOR_V4];
+        u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
+        u16 queue_offset;
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+
+        u16  os_debug_entry_point;
+
+        u8 dummy[18];
+        u8 pad;
+};
+
 union pmu_init_msg_pmu {
         struct pmu_init_msg_pmu_v1 v1;
         struct pmu_init_msg_pmu_v3 v3;
         struct pmu_init_msg_pmu_v4 v4;
+        struct pmu_init_msg_pmu_v5 v5;
 };
 
 struct pmu_init_msg {
@@ -153,6 +170,7 @@ struct pmu_init_msg {
                 struct pmu_init_msg_pmu_v1 pmu_init_v1;
                 struct pmu_init_msg_pmu_v3 pmu_init_v3;
                 struct pmu_init_msg_pmu_v4 pmu_init_v4;
+                struct pmu_init_msg_pmu_v5 pmu_init_v5;
         };
 };