gpu:nvgpu: Update vfe_load for GV100

Add gops to choose vfe_load between GP and GV.

Bug 200399373

Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702143
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 52 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 95ddb71c..9c9e3fe8 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1311,6 +1311,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                         clk_avfs_get_vin_cal_fuse_v20;
                         g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
                                         nvgpu_clk_vf_change_inject_data_fill_gv10x;
+                        g->ops.pmu_ver.clk.perf_pmu_vfe_load =
+                                perf_pmu_vfe_load_gv10x;
                 } else {
                         g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
                                 get_pmu_init_msg_pmu_queue_params_v4;
@@ -1482,6 +1484,10 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                 clk_avfs_get_vin_cal_fuse_v10;
                 g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
                                 nvgpu_clk_vf_change_inject_data_fill_gp10x;
+                g->ops.pmu_ver.clk.clk_set_boot_clk =
+                                nvgpu_clk_set_boot_fll_clk_gv10x;
+                g->ops.pmu_ver.clk.perf_pmu_vfe_load =
+                        perf_pmu_vfe_load;
                 break;
         case APP_VERSION_GM20B:
                 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 38952daf..f71ddc2c 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -819,6 +819,7 @@ struct gpu_ops {
                         u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g,
                                 struct nv_pmu_clk_rpc *rpccall,
                                 struct set_fll_clk *setfllclk);
+                        u32 (*perf_pmu_vfe_load)(struct gk20a *g);
                 }clk;
         } pmu_ver;
         struct {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
index 83d08afc..aedf7988 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
@@ -37,6 +37,34 @@
 #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET                      (0x00000003)
 #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS               (0x00000004)
 
+/*!
+ * RPC calls serviced by PERF unit.
+ */
+#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD                                0x00
+#define NV_PMU_RPC_ID_PERF_LOAD                                             0x01
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET                              0x02
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET                              0x03
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL                           0x04
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE                          0x05
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK                                  0x06
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD                                  0x07
+#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY                                 0x08
+#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE                           0x09
+#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL                                     0x0A
+#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE                                   0x0B
+#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET                              0x0C
+#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET                              0x0D
+#define NV_PMU_RPC_ID_PERF__COUNT                                           0x0E
+/*
+ * Defines the structure that holds data
+ * used to execute LOAD RPC.
+ */
+struct nv_pmu_rpc_struct_perf_load {
+        /*[IN/OUT] Must be first field in RPC structure */
+    struct nv_pmu_rpc_header hdr;
+        u32  scratch[1];
+};
+
 struct nv_pmu_perf_cmd_set_object {
         u8 cmd_type;
         u8 pad[2];
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c
index bf63e1ea..900496fd 100644
--- a/drivers/gpu/nvgpu/perf/perf.c
+++ b/drivers/gpu/nvgpu/perf/perf.c
@@ -65,6 +65,21 @@ static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
         return 0;
 }
 
+u32 perf_pmu_vfe_load_gv10x(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+        struct nv_pmu_rpc_struct_perf_load rpc;
+        u32 status = 0;
+
+        memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load));
+        PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0);
+        if (status) {
+                nvgpu_err(g, "Failed to execute RPC status=0x%x",
+                        status);
+        }
+        return status;
+}
+
 u32 perf_pmu_vfe_load(struct gk20a *g)
 {
         struct pmu_cmd cmd;
diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h
index c3708f61..180efb2c 100644
--- a/drivers/gpu/nvgpu/perf/perf.h
+++ b/drivers/gpu/nvgpu/perf/perf.h
@@ -74,5 +74,6 @@ struct perf_pmupstate {
 };
 
 u32 perf_pmu_vfe_load(struct gk20a *g);
+u32 perf_pmu_vfe_load_gv10x(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index e61ec0f8..3d6a436d 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -184,7 +184,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
         if (err)
                 return err;
 
-        err = perf_pmu_vfe_load(g);
+        err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g);
         if (err)
                 return err;