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authorDeepak Goyal <dgoyal@nvidia.com>2017-10-27 05:21:17 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-02 08:09:29 -0400
commit730ba218c1a57486f05e02cfaddf6a75e95ff498 (patch)
tree5df44782e95507ccdd2968ef34c4906f3ffb8aa6
parentf472922b3582dbba78b633958a4cb7b65ddb3f03 (diff)
gpu: nvgpu: gv11b: Kernel iface for Dynamic TPC-PG
This patch adds kernel interface for dynamic TPC-PG feature. User-space needs to send TPC-PG args to kernel via ioctl. Dynamic TPC-PG feature will allow every context to specify the number of TPC's it will use to run its workload. This way, graphics driver can power off non-required TPC's if a particular context has light to medium workload. JIRA GPUT19x-16 Change-Id: Id4846245a6414b719599d04784cbe2ca5282f4ad Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c17
-rw-r--r--drivers/gpu/nvgpu/tsg_t19x.h12
-rw-r--r--include/uapi/linux/nvgpu-t19x.h5
3 files changed, 29 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c
index 797115ac..ec7501ce 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c
@@ -28,6 +28,7 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g,
28 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 28 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
29 struct gk20a_sched_ctrl *sched = &l->sched_ctrl; 29 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
30 struct channel_gk20a *ch; 30 struct channel_gk20a *ch;
31 struct gr_gk20a *gr = &g->gr;
31 int err = 0; 32 int err = 0;
32 33
33 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); 34 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -48,6 +49,22 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g,
48 err = -EINVAL; 49 err = -EINVAL;
49 goto idle; 50 goto idle;
50 } 51 }
52
53 if (arg->tpc_pg_enabled && (!tsg->t19x.tpc_num_initialized)) {
54 if ((arg->num_active_tpcs > gr->max_tpc_count) ||
55 !(arg->num_active_tpcs)) {
56 nvgpu_err(g, "Invalid num of active TPCs");
57 err = -EINVAL;
58 goto ch_put;
59 }
60 tsg->t19x.tpc_num_initialized = true;
61 tsg->t19x.num_active_tpcs = arg->num_active_tpcs;
62 tsg->t19x.tpc_pg_enabled = true;
63 } else {
64 tsg->t19x.tpc_pg_enabled = false;
65 nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
66 }
67
51 if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) { 68 if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) {
52 ch->t19x.subctx_id = arg->subcontext_id; 69 ch->t19x.subctx_id = arg->subcontext_id;
53 } else { 70 } else {
diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h
index 18c00821..d1f47cc3 100644
--- a/drivers/gpu/nvgpu/tsg_t19x.h
+++ b/drivers/gpu/nvgpu/tsg_t19x.h
@@ -22,9 +22,15 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVGPU_TSG_T19X_H_ 25#ifndef __NVGPU_TSG_T19X_H__
26#define _NVGPU_TSG_T19X_H_ 26#define __NVGPU_TSG_T19X_H__
27 27
28#include "common/linux/ioctl_tsg_t19x.h" 28#include <nvgpu/types.h>
29
30struct tsg_t19x {
31 u32 num_active_tpcs;
32 u8 tpc_pg_enabled;
33 bool tpc_num_initialized;
34};
29 35
30#endif 36#endif
diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h
index f56bc9d7..27db97c0 100644
--- a/include/uapi/linux/nvgpu-t19x.h
+++ b/include/uapi/linux/nvgpu-t19x.h
@@ -44,8 +44,9 @@ struct nvgpu_tsg_bind_channel_ex_args {
44 44
45 /* in: VEID in Volta */ 45 /* in: VEID in Volta */
46 __u32 subcontext_id; 46 __u32 subcontext_id;
47 47 __u32 num_active_tpcs;
48 __u64 reserved[2]; 48 __u8 tpc_pg_enabled;
49 __u8 reserved[11];
49}; 50};
50 51
51#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \ 52#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \