gpu: nvgpu: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.

JIRA NVGPU-989

Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

10 files changed, 56 insertions, 29 deletions

diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
index 912c2c98..3c28963c 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
@@ -376,8 +376,9 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask);
 #define HIGHESTBITIDX_32(n32)   \
 {                               \
         u32 count = 0;        \
-        while (n32 >>= 1)       \
-                count++;        \
+        while (n32 >>= 1) {       \
+                count++;       \
+        }                      \
         n32 = count;            \
 }
 
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c
index 93befc99..849abe16 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -63,8 +63,9 @@ u32 boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
         if (mask->bitcount != bitsize)
                 return -EINVAL;
 
-        for (index = 0; index < mask->maskdatacount; index++)
+        for (index = 0; index < mask->maskdatacount; index++) {
                 mask->data[index] = extmask->data[index];
+        }
 
         BOARDOBJGRPMASK_NORMALIZE(mask);
 
@@ -83,8 +84,9 @@ u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
         if (mask->bitcount != bitsize)
                 return -EINVAL;
 
-        for (index = 0; index < mask->maskdatacount; index++)
+        for (index = 0; index < mask->maskdatacount; index++) {
                 extmask->data[index] = mask->data[index];
+        }
 
         return 0;
 }
@@ -95,8 +97,9 @@ u32 boardobjgrpmask_clr(struct boardobjgrpmask *mask)
 
         if (mask == NULL)
                 return -EINVAL;
-        for (index = 0; index < mask->maskdatacount; index++)
+        for (index = 0; index < mask->maskdatacount; index++) {
                 mask->data[index] = 0;
+        }
 
         return 0;
 }
@@ -107,8 +110,9 @@ u32 boardobjgrpmask_set(struct boardobjgrpmask *mask)
 
         if (mask == NULL)
                 return -EINVAL;
-        for (index = 0; index < mask->maskdatacount; index++)
+        for (index = 0; index < mask->maskdatacount; index++) {
                 mask->data[index] = 0xFFFFFFFF;
+        }
         BOARDOBJGRPMASK_NORMALIZE(mask);
         return 0;
 }
@@ -119,8 +123,9 @@ u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask)
 
         if (mask == NULL)
                 return -EINVAL;
-        for (index = 0; index < mask->maskdatacount; index++)
+        for (index = 0; index < mask->maskdatacount; index++) {
                 mask->data[index] = ~mask->data[index];
+        }
         BOARDOBJGRPMASK_NORMALIZE(mask);
         return 0;
 }
@@ -281,8 +286,9 @@ u32 boardobjgrpmask_and(struct boardobjgrpmask *dst,
         if (!boardobjgrpmask_sizeeq(dst, op2))
                 return -EINVAL;
 
-        for (index = 0; index < dst->maskdatacount; index++)
+        for (index = 0; index < dst->maskdatacount; index++) {
                 dst->data[index] = op1->data[index] & op2->data[index];
+        }
 
         return 0;
 }
@@ -298,8 +304,9 @@ u32 boardobjgrpmask_or(struct boardobjgrpmask *dst,
         if (!boardobjgrpmask_sizeeq(dst, op2))
                 return -EINVAL;
 
-        for (index = 0; index < dst->maskdatacount; index++)
+        for (index = 0; index < dst->maskdatacount; index++) {
                 dst->data[index] = op1->data[index] | op2->data[index];
+        }
 
         return 0;
 }
@@ -315,8 +322,9 @@ u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst,
         if (!boardobjgrpmask_sizeeq(dst, op2))
                 return -EINVAL;
 
-        for (index = 0; index < dst->maskdatacount; index++)
+        for (index = 0; index < dst->maskdatacount; index++) {
                 dst->data[index] = op1->data[index] ^ op2->data[index];
+        }
 
         return 0;
 }
@@ -329,8 +337,9 @@ u32 boardobjgrpmask_copy(struct boardobjgrpmask *dst,
         if (!boardobjgrpmask_sizeeq(dst, src))
                 return -EINVAL;
 
-        for (index = 0; index < dst->maskdatacount; index++)
+        for (index = 0; index < dst->maskdatacount; index++) {
                 dst->data[index] = src->data[index];
+        }
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c
index deeae2fe..e470fffc 100644
--- a/drivers/gpu/nvgpu/gp106/bios_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/bios_gp106.c
@@ -70,8 +70,9 @@ static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
                 pwr_falcon_dmemc_blk_f(blk) |
                 pwr_falcon_dmemc_aincw_f(1));
 
-        for (i = 0; i < words; i++)
+        for (i = 0; i < words; i++) {
                 gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
+        }
 }
 
 int gp106_bios_devinit(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 7792728c..5a22af80 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1572,8 +1572,9 @@ int gr_gp10b_load_smid_config(struct gk20a *g)
                 gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg);
         }
 
-        for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++)
+        for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) {
                 gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]);
+        }
 
         nvgpu_kfree(g, tpc_sm_id);
 
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index a0e08437..7036ca15 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -286,8 +286,9 @@ static enum gmmu_pgsz_gk20a gp10b_get_pde0_pgsz(struct gk20a *g,
         if (!pd->mem)
                 return pgsz;
 
-        for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++)
+        for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) {
                 pde_v[i] = nvgpu_mem_rd32(g, pd->mem, pde_offset + i);
+        }
 
         /*
          * Check if the aperture AND address are set
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index 97affdd9..13092f2a 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -229,9 +229,11 @@ int gr_gv100_init_sm_id_table(struct gk20a *g)
                 goto exit_build_table;
         }
 
-        for (gpc = 0; gpc < g->gr.gpc_count; gpc++)
-                for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++)
+        for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
+                for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) {
                         gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc];
+                }
+        }
 
         for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) {
                 maxperf = -1;
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
index 696eb015..d0928335 100644
--- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
@@ -144,9 +144,10 @@ int gv11b_bootstrap_hs_flcn(struct gk20a *g)
                         goto err_release_acr_fw;
                 }
 
-                for (index = 0; index < 9; index++)
+                for (index = 0; index < 9; index++) {
                         gv11b_dbg_pmu(g, "acr_ucode_header_t210_load %u\n",
                                         acr_ucode_header_t210_load[index]);
+                }
 
                 acr_dmem = (u64 *)
                         &(((u8 *)acr_ucode_data_t210_load)[
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index d1bd7111..56012dd7 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -808,14 +808,16 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
         runlist_served_pbdmas = f->runlist_info[runlist_id].pbdma_bitmask;
         runlist_served_engines = f->runlist_info[runlist_id].eng_bitmask;
 
-        for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma)
+        for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma) {
                 ret |= gv11b_fifo_poll_pbdma_chan_status(g, tsgid, pbdma_id);
+        }
 
         f->runlist_info[runlist_id].reset_eng_bitmask = 0;
 
-        for_each_set_bit(act_eng_id, &runlist_served_engines, f->max_engines)
+        for_each_set_bit(act_eng_id, &runlist_served_engines, f->max_engines) {
                 ret |= gv11b_fifo_poll_eng_ctx_status(g, tsgid, act_eng_id,
                                 &f->runlist_info[runlist_id].reset_eng_bitmask);
+        }
         return ret;
 }
 
@@ -1028,9 +1030,10 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
         u32 num_runlists = 0;
 
         nvgpu_log_fn(g, "acquire runlist_lock for all runlists");
-        for (rlid = 0; rlid < g->fifo.max_runlists; rlid++)
+        for (rlid = 0; rlid < g->fifo.max_runlists; rlid++) {
                 nvgpu_mutex_acquire(&f->runlist_info[rlid].
                         runlist_lock);
+        }
 
         /* get runlist id and tsg */
         if (id_type == ID_TYPE_TSG) {
@@ -1206,9 +1209,10 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                 nvgpu_mutex_release(&f->runlist_info[runlist_id].runlist_lock);
         } else {
                 nvgpu_log_fn(g, "release runlist_lock for all runlists");
-                for (rlid = 0; rlid < g->fifo.max_runlists; rlid++)
+                for (rlid = 0; rlid < g->fifo.max_runlists; rlid++) {
                         nvgpu_mutex_release(&f->runlist_info[rlid].
                                 runlist_lock);
+                }
         }
 }
 
@@ -1756,9 +1760,10 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
                         break;
         }
         if (err) {
-                for (i = (runque - 1); i >= 0; i--)
+                for (i = (runque - 1); i >= 0; i--) {
                         nvgpu_dma_unmap_free(vm,
                                  &tsg->eng_method_buffers[i]);
+                }
 
                 nvgpu_kfree(g, tsg->eng_method_buffers);
                 tsg->eng_method_buffers = NULL;
@@ -1778,8 +1783,9 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
         if (tsg->eng_method_buffers == NULL)
                 return;
 
-        for (runque = 0; runque < g->fifo.num_pbdma; runque++)
+        for (runque = 0; runque < g->fifo.num_pbdma; runque++) {
                 nvgpu_dma_unmap_free(vm, &tsg->eng_method_buffers[runque]);
+        }
 
         nvgpu_kfree(g, tsg->eng_method_buffers);
         tsg->eng_method_buffers = NULL;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9e36071f..791c0d6f 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2801,8 +2801,9 @@ int gr_gv11b_load_smid_config(struct gk20a *g)
                 gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg);
         }
 
-        for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++)
+        for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) {
                 gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]);
+        }
         nvgpu_kfree(g, tpc_sm_id);
 
         return 0;
@@ -4894,11 +4895,12 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                         if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC)
                                 for (tpc_num = 0;
                                      tpc_num < g->gr.gpc_tpc_count[gpc_num];
-                                     tpc_num++)
+                                     tpc_num++) {
                                         priv_addr_table[t++] =
                                                 pri_tpc_addr(g,
                                                     pri_tpccs_addr_mask(addr),
                                                     gpc_num, tpc_num);
+                                }
 
                         else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) {
                                 err = gr_gk20a_split_ppc_broadcast_addr(g,
@@ -4998,11 +5000,12 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC)
                         for (tpc_num = 0;
                              tpc_num < g->gr.gpc_tpc_count[gpc_num];
-                             tpc_num++)
+                             tpc_num++) {
                                 priv_addr_table[t++] =
                                         pri_tpc_addr(g,
                                                 pri_tpccs_addr_mask(addr),
                                                 gpc_num, tpc_num);
+                        }
                 else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC)
                         err = gr_gk20a_split_ppc_broadcast_addr(g,
                                         addr, gpc_num, priv_addr_table, &t);
diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c
index 8321d98d..fa742c35 100644
--- a/drivers/gpu/nvgpu/perf/vfe_equ.c
+++ b/drivers/gpu/nvgpu/perf/vfe_equ.c
@@ -517,8 +517,9 @@ static u32 _vfe_equ_pmudatainit_quadratic(struct gk20a *g,
 
         pset = (struct nv_pmu_vfe_equ_quadratic *) ppmudata;
 
-        for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++)
+        for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
                 pset->coeffs[i] = pvfe_equ_quadratic->coeffs[i];
+        }
 
         return status;
 }
@@ -547,8 +548,9 @@ static u32 vfe_equ_construct_quadratic(struct gk20a *g,
         pvfeequ->super.super.pmudatainit =
                         _vfe_equ_pmudatainit_quadratic;
 
-        for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++)
+        for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
                 pvfeequ->coeffs[i] = ptmpequ->coeffs[i];
+        }
 
         return status;
 }