gpu: nvgpu: gv11b: h/w header updated for CL 38810810

H/w header updates for FPGA SNAP_0617

Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515766
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

2 files changed, 125 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
index bd2f628c..e98c9f76 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
@@ -266,10 +266,6 @@ static inline u32 fifo_intr_sched_error_code_f(u32 v)
 {
         return (v & 0xff) << 0;
 }
-static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
-{
-        return 0x0000000a;
-}
 static inline u32 fifo_intr_chsw_error_r(void)
 {
         return 0x0000256c;
@@ -308,7 +304,7 @@ static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void)
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r)
 {
-        return (r >> 0) & 0x3;
+        return (r >> 14) & 0x3;
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void)
 {
@@ -324,15 +320,15 @@ static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void)
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r)
 {
-        return (r >> 4) & 0xfff;
+        return (r >> 0) & 0x3fff;
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r)
 {
-        return (r >> 16) & 0xfff;
+        return (r >> 16) & 0x3fff;
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r)
 {
-        return (r >> 28) & 0x3;
+        return (r >> 30) & 0x3;
 }
 static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index 965f8663..6c6dea4a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -78,6 +78,10 @@ static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
 {
         return 0x40;
 }
+static inline u32 pwr_falcon_irqstat_ext_second_true_f(void)
+{
+        return 0x800;
+}
 static inline u32 pwr_falcon_irqmode_r(void)
 {
         return 0x0010a00c;
@@ -118,6 +122,38 @@ static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
 {
         return (v & 0x1) << 7;
 }
+static inline u32 pwr_falcon_irqmset_ext_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v)
+{
+        return (v & 0x1) << 9;
+}
+static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v)
+{
+        return (v & 0x1) << 12;
+}
+static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v)
+{
+        return (v & 0x1) << 13;
+}
+static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1) << 14;
+}
+static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v)
+{
+        return (v & 0x1) << 15;
+}
 static inline u32 pwr_falcon_irqmclr_r(void)
 {
         return 0x0010a014;
@@ -158,6 +194,34 @@ static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
 {
         return (v & 0xff) << 8;
 }
+static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v)
+{
+        return (v & 0x1) << 9;
+}
+static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v)
+{
+        return (v & 0x1) << 12;
+}
+static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v)
+{
+        return (v & 0x1) << 13;
+}
+static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1) << 14;
+}
+static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v)
+{
+        return (v & 0x1) << 15;
+}
 static inline u32 pwr_falcon_irqmask_r(void)
 {
         return 0x0010a018;
@@ -202,6 +266,34 @@ static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
 {
         return (v & 0xff) << 8;
 }
+static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v)
+{
+        return (v & 0x1) << 9;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v)
+{
+        return (v & 0x1) << 12;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v)
+{
+        return (v & 0x1) << 13;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1) << 14;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v)
+{
+        return (v & 0x1) << 15;
+}
 static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
 {
         return (v & 0x1) << 16;
@@ -238,6 +330,34 @@ static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
 {
         return (v & 0xff) << 24;
 }
+static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v)
+{
+        return (v & 0x1) << 25;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v)
+{
+        return (v & 0x1) << 27;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v)
+{
+        return (v & 0x1) << 28;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v)
+{
+        return (v & 0x1) << 29;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
 static inline u32 pwr_falcon_curctx_r(void)
 {
         return 0x0010a050;