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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-16 15:51:25 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-28 00:44:21 -0400
commit6662188868b824d1fa99292cff0ce82b55d180ce (patch)
treed9686e5e37dd57183ba5a146b5c33af35deb31db
parent6f57a339ee359d57e470552da18e3f487e3e0625 (diff)
gpu: nvgpu: Do not refer to RAM_IN fields in FB
Do not refer to bit width in RAM_IN field when shifting MMU fault buffer entries. Export the correct bit shift values for the fields and shift with that. Change-Id: I6878118bb14f070626e8244d5044b6818c8ea283 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801417 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv11b.c11
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h14
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h10
3 files changed, 27 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
index cf70b64d..e6996321 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
@@ -46,7 +46,6 @@
46 46
47#include <nvgpu/hw/gv11b/hw_fb_gv11b.h> 47#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
48#include <nvgpu/hw/gv11b/hw_mc_gv11b.h> 48#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
49#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
50#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> 49#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
51 50
52static int gv11b_fb_fix_page_fault(struct gk20a *g, 51static int gv11b_fb_fix_page_fault(struct gk20a *g,
@@ -375,7 +374,7 @@ void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, u32 index)
375 gv11b_fb_fault_buf_set_state_hw(g, index, 374 gv11b_fb_fault_buf_set_state_hw(g, index,
376 NVGPU_FB_MMU_FAULT_BUF_DISABLED); 375 NVGPU_FB_MMU_FAULT_BUF_DISABLED);
377 addr_lo = u64_lo32(g->mm.hw_fault_buf[index].gpu_va >> 376 addr_lo = u64_lo32(g->mm.hw_fault_buf[index].gpu_va >>
378 ram_in_base_shift_v()); 377 fb_mmu_fault_buffer_lo_addr_b());
379 addr_hi = u64_hi32(g->mm.hw_fault_buf[index].gpu_va); 378 addr_hi = u64_hi32(g->mm.hw_fault_buf[index].gpu_va);
380 379
381 g->ops.fb.write_mmu_fault_buffer_lo_hi(g, index, 380 g->ops.fb.write_mmu_fault_buffer_lo_hi(g, index,
@@ -749,7 +748,7 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
749 rd32_val = nvgpu_mem_rd32(g, mem, offset + 748 rd32_val = nvgpu_mem_rd32(g, mem, offset +
750 gmmu_fault_buf_entry_inst_lo_w()); 749 gmmu_fault_buf_entry_inst_lo_w());
751 addr_lo = gmmu_fault_buf_entry_inst_lo_v(rd32_val); 750 addr_lo = gmmu_fault_buf_entry_inst_lo_v(rd32_val);
752 addr_lo = addr_lo << ram_in_base_shift_v(); 751 addr_lo = addr_lo << gmmu_fault_buf_entry_inst_lo_b();
753 752
754 addr_hi = nvgpu_mem_rd32(g, mem, offset + 753 addr_hi = nvgpu_mem_rd32(g, mem, offset +
755 gmmu_fault_buf_entry_inst_hi_w()); 754 gmmu_fault_buf_entry_inst_hi_w());
@@ -775,7 +774,7 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
775 mmfault->fault_addr_aperture = 774 mmfault->fault_addr_aperture =
776 gmmu_fault_buf_entry_addr_phys_aperture_v(rd32_val); 775 gmmu_fault_buf_entry_addr_phys_aperture_v(rd32_val);
777 addr_lo = gmmu_fault_buf_entry_addr_lo_v(rd32_val); 776 addr_lo = gmmu_fault_buf_entry_addr_lo_v(rd32_val);
778 addr_lo = addr_lo << ram_in_base_shift_v(); 777 addr_lo = addr_lo << gmmu_fault_buf_entry_addr_lo_b();
779 778
780 rd32_val = nvgpu_mem_rd32(g, mem, offset + 779 rd32_val = nvgpu_mem_rd32(g, mem, offset +
781 gmmu_fault_buf_entry_addr_hi_w()); 780 gmmu_fault_buf_entry_addr_hi_w());
@@ -1096,7 +1095,7 @@ static void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g,
1096 g->ops.fb.read_mmu_fault_inst_lo_hi(g, &reg_val, &addr_hi); 1095 g->ops.fb.read_mmu_fault_inst_lo_hi(g, &reg_val, &addr_hi);
1097 1096
1098 addr_lo = fb_mmu_fault_inst_lo_addr_v(reg_val); 1097 addr_lo = fb_mmu_fault_inst_lo_addr_v(reg_val);
1099 addr_lo = addr_lo << ram_in_base_shift_v(); 1098 addr_lo = addr_lo << fb_mmu_fault_inst_lo_addr_b();
1100 1099
1101 addr_hi = fb_mmu_fault_inst_hi_addr_v(addr_hi); 1100 addr_hi = fb_mmu_fault_inst_hi_addr_v(addr_hi);
1102 inst_ptr = hi32_lo32_to_u64(addr_hi, addr_lo); 1101 inst_ptr = hi32_lo32_to_u64(addr_hi, addr_lo);
@@ -1121,7 +1120,7 @@ static void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g,
1121 g->ops.fb.read_mmu_fault_addr_lo_hi(g, &reg_val, &addr_hi); 1120 g->ops.fb.read_mmu_fault_addr_lo_hi(g, &reg_val, &addr_hi);
1122 1121
1123 addr_lo = fb_mmu_fault_addr_lo_addr_v(reg_val); 1122 addr_lo = fb_mmu_fault_addr_lo_addr_v(reg_val);
1124 addr_lo = addr_lo << ram_in_base_shift_v(); 1123 addr_lo = addr_lo << fb_mmu_fault_addr_lo_addr_b();
1125 1124
1126 mmfault->fault_addr_aperture = 1125 mmfault->fault_addr_aperture =
1127 fb_mmu_fault_addr_lo_phys_aperture_v(reg_val); 1126 fb_mmu_fault_addr_lo_phys_aperture_v(reg_val);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index ea3c7939..5c4477a0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -1112,6 +1112,10 @@ static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r)
1112{ 1112{
1113 return (r >> 12U) & 0xfffffU; 1113 return (r >> 12U) & 0xfffffU;
1114} 1114}
1115static inline u32 fb_mmu_fault_buffer_lo_addr_b(void)
1116{
1117 return 12U;
1118}
1115static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) 1119static inline u32 fb_mmu_fault_buffer_hi_r(u32 i)
1116{ 1120{
1117 return 0x00100e28U + i*20U; 1121 return 0x00100e28U + i*20U;
@@ -1340,6 +1344,10 @@ static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r)
1340{ 1344{
1341 return (r >> 12U) & 0xfffffU; 1345 return (r >> 12U) & 0xfffffU;
1342} 1346}
1347static inline u32 fb_mmu_fault_addr_lo_addr_b(void)
1348{
1349 return 12U;
1350}
1343static inline u32 fb_mmu_fault_addr_hi_r(void) 1351static inline u32 fb_mmu_fault_addr_hi_r(void)
1344{ 1352{
1345 return 0x00100e50U; 1353 return 0x00100e50U;
@@ -1380,6 +1388,10 @@ static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r)
1380{ 1388{
1381 return (r >> 12U) & 0xfffffU; 1389 return (r >> 12U) & 0xfffffU;
1382} 1390}
1391static inline u32 fb_mmu_fault_inst_lo_addr_b(void)
1392{
1393 return 12U;
1394}
1383static inline u32 fb_mmu_fault_inst_hi_r(void) 1395static inline u32 fb_mmu_fault_inst_hi_r(void)
1384{ 1396{
1385 return 0x00100e58U; 1397 return 0x00100e58U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
index 0a442b1f..980f54c1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -1320,6 +1320,10 @@ static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r)
1320{ 1320{
1321 return (r >> 12U) & 0xfffffU; 1321 return (r >> 12U) & 0xfffffU;
1322} 1322}
1323static inline u32 gmmu_fault_buf_entry_inst_lo_b(void)
1324{
1325 return 12U;
1326}
1323static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) 1327static inline u32 gmmu_fault_buf_entry_inst_lo_w(void)
1324{ 1328{
1325 return 0U; 1329 return 0U;
@@ -1348,6 +1352,10 @@ static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r)
1348{ 1352{
1349 return (r >> 12U) & 0xfffffU; 1353 return (r >> 12U) & 0xfffffU;
1350} 1354}
1355static inline u32 gmmu_fault_buf_entry_addr_lo_b(void)
1356{
1357 return 12U;
1358}
1351static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) 1359static inline u32 gmmu_fault_buf_entry_addr_lo_w(void)
1352{ 1360{
1353 return 2U; 1361 return 2U;