gpu: nvgpu: PMU nv_pmu_boardobj & queue update

- Updated "struct nv_pmu_boardobj, nv_pmu_boardobj_query &
  nv_pmu_boardobjgrp_super" by adding new members
  as per gv10x PMU ucode boardobj interface.
- Created "PMU_QUEUE_COUNT_FOR_V5 4" for gv10x PMU ucode
- Created "PMU_QUEUE_MSG_IDX_FOR_V5 3" for gv10x PMU ucode
- Deleted unused "PMU_QUEUE_MSG_IDX_FOR_4"
- Updating "APP_VERSION_GV10X 23616379" for ucode
  git CL: https://git-master.nvidia.com/r/#/c/1662993/
  P4 CL#: 23647491
- Updating "APP_VERSION_GP10X 22099494" for ucode
  git CL: https://git-master.nvidia.com/r/#/c/1662995/
  P4 CL#: 23647537

Change-Id: I6e8e2b30e81422f8b529a2fad6d926f93bd73d3e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 13 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c
index f20b4a78..9530e460 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -301,6 +301,7 @@ u32 boardobjgrp_pmuhdrdatainit_super(struct gk20a *g, struct boardobjgrp
         pboardobjgrppmu->type = pboardobjgrp->type;
         pboardobjgrppmu->class_id = pboardobjgrp->classid;
         pboardobjgrppmu->obj_slots = BOARDOBJGRP_PMU_SLOTS_GET(pboardobjgrp);
+        pboardobjgrppmu->flags = 0;
 
         gk20a_dbg_info(" Done");
         return 0;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 20120393..6a038317 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -37,8 +37,8 @@
 
 /* PMU F/W version */
 #define APP_VERSION_GV11B       23416738
-#define APP_VERSION_GV10X       23440730
-#define APP_VERSION_GP10X       21308030
+#define APP_VERSION_GV10X       23616379
+#define APP_VERSION_GP10X       22099494
 #define APP_VERSION_GP10B       20429989
 #define APP_VERSION_GM20B       20490253
 
@@ -897,7 +897,7 @@ static void get_pmu_init_msg_pmu_queue_params_v5(struct pmu_queue *queue,
         else if (tmp_id == PMU_COMMAND_QUEUE_LPQ)
                 tmp_id = PMU_QUEUE_LPQ_IDX_FOR_V3;
         else if (tmp_id == PMU_MESSAGE_QUEUE)
-                tmp_id = PMU_QUEUE_MSG_IDX_FOR_V4;
+                tmp_id = PMU_QUEUE_MSG_IDX_FOR_V5;
         else
                 return;
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
index 2dd511de..71684f6c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -107,12 +107,13 @@ struct pmu_init_msg_pmu_v1 {
         u16 sw_managed_area_size;
 };
 
+#define PMU_QUEUE_COUNT_FOR_V5 4
 #define PMU_QUEUE_COUNT_FOR_V4 5
 #define PMU_QUEUE_COUNT_FOR_V3 3
 #define PMU_QUEUE_HPQ_IDX_FOR_V3 0
 #define PMU_QUEUE_LPQ_IDX_FOR_V3 1
 #define PMU_QUEUE_MSG_IDX_FOR_V3 2
-#define PMU_QUEUE_MSG_IDX_FOR_V4 4
+#define PMU_QUEUE_MSG_IDX_FOR_V5 3
 struct pmu_init_msg_pmu_v3 {
         u8 msg_type;
         u8  queue_index[PMU_QUEUE_COUNT_FOR_V3];
@@ -144,8 +145,8 @@ struct pmu_init_msg_pmu_v4 {
 struct pmu_init_msg_pmu_v5 {
         u8 msg_type;
         u8 flcn_status;
-        u8  queue_index[PMU_QUEUE_COUNT_FOR_V4];
-        u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
+        u8  queue_index[PMU_QUEUE_COUNT_FOR_V5];
+        u16 queue_size[PMU_QUEUE_COUNT_FOR_V5];
         u16 queue_offset;
 
         u16 sw_managed_area_offset;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
index b8c1e394..697f95bc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -43,6 +43,7 @@
  */
 struct nv_pmu_boardobj {
         u8 type;
+        u8 grp_idx;
 };
 
 /*
@@ -51,6 +52,7 @@ struct nv_pmu_boardobj {
  */
 struct nv_pmu_boardobj_query {
         u8 type;
+        u8 grp_idx;
 };
 
 /*
@@ -61,7 +63,7 @@ struct nv_pmu_boardobjgrp_super {
         u8 type;
         u8 class_id;
         u8 obj_slots;
-        u8 rsvd;
+        u8 flags;
 };
 
 struct nv_pmu_boardobjgrp {