diff options
author | Adeel Raza <araza@nvidia.com> | 2014-12-22 19:16:29 -0500 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:03 -0500 |
commit | 6056528af809a9a861149e218bcaff250f964eea (patch) | |
tree | c2ac5a6886469bb67a2219ce17f30332f86ef7f2 | |
parent | 587a7b1e931d421b7526a0328c2c82ee78075f0c (diff) |
gpu: nvgpu: headers for linsim CL 34000094
Change-Id: I43380fda328414e96601e1c03c3e0ec28c0b4871
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/666905
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 6 |
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index d2629b08..d10345c3 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | |||
@@ -276,23 +276,23 @@ static inline u32 fifo_intr_mmu_fault_info_r(u32 i) | |||
276 | } | 276 | } |
277 | static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) | 277 | static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) |
278 | { | 278 | { |
279 | return (r >> 0) & 0xf; | 279 | return (r >> 0) & 0x1f; |
280 | } | 280 | } |
281 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) | 281 | static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) |
282 | { | 282 | { |
283 | return (r >> 6) & 0x1; | 283 | return (r >> 20) & 0x1; |
284 | } | 284 | } |
285 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) | 285 | static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) |
286 | { | 286 | { |
287 | return 0x00000000; | 287 | return 0x00000000; |
288 | } | 288 | } |
289 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) | 289 | static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) |
290 | { | 290 | { |
291 | return 0x00000001; | 291 | return 0x00000001; |
292 | } | 292 | } |
293 | static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) | 293 | static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) |
294 | { | 294 | { |
295 | return (r >> 8) & 0x3f; | 295 | return (r >> 8) & 0x7f; |
296 | } | 296 | } |
297 | static inline u32 fifo_intr_pbdma_id_r(void) | 297 | static inline u32 fifo_intr_pbdma_id_r(void) |
298 | { | 298 | { |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index 272f7fb3..cdb28d08 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | |||
@@ -64,15 +64,15 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) | |||
64 | } | 64 | } |
65 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) | 65 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) |
66 | { | 66 | { |
67 | return (v & 0x3) << 0; | 67 | return (v & 0xff) << 0; |
68 | } | 68 | } |
69 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) | 69 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) |
70 | { | 70 | { |
71 | return 0x3 << 0; | 71 | return 0xff << 0; |
72 | } | 72 | } |
73 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) | 73 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) |
74 | { | 74 | { |
75 | return (r >> 0) & 0x3; | 75 | return (r >> 0) & 0xff; |
76 | } | 76 | } |
77 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) | 77 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) |
78 | { | 78 | { |