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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-05-24 18:25:41 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commit5215d65c25b5e76c19d9d12b03c52f69e2d40227 (patch)
tree36991e3113ace2bb3c6cd1dc1164c5288412c13d
parentf9a2f449a5f4dd62fcfb1701d69dc40f97a827ff (diff)
gpu: nvgpu: Remove setting of PRI timeout
PRI timeout should always use the HW initialization value. Do not set it explicitly. JIRA NVGPU-588 Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730892 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/bus/bus_gk20a.c19
-rw-r--r--drivers/gpu/nvgpu/common/linux/driver_common.c1
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c9
-rw-r--r--drivers/gpu/nvgpu/common/linux/platform_gk20a.h5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
5 files changed, 2 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
index d173123d..9f0446c6 100644
--- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
@@ -32,29 +32,14 @@
32 32
33void gk20a_bus_init_hw(struct gk20a *g) 33void gk20a_bus_init_hw(struct gk20a *g)
34{ 34{
35 u32 timeout_period, intr_en_mask = 0; 35 u32 intr_en_mask = 0;
36
37 if (nvgpu_platform_is_silicon(g))
38 timeout_period = g->default_pri_timeout ?
39 g->default_pri_timeout : 0x186A0;
40 else
41 timeout_period = 0x186A0;
42 36
43 if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) { 37 if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
44 intr_en_mask = bus_intr_en_0_pri_squash_m() | 38 intr_en_mask = bus_intr_en_0_pri_squash_m() |
45 bus_intr_en_0_pri_fecserr_m() | 39 bus_intr_en_0_pri_fecserr_m() |
46 bus_intr_en_0_pri_timeout_m(); 40 bus_intr_en_0_pri_timeout_m();
47 gk20a_writel(g,
48 timer_pri_timeout_r(),
49 timer_pri_timeout_period_f(timeout_period) |
50 timer_pri_timeout_en_en_enabled_f());
51
52 } else {
53 gk20a_writel(g,
54 timer_pri_timeout_r(),
55 timer_pri_timeout_period_f(timeout_period) |
56 timer_pri_timeout_en_en_disabled_f());
57 } 41 }
42
58 gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask); 43 gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask);
59} 44}
60 45
diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c
index 2475912a..8f33c5d2 100644
--- a/drivers/gpu/nvgpu/common/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/common/linux/driver_common.c
@@ -158,7 +158,6 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
158 __nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG, 158 __nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG,
159 nvgpu_platform_is_silicon(g) ? platform->can_blcg : false); 159 nvgpu_platform_is_silicon(g) ? platform->can_blcg : false);
160 160
161 g->default_pri_timeout = platform->default_pri_timeout;
162 g->aggressive_sync_destroy = platform->aggressive_sync_destroy; 161 g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
163 g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh; 162 g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
164 g->has_syncpoints = platform->has_syncpoints; 163 g->has_syncpoints = platform->has_syncpoints;
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index 70125cbc..3d3c2a9f 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -90,7 +90,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
90 .can_slcg = true, 90 .can_slcg = true,
91 .can_blcg = true, 91 .can_blcg = true,
92 .can_elcg = true, 92 .can_elcg = true,
93 .default_pri_timeout = 0x3ff,
94 93
95 .disable_aspm = true, 94 .disable_aspm = true,
96 95
@@ -127,7 +126,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
127 .can_slcg = true, 126 .can_slcg = true,
128 .can_blcg = true, 127 .can_blcg = true,
129 .can_elcg = true, 128 .can_elcg = true,
130 .default_pri_timeout = 0x3ff,
131 129
132 .disable_aspm = true, 130 .disable_aspm = true,
133 131
@@ -164,7 +162,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
164 .can_slcg = true, 162 .can_slcg = true,
165 .can_blcg = true, 163 .can_blcg = true,
166 .can_elcg = true, 164 .can_elcg = true,
167 .default_pri_timeout = 0x3ff,
168 165
169 .disable_aspm = true, 166 .disable_aspm = true,
170 167
@@ -201,7 +198,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
201 .can_slcg = true, 198 .can_slcg = true,
202 .can_blcg = true, 199 .can_blcg = true,
203 .can_elcg = true, 200 .can_elcg = true,
204 .default_pri_timeout = 0x3ff,
205 201
206 .disable_aspm = true, 202 .disable_aspm = true,
207 203
@@ -238,7 +234,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
238 .can_slcg = false, 234 .can_slcg = false,
239 .can_blcg = false, 235 .can_blcg = false,
240 .can_elcg = false, 236 .can_elcg = false,
241 .default_pri_timeout = 0x3ff,
242 237
243 .disable_aspm = true, 238 .disable_aspm = true,
244 239
@@ -273,7 +268,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
273 .can_slcg = false, 268 .can_slcg = false,
274 .can_blcg = false, 269 .can_blcg = false,
275 .can_elcg = false, 270 .can_elcg = false,
276 .default_pri_timeout = 0x3ff,
277 271
278 .disable_aspm = true, 272 .disable_aspm = true,
279 273
@@ -308,7 +302,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
308 .can_slcg = false, 302 .can_slcg = false,
309 .can_blcg = false, 303 .can_blcg = false,
310 .can_elcg = false, 304 .can_elcg = false,
311 .default_pri_timeout = 0x3ff,
312 305
313 .disable_aspm = true, 306 .disable_aspm = true,
314 307
@@ -344,7 +337,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
344 .can_slcg = true, 337 .can_slcg = true,
345 .can_blcg = true, 338 .can_blcg = true,
346 .can_elcg = true, 339 .can_elcg = true,
347 .default_pri_timeout = 0x3ff,
348 340
349 .disable_aspm = true, 341 .disable_aspm = true,
350 342
@@ -380,7 +372,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
380 .can_slcg = false, 372 .can_slcg = false,
381 .can_blcg = false, 373 .can_blcg = false,
382 .can_elcg = false, 374 .can_elcg = false,
383 .default_pri_timeout = 0x3ff,
384 375
385 .disable_aspm = true, 376 .disable_aspm = true,
386 377
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
index 07e72247..9a99b7fe 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
@@ -120,11 +120,6 @@ struct gk20a_platform {
120 */ 120 */
121 bool force_reset_in_do_idle; 121 bool force_reset_in_do_idle;
122 122
123 /* default pri timeout, on PCIe it should be lower than timeout
124 * detection
125 */
126 u32 default_pri_timeout;
127
128 /* guest/vm id, needed for IPA to PA transation */ 123 /* guest/vm id, needed for IPA to PA transation */
129 int vmid; 124 int vmid;
130 125
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f6b0b362..2a9fb57c 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1353,8 +1353,6 @@ struct gk20a {
1353 bool forced_reset; 1353 bool forced_reset;
1354 bool allow_all; 1354 bool allow_all;
1355 1355
1356 u32 default_pri_timeout;
1357
1358 u32 ptimer_src_freq; 1356 u32 ptimer_src_freq;
1359 1357
1360 bool can_railgate; 1358 bool can_railgate;