gpu: nvgpu: Pull latest gp10b headers

HWCL 38000754

Bug 1819874

Change-Id: Ic28bd2abee4caac83c2d21b035a64558d72aa0fa
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1301674
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 24 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
index eef9a96f..9048f230 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -258,6 +258,14 @@ static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(v
 {
         return 0x0;
 }
+static inline u32 ctxsw_prog_main_image_pmu_options_o(void)
+{
+        return 0x00000070;
+}
+static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
 static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
 {
         return 0x00000080;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
index 2b1acf2f..76428c44 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -124,7 +124,7 @@ static inline u32 fuse_status_opt_fbp_r(void)
 }
 static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
-        return (r >> (0 + i*0)) & 0x1;
+        return (r >> (0 + i*1)) & 0x1;
 }
 static inline u32 fuse_opt_ecc_en_r(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index 9e3137e7..6bef30e0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2534,6 +2534,18 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
 {
         return 0x80000000;
 }
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
+{
+        return 0x00419a3c;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
+{
+        return 0x1 << 2;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
         return 0x0041a0ac;