gpu: nvgpu: nvhost: PC_SAMPLING ioctl failure.

NVGPU_DBG_GPU_IOCTL_PC_SAMPLING ioctl is not handled properly for HV
case for both Linux and QNX. Currently guest vm is trying to perform
gpu memory read and write operations which supposed to be done by RM
server, causing the crash. This patch is supposed to fix ioctl failure.

Bug 2052040

Change-Id: Ia0773959b84739a1bced858331764751520a3561
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708102
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 41 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index f34fc5e7..4e6f2cd1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -117,6 +117,7 @@ enum {
         TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78,
         TEGRA_VGPU_CMD_MAP_SYNCPT = 79,
         TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80,
+        TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING = 81,
 };
 
 struct tegra_vgpu_connect_params {
@@ -354,12 +355,21 @@ enum {
         TEGRA_VGPU_CTXSW_MODE_CTXSW,
 };
 
+enum {
+        TEGRA_VGPU_DISABLE_SAMPLING = 0,
+        TEGRA_VGPU_ENABLE_SAMPLING,
+};
 struct tegra_vgpu_channel_set_ctxsw_mode {
         u64 handle;
         u64 gpu_va;
         u32 mode;
 };
 
+struct tegra_vgpu_channel_update_pc_sampling {
+        u64 handle;
+        u32 mode;
+};
+
 struct tegra_vgpu_channel_free_hwpm_ctx {
         u64 handle;
 };
@@ -638,6 +648,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_free_ctx_header_params free_ctx_header;
                 struct tegra_vgpu_map_syncpt_params map_syncpt;
                 struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
+                struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling;
                 char padding[192];
         } params;
 };
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 6b593359..5630e406 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -139,7 +139,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .update_ctxsw_preemption_mode =
                         gr_gp10b_update_ctxsw_preemption_mode,
                 .dump_gr_regs = NULL,
-                .update_pc_sampling = gr_gm20b_update_pc_sampling,
+                .update_pc_sampling = vgpu_gr_update_pc_sampling,
                 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
                 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
                 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 1e633d5f..9d765984 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -1310,3 +1310,30 @@ int vgpu_gr_init_fs_state(struct gk20a *g)
 
         return g->ops.gr.init_sm_id_table(g);
 }
+
+int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable)
+{
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_channel_update_pc_sampling *p =
+                                                &msg.params.update_pc_sampling;
+        struct gk20a *g;
+        int err = -EINVAL;
+
+        if (!ch->g)
+                return err;
+        g = ch->g;
+        nvgpu_log_fn(g, " ");
+
+        msg.cmd = TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING;
+        msg.handle = vgpu_get_handle(g);
+        p->handle = ch->virt_ctx;
+        if (enable)
+                p->mode = TEGRA_VGPU_ENABLE_SAMPLING;
+        else
+                p->mode = TEGRA_VGPU_DISABLE_SAMPLING;
+
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        WARN_ON(err || msg.ret);
+
+        return err ? err : msg.ret;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index d6b25b97..c4b3944e 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -70,5 +70,5 @@ int vgpu_gr_resume_contexts(struct gk20a *g,
 int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
 int vgpu_gr_init_sm_id_table(struct gk20a *g);
 int vgpu_gr_init_fs_state(struct gk20a *g);
-
+int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);
 #endif
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 1b78a4c9..7b536329 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -156,7 +156,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .update_ctxsw_preemption_mode =
                         gr_gv11b_update_ctxsw_preemption_mode,
                 .dump_gr_regs = NULL,
-                .update_pc_sampling = gr_gm20b_update_pc_sampling,
+                .update_pc_sampling = vgpu_gr_update_pc_sampling,
                 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
                 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
                 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,