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authorPeter Daifuku <pdaifuku@nvidia.com>2017-10-06 18:38:11 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-13 18:20:19 -0400
commit4b8dc71de5696679f13f8863bc5775a23e786b34 (patch)
treed81dfac48102afc7a5067213f264b4d016bd3aaa
parent7612e412151c676c4e7af08839bd98d879a25dea (diff)
gpu: nvgpu: vgpu: flatten out t19x vgpu hal
Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574619 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.h3
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c16
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h5
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c10
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h4
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c618
7 files changed, 619 insertions, 39 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 4a289d8f..4241145a 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -94,7 +94,7 @@
94#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> 94#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
95#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> 95#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
96 96
97static int gv11b_get_litter_value(struct gk20a *g, int value) 97int gv11b_get_litter_value(struct gk20a *g, int value)
98{ 98{
99 int ret = EINVAL; 99 int ret = EINVAL;
100 switch (value) { 100 switch (value) {
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
index 0fdda6f3..668353dc 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Tegra HAL interface 2 * GV11B Tegra HAL interface
3 * 3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,5 @@
27struct gk20a; 27struct gk20a;
28 28
29int gv11b_init_hal(struct gk20a *gops); 29int gv11b_init_hal(struct gk20a *gops);
30int gv11b_get_litter_value(struct gk20a *g, int value);
30#endif 31#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c
index ff13b11f..048a4c64 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c
@@ -21,14 +21,10 @@
21 */ 21 */
22 22
23#include <gk20a/gk20a.h> 23#include <gk20a/gk20a.h>
24#include <vgpu/gp10b/vgpu_fifo_gp10b.h>
25 24
26#include "vgpu/vgpu.h" 25#include "vgpu/vgpu.h"
27 26
28#include "vgpu_fifo_gv11b.h" 27int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
29#include "vgpu_subctx_gv11b.h"
30
31static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
32{ 28{
33 struct fifo_gk20a *f = &g->fifo; 29 struct fifo_gk20a *f = &g->fifo;
34 int err; 30 int err;
@@ -43,13 +39,3 @@ static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
43 39
44 return 0; 40 return 0;
45} 41}
46
47void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops)
48{
49 vgpu_gp10b_init_fifo_ops(gops);
50
51 gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw;
52 gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header;
53 /* TODO: implement it for CE fault */
54 gops->fifo.tsg_verify_status_faulted = NULL;
55}
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h
index b3c7f729..03404542 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h
@@ -23,8 +23,7 @@
23#ifndef _VGPU_FIFO_GV11B_H_ 23#ifndef _VGPU_FIFO_GV11B_H_
24#define _VGPU_FIFO_GV11B_H_ 24#define _VGPU_FIFO_GV11B_H_
25 25
26struct gpu_ops; 26struct gk20a;
27
28void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops);
29 27
28int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g);
30#endif 29#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c
index a3d1cd90..89952221 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c
@@ -22,12 +22,10 @@
22 22
23#include <gk20a/gk20a.h> 23#include <gk20a/gk20a.h>
24#include <vgpu/gr_vgpu.h> 24#include <vgpu/gr_vgpu.h>
25#include <vgpu/gp10b/vgpu_gr_gp10b.h>
26 25
27#include "vgpu_gr_gv11b.h"
28#include "vgpu_subctx_gv11b.h" 26#include "vgpu_subctx_gv11b.h"
29 27
30static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) 28int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
31{ 29{
32 int err; 30 int err;
33 31
@@ -41,9 +39,3 @@ static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
41 39
42 return err; 40 return err;
43} 41}
44
45void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops)
46{
47 vgpu_gp10b_init_gr_ops(gops);
48 gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst;
49}
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h
index 933aa06b..562198ca 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h
@@ -23,6 +23,8 @@
23#ifndef _VGPU_GR_GV11B_H_ 23#ifndef _VGPU_GR_GV11B_H_
24#define _VGPU_GR_GV11B_H_ 24#define _VGPU_GR_GV11B_H_
25 25
26void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops); 26struct channel_gk20a;
27
28int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
27 29
28#endif 30#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 34f1198f..aa661d66 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -23,27 +23,627 @@
23#include <gk20a/gk20a.h> 23#include <gk20a/gk20a.h>
24#include <gv11b/hal_gv11b.h> 24#include <gv11b/hal_gv11b.h>
25#include <vgpu/vgpu.h> 25#include <vgpu/vgpu.h>
26#include <vgpu/fifo_vgpu.h>
27#include <vgpu/gr_vgpu.h>
28#include <vgpu/ltc_vgpu.h>
29#include <vgpu/mm_vgpu.h>
30#include <vgpu/dbg_vgpu.h>
31#include <vgpu/fecs_trace_vgpu.h>
32#include <vgpu/css_vgpu.h>
26#include <vgpu/vgpu_t19x.h> 33#include <vgpu/vgpu_t19x.h>
34#include <vgpu/gm20b/vgpu_gr_gm20b.h>
27#include <vgpu/gp10b/vgpu_mm_gp10b.h> 35#include <vgpu/gp10b/vgpu_mm_gp10b.h>
36#include <vgpu/gp10b/vgpu_gr_gp10b.h>
37
38#include <gk20a/fb_gk20a.h>
39#include <gk20a/flcn_gk20a.h>
40#include <gk20a/bus_gk20a.h>
41#include <gk20a/mc_gk20a.h>
42
43#include <gm20b/gr_gm20b.h>
44#include <gm20b/fb_gm20b.h>
45#include <gm20b/fifo_gm20b.h>
46#include <gm20b/pmu_gm20b.h>
47#include <gm20b/mm_gm20b.h>
48#include <gm20b/acr_gm20b.h>
49#include <gm20b/ltc_gm20b.h>
50
51#include <gp10b/fb_gp10b.h>
52#include <gp10b/pmu_gp10b.h>
53#include <gp10b/mm_gp10b.h>
54#include <gp10b/mc_gp10b.h>
55#include <gp10b/ce_gp10b.h>
56#include <gp10b/fifo_gp10b.h>
57#include <gp10b/therm_gp10b.h>
58#include <gp10b/priv_ring_gp10b.h>
59#include <gp10b/ltc_gp10b.h>
60
61#include <gp106/pmu_gp106.h>
62#include <gp106/acr_gp106.h>
63
64#include <gv11b/fb_gv11b.h>
65#include <gv11b/pmu_gv11b.h>
66#include <gv11b/acr_gv11b.h>
67#include <gv11b/mm_gv11b.h>
68#include <gv11b/mc_gv11b.h>
69#include <gv11b/ce_gv11b.h>
70#include <gv11b/fifo_gv11b.h>
71#include <gv11b/therm_gv11b.h>
72#include <gv11b/regops_gv11b.h>
73#include <gv11b/gr_ctx_gv11b.h>
74#include <gv11b/ltc_gv11b.h>
75#include <gv11b/gv11b_gating_reglist.h>
76
77#include <nvgpu/enabled.h>
28 78
29#include "vgpu_gr_gv11b.h" 79#include "vgpu_gr_gv11b.h"
30#include "vgpu_fifo_gv11b.h" 80#include "vgpu_fifo_gv11b.h"
81#include "vgpu_subctx_gv11b.h"
82
83#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
84#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
85#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
86#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
87#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
88
89static const struct gpu_ops vgpu_gv11b_ops = {
90 .ltc = {
91 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
92 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
93 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
94 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
95 .init_cbc = NULL,
96 .init_fs_state = vgpu_ltc_init_fs_state,
97 .init_comptags = vgpu_ltc_init_comptags,
98 .cbc_ctrl = NULL,
99 .isr = gv11b_ltc_isr,
100 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
101 .flush = gm20b_flush_ltc,
102 .set_enabled = gp10b_ltc_set_enabled,
103 },
104 .ce2 = {
105 .isr_stall = gv11b_ce_isr,
106 .isr_nonstall = gp10b_ce_nonstall_isr,
107 .get_num_pce = vgpu_ce_get_num_pce,
108 },
109 .gr = {
110 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
111 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
112 .cb_size_default = gr_gv11b_cb_size_default,
113 .calc_global_ctx_buffer_size =
114 gr_gv11b_calc_global_ctx_buffer_size,
115 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
116 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
117 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
118 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
119 .handle_sw_method = gr_gv11b_handle_sw_method,
120 .set_alpha_circular_buffer_size =
121 gr_gv11b_set_alpha_circular_buffer_size,
122 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
123 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
124 .is_valid_class = gr_gv11b_is_valid_class,
125 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
126 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
127 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
128 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
129 .init_fs_state = vgpu_gm20b_init_fs_state,
130 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
131 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
132 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
133 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
134 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
135 .free_channel_ctx = vgpu_gr_free_channel_ctx,
136 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
137 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
138 .get_zcull_info = vgpu_gr_get_zcull_info,
139 .is_tpc_addr = gr_gm20b_is_tpc_addr,
140 .get_tpc_num = gr_gm20b_get_tpc_num,
141 .detect_sm_arch = vgpu_gr_detect_sm_arch,
142 .add_zbc_color = gr_gp10b_add_zbc_color,
143 .add_zbc_depth = gr_gp10b_add_zbc_depth,
144 .zbc_set_table = vgpu_gr_add_zbc,
145 .zbc_query_table = vgpu_gr_query_zbc,
146 .pmu_save_zbc = gk20a_pmu_save_zbc,
147 .add_zbc = gr_gk20a_add_zbc,
148 .pagepool_default_size = gr_gv11b_pagepool_default_size,
149 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
150 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
151 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
152 .update_ctxsw_preemption_mode =
153 gr_gp10b_update_ctxsw_preemption_mode,
154 .dump_gr_regs = NULL,
155 .update_pc_sampling = gr_gm20b_update_pc_sampling,
156 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
157 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
158 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
159 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
160 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
161 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
162 .wait_empty = gr_gv11b_wait_empty,
163 .init_cyclestats = gr_gv11b_init_cyclestats,
164 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
165 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
166 .bpt_reg_info = gv11b_gr_bpt_reg_info,
167 .get_access_map = gr_gv11b_get_access_map,
168 .handle_fecs_error = gr_gv11b_handle_fecs_error,
169 .handle_sm_exception = gr_gk20a_handle_sm_exception,
170 .handle_tex_exception = gr_gv11b_handle_tex_exception,
171 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
172 .enable_exceptions = gr_gv11b_enable_exceptions,
173 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
174 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
175 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
176 .record_sm_error_state = gv11b_gr_record_sm_error_state,
177 .update_sm_error_state = gv11b_gr_update_sm_error_state,
178 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
179 .suspend_contexts = vgpu_gr_suspend_contexts,
180 .resume_contexts = vgpu_gr_resume_contexts,
181 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
182 .fuse_override = gp10b_gr_fuse_override,
183 .init_sm_id_table = gr_gv11b_init_sm_id_table,
184 .load_smid_config = gr_gv11b_load_smid_config,
185 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
186 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
187 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
188 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
189 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
190 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
191 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
192 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
193 .commit_inst = vgpu_gr_gv11b_commit_inst,
194 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
195 .write_pm_ptr = gr_gv11b_write_pm_ptr,
196 .init_elcg_mode = gr_gv11b_init_elcg_mode,
197 .load_tpc_mask = gr_gv11b_load_tpc_mask,
198 .inval_icache = gr_gk20a_inval_icache,
199 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
200 .wait_for_pause = gr_gk20a_wait_for_pause,
201 .resume_from_pause = gv11b_gr_resume_from_pause,
202 .clear_sm_errors = gr_gk20a_clear_sm_errors,
203 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
204 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
205 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
206 .suspend_single_sm = gv11b_gr_suspend_single_sm,
207 .suspend_all_sms = gv11b_gr_suspend_all_sms,
208 .resume_single_sm = gv11b_gr_resume_single_sm,
209 .resume_all_sms = gv11b_gr_resume_all_sms,
210 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
211 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
212 .get_sm_no_lock_down_hww_global_esr_mask =
213 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
214 .lock_down_sm = gv11b_gr_lock_down_sm,
215 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
216 .clear_sm_hww = gv11b_gr_clear_sm_hww,
217 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
218 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
219 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
220 .set_boosted_ctx = NULL,
221 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
222 .set_czf_bypass = NULL,
223 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
224 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
225 .init_preemption_state = NULL,
226 .update_boosted_ctx = NULL,
227 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
228 .create_gr_sysfs = gr_gv11b_create_sysfs,
229 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
230 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
231 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
232 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
233 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
234 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
235 .restore_context_header = gv11b_restore_context_header,
236 .handle_gpc_gpcmmu_exception =
237 gr_gv11b_handle_gpc_gpcmmu_exception,
238 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
239 .get_egpc_base = gv11b_gr_get_egpc_base,
240 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
241 .handle_gpc_gpccs_exception =
242 gr_gv11b_handle_gpc_gpccs_exception,
243 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
244 .access_smpc_reg = gv11b_gr_access_smpc_reg,
245 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
246 .add_zbc_s = gr_gv11b_add_zbc_stencil,
247 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
248 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
249 .handle_tpc_sm_ecc_exception =
250 gr_gv11b_handle_tpc_sm_ecc_exception,
251 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
252 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
253 },
254 .fb = {
255 .reset = gv11b_fb_reset,
256 .init_hw = gk20a_fb_init_hw,
257 .init_fs_state = gv11b_fb_init_fs_state,
258 .init_cbc = gv11b_fb_init_cbc,
259 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
260 .set_use_full_comp_tag_line =
261 gm20b_fb_set_use_full_comp_tag_line,
262 .compression_page_size = gp10b_fb_compression_page_size,
263 .compressible_page_size = gp10b_fb_compressible_page_size,
264 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
265 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
266 .read_wpr_info = gm20b_fb_read_wpr_info,
267 .is_debug_mode_enabled = NULL,
268 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
269 .tlb_invalidate = vgpu_mm_tlb_invalidate,
270 .hub_isr = gv11b_fb_hub_isr,
271 },
272 .clock_gating = {
273 .slcg_bus_load_gating_prod =
274 gv11b_slcg_bus_load_gating_prod,
275 .slcg_ce2_load_gating_prod =
276 gv11b_slcg_ce2_load_gating_prod,
277 .slcg_chiplet_load_gating_prod =
278 gv11b_slcg_chiplet_load_gating_prod,
279 .slcg_ctxsw_firmware_load_gating_prod =
280 gv11b_slcg_ctxsw_firmware_load_gating_prod,
281 .slcg_fb_load_gating_prod =
282 gv11b_slcg_fb_load_gating_prod,
283 .slcg_fifo_load_gating_prod =
284 gv11b_slcg_fifo_load_gating_prod,
285 .slcg_gr_load_gating_prod =
286 gr_gv11b_slcg_gr_load_gating_prod,
287 .slcg_ltc_load_gating_prod =
288 ltc_gv11b_slcg_ltc_load_gating_prod,
289 .slcg_perf_load_gating_prod =
290 gv11b_slcg_perf_load_gating_prod,
291 .slcg_priring_load_gating_prod =
292 gv11b_slcg_priring_load_gating_prod,
293 .slcg_pmu_load_gating_prod =
294 gv11b_slcg_pmu_load_gating_prod,
295 .slcg_therm_load_gating_prod =
296 gv11b_slcg_therm_load_gating_prod,
297 .slcg_xbar_load_gating_prod =
298 gv11b_slcg_xbar_load_gating_prod,
299 .blcg_bus_load_gating_prod =
300 gv11b_blcg_bus_load_gating_prod,
301 .blcg_ce_load_gating_prod =
302 gv11b_blcg_ce_load_gating_prod,
303 .blcg_ctxsw_firmware_load_gating_prod =
304 gv11b_blcg_ctxsw_firmware_load_gating_prod,
305 .blcg_fb_load_gating_prod =
306 gv11b_blcg_fb_load_gating_prod,
307 .blcg_fifo_load_gating_prod =
308 gv11b_blcg_fifo_load_gating_prod,
309 .blcg_gr_load_gating_prod =
310 gv11b_blcg_gr_load_gating_prod,
311 .blcg_ltc_load_gating_prod =
312 gv11b_blcg_ltc_load_gating_prod,
313 .blcg_pwr_csb_load_gating_prod =
314 gv11b_blcg_pwr_csb_load_gating_prod,
315 .blcg_pmu_load_gating_prod =
316 gv11b_blcg_pmu_load_gating_prod,
317 .blcg_xbar_load_gating_prod =
318 gv11b_blcg_xbar_load_gating_prod,
319 .pg_gr_load_gating_prod =
320 gr_gv11b_pg_gr_load_gating_prod,
321 },
322 .fifo = {
323 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
324 .bind_channel = vgpu_channel_bind,
325 .unbind_channel = vgpu_channel_unbind,
326 .disable_channel = vgpu_channel_disable,
327 .enable_channel = vgpu_channel_enable,
328 .alloc_inst = vgpu_channel_alloc_inst,
329 .free_inst = vgpu_channel_free_inst,
330 .setup_ramfc = vgpu_channel_setup_ramfc,
331 .channel_set_priority = vgpu_channel_set_priority,
332 .channel_set_timeslice = vgpu_channel_set_timeslice,
333 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
334 .setup_userd = gk20a_fifo_setup_userd,
335 .userd_gp_get = gv11b_userd_gp_get,
336 .userd_gp_put = gv11b_userd_gp_put,
337 .userd_pb_get = gv11b_userd_pb_get,
338 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
339 .preempt_channel = vgpu_fifo_preempt_channel,
340 .preempt_tsg = vgpu_fifo_preempt_tsg,
341 .enable_tsg = gk20a_enable_tsg,
342 .disable_tsg = gk20a_disable_tsg,
343 .tsg_verify_channel_status = NULL,
344 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
345 /* TODO: implement it for CE fault */
346 .tsg_verify_status_faulted = NULL,
347 .update_runlist = vgpu_fifo_update_runlist,
348 .trigger_mmu_fault = NULL,
349 .get_mmu_fault_info = NULL,
350 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
351 .get_num_fifos = gv11b_fifo_get_num_fifos,
352 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
353 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
354 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
355 .tsg_open = vgpu_tsg_open,
356 .force_reset_ch = vgpu_fifo_force_reset_ch,
357 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
358 .device_info_data_parse = gp10b_device_info_data_parse,
359 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
360 .init_engine_info = vgpu_fifo_init_engine_info,
361 .runlist_entry_size = ram_rl_entry_size_v,
362 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
363 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
364 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
365 .dump_pbdma_status = gk20a_dump_pbdma_status,
366 .dump_eng_status = gv11b_dump_eng_status,
367 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
368 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
369 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
370 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
371 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
372 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
373 .handle_sched_error = gv11b_fifo_handle_sched_error,
374 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
375 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
376 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
377 .deinit_eng_method_buffers =
378 gv11b_fifo_deinit_eng_method_buffers,
379 .tsg_bind_channel = vgpu_tsg_bind_channel,
380 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
381#ifdef CONFIG_TEGRA_GK20A_NVHOST
382 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
383 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
384 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
385 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
386 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
387 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
388#endif
389 .resetup_ramfc = NULL,
390 .reschedule_runlist = NULL,
391 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
392 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
393 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
394 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
395 },
396 .gr_ctx = {
397 .get_netlist_name = gr_gv11b_get_netlist_name,
398 .is_fw_defined = gr_gv11b_is_firmware_defined,
399 },
400#ifdef CONFIG_GK20A_CTXSW_TRACE
401 .fecs_trace = {
402 .alloc_user_buffer = NULL,
403 .free_user_buffer = NULL,
404 .mmap_user_buffer = NULL,
405 .init = NULL,
406 .deinit = NULL,
407 .enable = NULL,
408 .disable = NULL,
409 .is_enabled = NULL,
410 .reset = NULL,
411 .flush = NULL,
412 .poll = NULL,
413 .bind_channel = NULL,
414 .unbind_channel = NULL,
415 .max_entries = NULL,
416 },
417#endif /* CONFIG_GK20A_CTXSW_TRACE */
418 .mm = {
419 /* FIXME: add support for sparse mappings */
420 .support_sparse = NULL,
421 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
422 .gmmu_unmap = vgpu_locked_gmmu_unmap,
423 .vm_bind_channel = vgpu_vm_bind_channel,
424 .fb_flush = vgpu_mm_fb_flush,
425 .l2_invalidate = vgpu_mm_l2_invalidate,
426 .l2_flush = vgpu_mm_l2_flush,
427 .cbc_clean = gk20a_mm_cbc_clean,
428 .set_big_page_size = gm20b_mm_set_big_page_size,
429 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
430 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
431 .gpu_phys_addr = gm20b_gpu_phys_addr,
432 .get_iommu_bit = gk20a_mm_get_iommu_bit,
433 .get_mmu_levels = gp10b_mm_get_mmu_levels,
434 .init_pdb = gp10b_mm_init_pdb,
435 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
436 .is_bar1_supported = gv11b_mm_is_bar1_supported,
437 .init_inst_block = gv11b_init_inst_block,
438 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
439 .init_bar2_vm = gb10b_init_bar2_vm,
440 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
441 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
442 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
443 },
444 .therm = {
445 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
446 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
447 },
448 .pmu = {
449 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
450 .pmu_get_queue_head = pwr_pmu_queue_head_r,
451 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
452 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
453 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
454 .pmu_queue_head = gk20a_pmu_queue_head,
455 .pmu_queue_tail = gk20a_pmu_queue_tail,
456 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
457 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
458 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
459 .pmu_mutex_release = gk20a_pmu_mutex_release,
460 .write_dmatrfbase = gp10b_write_dmatrfbase,
461 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
462 .pmu_pg_init_param = gv11b_pg_gr_init,
463 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
464 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
465 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
466 .reset_engine = gp106_pmu_engine_reset,
467 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
468 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
469 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
470 .is_pmu_supported = gv11b_is_pmu_supported,
471 },
472 .regops = {
473 .get_global_whitelist_ranges =
474 gv11b_get_global_whitelist_ranges,
475 .get_global_whitelist_ranges_count =
476 gv11b_get_global_whitelist_ranges_count,
477 .get_context_whitelist_ranges =
478 gv11b_get_context_whitelist_ranges,
479 .get_context_whitelist_ranges_count =
480 gv11b_get_context_whitelist_ranges_count,
481 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
482 .get_runcontrol_whitelist_count =
483 gv11b_get_runcontrol_whitelist_count,
484 .get_runcontrol_whitelist_ranges =
485 gv11b_get_runcontrol_whitelist_ranges,
486 .get_runcontrol_whitelist_ranges_count =
487 gv11b_get_runcontrol_whitelist_ranges_count,
488 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
489 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
490 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
491 .get_qctl_whitelist_ranges_count =
492 gv11b_get_qctl_whitelist_ranges_count,
493 .apply_smpc_war = gv11b_apply_smpc_war,
494 },
495 .mc = {
496 .intr_enable = mc_gv11b_intr_enable,
497 .intr_unit_config = mc_gp10b_intr_unit_config,
498 .isr_stall = mc_gp10b_isr_stall,
499 .intr_stall = mc_gp10b_intr_stall,
500 .intr_stall_pause = mc_gp10b_intr_stall_pause,
501 .intr_stall_resume = mc_gp10b_intr_stall_resume,
502 .intr_nonstall = mc_gp10b_intr_nonstall,
503 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
504 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
505 .enable = gk20a_mc_enable,
506 .disable = gk20a_mc_disable,
507 .reset = gk20a_mc_reset,
508 .boot_0 = gk20a_mc_boot_0,
509 .is_intr1_pending = mc_gp10b_is_intr1_pending,
510 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
511 },
512 .debug = {
513 .show_dump = NULL,
514 },
515 .dbg_session_ops = {
516 .exec_reg_ops = vgpu_exec_regops,
517 .dbg_set_powergate = vgpu_dbg_set_powergate,
518 .check_and_set_global_reservation =
519 vgpu_check_and_set_global_reservation,
520 .check_and_set_context_reservation =
521 vgpu_check_and_set_context_reservation,
522 .release_profiler_reservation =
523 vgpu_release_profiler_reservation,
524 .perfbuffer_enable = vgpu_perfbuffer_enable,
525 .perfbuffer_disable = vgpu_perfbuffer_disable,
526 },
527 .bus = {
528 .init_hw = gk20a_bus_init_hw,
529 .isr = gk20a_bus_isr,
530 .read_ptimer = vgpu_read_ptimer,
531 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
532 .bar1_bind = NULL,
533 },
534#if defined(CONFIG_GK20A_CYCLE_STATS)
535 .css = {
536 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
537 .disable_snapshot = vgpu_css_release_snapshot_buffer,
538 .check_data_available = vgpu_css_flush_snapshots,
539 .set_handled_snapshots = NULL,
540 .allocate_perfmon_ids = NULL,
541 .release_perfmon_ids = NULL,
542 },
543#endif
544 .falcon = {
545 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
546 },
547 .priv_ring = {
548 .isr = gp10b_priv_ring_isr,
549 },
550 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
551 .get_litter_value = gv11b_get_litter_value,
552};
31 553
32int vgpu_gv11b_init_hal(struct gk20a *g) 554int vgpu_gv11b_init_hal(struct gk20a *g)
33{ 555{
34 int err; 556 struct gpu_ops *gops = &g->ops;
557 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
558 u32 val;
559 bool priv_security;
560
561 gops->ltc = vgpu_gv11b_ops.ltc;
562 gops->ce2 = vgpu_gv11b_ops.ce2;
563 gops->gr = vgpu_gv11b_ops.gr;
564 gops->fb = vgpu_gv11b_ops.fb;
565 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
566 gops->fifo = vgpu_gv11b_ops.fifo;
567 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
568 gops->mm = vgpu_gv11b_ops.mm;
569 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
570 gops->therm = vgpu_gv11b_ops.therm;
571 gops->pmu = vgpu_gv11b_ops.pmu;
572 gops->regops = vgpu_gv11b_ops.regops;
573 gops->mc = vgpu_gv11b_ops.mc;
574 gops->debug = vgpu_gv11b_ops.debug;
575 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
576 gops->bus = vgpu_gv11b_ops.bus;
577#if defined(CONFIG_GK20A_CYCLE_STATS)
578 gops->css = vgpu_gv11b_ops.css;
579#endif
580 gops->falcon = vgpu_gv11b_ops.falcon;
581 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
582
583 /* Lone functions */
584 gops->chip_init_gpu_characteristics =
585 vgpu_gv11b_ops.chip_init_gpu_characteristics;
586 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
587
588 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
589 if (val) {
590 priv_security = true;
591 pr_err("priv security is enabled\n");
592 } else {
593 priv_security = false;
594 pr_err("priv security is disabled\n");
595 }
596 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
597 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
598 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
599
600 /* priv security dependent ops */
601 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
602 /* Add in ops from gm20b acr */
603 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
604 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
605 gops->pmu.get_wpr = gm20b_wpr_info,
606 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
607 gops->pmu.pmu_populate_loader_cfg =
608 gp106_pmu_populate_loader_cfg,
609 gops->pmu.flcn_populate_bl_dmem_desc =
610 gp106_flcn_populate_bl_dmem_desc,
611 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
612 gops->pmu.falcon_clear_halt_interrupt_status =
613 clear_halt_interrupt_status,
614 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
615
616 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
617 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
618 gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
619 gops->pmu.is_priv_load = gv11b_is_priv_load,
620
621 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
622 } else {
623 /* Inherit from gk20a */
624 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
625 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
626
627 gops->pmu.load_lsfalcon_ucode = NULL;
628 gops->pmu.init_wpr_region = NULL;
629 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
35 630
36 gk20a_dbg_fn(""); 631 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
632 }
37 633
38 err = gv11b_init_hal(g); 634 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
39 if (err) 635 gv11b_init_uncompressed_kind_map();
40 return err; 636 gv11b_init_kind_attr();
637 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
41 638
42 vgpu_init_hal_common(g); 639 g->name = "gv11b";
43 vgpu_gp10b_init_mm_ops(&g->ops);
44 640
45 vgpu_gv11b_init_gr_ops(&g->ops); 641 c->twod_class = FERMI_TWOD_A;
46 vgpu_gv11b_init_fifo_ops(&g->ops); 642 c->threed_class = VOLTA_A;
643 c->compute_class = VOLTA_COMPUTE_A;
644 c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A;
645 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
646 c->dma_copy_class = VOLTA_DMA_COPY_A;
47 647
48 return 0; 648 return 0;
49} 649}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-15 23:58:29 -0400