summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-01-09 18:29:54 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-12 15:42:54 -0500
commit44a1208fecab46f6e660d0315579c86cb6f32d0a (patch)
tree0b9139a2f0a5606ace1f2f7af2ffd5e467873191
parent351f519c2e1a2424a9a09c7a6b0f5c075198b3f0 (diff)
gpu: nvgpu: vgpu: Delete gm20b support
Delete gm20b vgpu support. It has not been supported for a long time and keeping it up-to-date is extra work. Change-Id: I3c06d29a79cb83d53a25d2242247b4eeabeab310 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635126 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/Makefile2
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c37
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h30
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c562
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c5
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h1
6 files changed, 0 insertions, 637 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 47c7e7d7..8b366538 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -166,9 +166,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
166 common/linux/vgpu/tsg_vgpu.o \ 166 common/linux/vgpu/tsg_vgpu.o \
167 common/linux/vgpu/clk_vgpu.o \ 167 common/linux/vgpu/clk_vgpu.o \
168 common/linux/vgpu/css_vgpu.o \ 168 common/linux/vgpu/css_vgpu.o \
169 common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \
170 common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ 169 common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \
171 common/linux/vgpu/gm20b/vgpu_fuse_gm20b.o \
172 common/linux/vgpu/sysfs_vgpu.o 170 common/linux/vgpu/sysfs_vgpu.o
173 171
174nvgpu-$(CONFIG_COMMON_CLK) += \ 172nvgpu-$(CONFIG_COMMON_CLK) += \
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c
deleted file mode 100644
index 2ab745ab..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/enabled.h>
24
25#include "gk20a/gk20a.h"
26
27int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g)
28{
29 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
30
31 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
32 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
33 else
34 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
35
36 return 0;
37}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h
deleted file mode 100644
index 39da09fa..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _VGPU_GM20B_FUSE
24#define _VGPU_GM20B_FUSE
25
26struct gk20a;
27
28int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g);
29
30#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
deleted file mode 100644
index eeeccf62..00000000
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
+++ /dev/null
@@ -1,562 +0,0 @@
1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gm20b/hal_gm20b.h"
18#include "common/linux/vgpu/vgpu.h"
19#include "common/linux/vgpu/fifo_vgpu.h"
20#include "common/linux/vgpu/gr_vgpu.h"
21#include "common/linux/vgpu/ltc_vgpu.h"
22#include "common/linux/vgpu/mm_vgpu.h"
23#include "common/linux/vgpu/dbg_vgpu.h"
24#include "common/linux/vgpu/fecs_trace_vgpu.h"
25#include "common/linux/vgpu/css_vgpu.h"
26#include "vgpu_gr_gm20b.h"
27#include "vgpu_fuse_gm20b.h"
28
29#include "gk20a/bus_gk20a.h"
30#include "gk20a/flcn_gk20a.h"
31#include "gk20a/mc_gk20a.h"
32#include "gk20a/fb_gk20a.h"
33
34#include "gm20b/gr_gm20b.h"
35#include "gm20b/fifo_gm20b.h"
36#include "gm20b/acr_gm20b.h"
37#include "gm20b/pmu_gm20b.h"
38#include "gm20b/fb_gm20b.h"
39#include "gm20b/bus_gm20b.h"
40#include "gm20b/regops_gm20b.h"
41#include "gm20b/clk_gm20b.h"
42#include "gm20b/therm_gm20b.h"
43#include "gm20b/mm_gm20b.h"
44#include "gm20b/gr_ctx_gm20b.h"
45#include "gm20b/gm20b_gating_reglist.h"
46#include "gm20b/ltc_gm20b.h"
47
48#include <nvgpu/enabled.h>
49
50#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
51#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
52#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
53#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
54
55static const struct gpu_ops vgpu_gm20b_ops = {
56 .ltc = {
57 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
58 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
59 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
60 .init_cbc = gm20b_ltc_init_cbc,
61 .init_fs_state = vgpu_ltc_init_fs_state,
62 .init_comptags = vgpu_ltc_init_comptags,
63 .cbc_ctrl = NULL,
64 .isr = gm20b_ltc_isr,
65 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
66 .flush = gm20b_flush_ltc,
67 .set_enabled = gm20b_ltc_set_enabled,
68 },
69 .ce2 = {
70 .isr_stall = gk20a_ce2_isr,
71 .isr_nonstall = gk20a_ce2_nonstall_isr,
72 .get_num_pce = vgpu_ce_get_num_pce,
73 },
74 .gr = {
75 .get_patch_slots = gr_gk20a_get_patch_slots,
76 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
77 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
78 .cb_size_default = gr_gm20b_cb_size_default,
79 .calc_global_ctx_buffer_size =
80 gr_gm20b_calc_global_ctx_buffer_size,
81 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
82 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
83 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
84 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
85 .handle_sw_method = gr_gm20b_handle_sw_method,
86 .set_alpha_circular_buffer_size =
87 gr_gm20b_set_alpha_circular_buffer_size,
88 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
89 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
90 .is_valid_class = gr_gm20b_is_valid_class,
91 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
92 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
93 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
94 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
95 .init_fs_state = vgpu_gr_init_fs_state,
96 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
97 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
98 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
99 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
100 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
101 .free_channel_ctx = vgpu_gr_free_channel_ctx,
102 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
103 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
104 .get_zcull_info = vgpu_gr_get_zcull_info,
105 .is_tpc_addr = gr_gm20b_is_tpc_addr,
106 .get_tpc_num = gr_gm20b_get_tpc_num,
107 .detect_sm_arch = vgpu_gr_detect_sm_arch,
108 .add_zbc_color = gr_gk20a_add_zbc_color,
109 .add_zbc_depth = gr_gk20a_add_zbc_depth,
110 .zbc_set_table = vgpu_gr_add_zbc,
111 .zbc_query_table = vgpu_gr_query_zbc,
112 .pmu_save_zbc = gk20a_pmu_save_zbc,
113 .add_zbc = gr_gk20a_add_zbc,
114 .pagepool_default_size = gr_gm20b_pagepool_default_size,
115 .init_ctx_state = vgpu_gr_init_ctx_state,
116 .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
117 .free_gr_ctx = vgpu_gr_free_gr_ctx,
118 .update_ctxsw_preemption_mode =
119 gr_gm20b_update_ctxsw_preemption_mode,
120 .dump_gr_regs = NULL,
121 .update_pc_sampling = gr_gm20b_update_pc_sampling,
122 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
123 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
124 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
125 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
126 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
127 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
128 .wait_empty = gr_gk20a_wait_idle,
129 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
130 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
131 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
132 .bpt_reg_info = gr_gm20b_bpt_reg_info,
133 .get_access_map = gr_gm20b_get_access_map,
134 .handle_fecs_error = gk20a_gr_handle_fecs_error,
135 .handle_sm_exception = gr_gk20a_handle_sm_exception,
136 .handle_tex_exception = gr_gk20a_handle_tex_exception,
137 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
138 .enable_exceptions = gk20a_gr_enable_exceptions,
139 .get_lrf_tex_ltc_dram_override = NULL,
140 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
141 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
142 .record_sm_error_state = gm20b_gr_record_sm_error_state,
143 .update_sm_error_state = gm20b_gr_update_sm_error_state,
144 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
145 .suspend_contexts = vgpu_gr_suspend_contexts,
146 .resume_contexts = vgpu_gr_resume_contexts,
147 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
148 .init_sm_id_table = vgpu_gr_init_sm_id_table,
149 .load_smid_config = gr_gm20b_load_smid_config,
150 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
151 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
152 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
153 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
154 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
155 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
156 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
157 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
158 .commit_inst = vgpu_gr_commit_inst,
159 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
160 .write_pm_ptr = gr_gk20a_write_pm_ptr,
161 .init_elcg_mode = gr_gk20a_init_elcg_mode,
162 .load_tpc_mask = gr_gm20b_load_tpc_mask,
163 .inval_icache = gr_gk20a_inval_icache,
164 .trigger_suspend = gr_gk20a_trigger_suspend,
165 .wait_for_pause = gr_gk20a_wait_for_pause,
166 .resume_from_pause = gr_gk20a_resume_from_pause,
167 .clear_sm_errors = gr_gk20a_clear_sm_errors,
168 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
169 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
170 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
171 .suspend_single_sm = gk20a_gr_suspend_single_sm,
172 .suspend_all_sms = gk20a_gr_suspend_all_sms,
173 .resume_single_sm = gk20a_gr_resume_single_sm,
174 .resume_all_sms = gk20a_gr_resume_all_sms,
175 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
176 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
177 .get_sm_no_lock_down_hww_global_esr_mask =
178 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
179 .lock_down_sm = gk20a_gr_lock_down_sm,
180 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
181 .clear_sm_hww = gm20b_gr_clear_sm_hww,
182 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
183 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
184 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
185 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
186 .set_boosted_ctx = NULL,
187 .update_boosted_ctx = NULL,
188 },
189 .fb = {
190 .reset = fb_gk20a_reset,
191 .init_hw = gk20a_fb_init_hw,
192 .init_fs_state = fb_gm20b_init_fs_state,
193 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
194 .set_use_full_comp_tag_line =
195 gm20b_fb_set_use_full_comp_tag_line,
196 .compression_page_size = gm20b_fb_compression_page_size,
197 .compressible_page_size = gm20b_fb_compressible_page_size,
198 .compression_align_mask = gm20b_fb_compression_align_mask,
199 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
200 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
201 .read_wpr_info = gm20b_fb_read_wpr_info,
202 .is_debug_mode_enabled = NULL,
203 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
204 .tlb_invalidate = vgpu_mm_tlb_invalidate,
205 },
206 .clock_gating = {
207 .slcg_bus_load_gating_prod =
208 gm20b_slcg_bus_load_gating_prod,
209 .slcg_ce2_load_gating_prod =
210 gm20b_slcg_ce2_load_gating_prod,
211 .slcg_chiplet_load_gating_prod =
212 gm20b_slcg_chiplet_load_gating_prod,
213 .slcg_ctxsw_firmware_load_gating_prod =
214 gm20b_slcg_ctxsw_firmware_load_gating_prod,
215 .slcg_fb_load_gating_prod =
216 gm20b_slcg_fb_load_gating_prod,
217 .slcg_fifo_load_gating_prod =
218 gm20b_slcg_fifo_load_gating_prod,
219 .slcg_gr_load_gating_prod =
220 gr_gm20b_slcg_gr_load_gating_prod,
221 .slcg_ltc_load_gating_prod =
222 ltc_gm20b_slcg_ltc_load_gating_prod,
223 .slcg_perf_load_gating_prod =
224 gm20b_slcg_perf_load_gating_prod,
225 .slcg_priring_load_gating_prod =
226 gm20b_slcg_priring_load_gating_prod,
227 .slcg_pmu_load_gating_prod =
228 gm20b_slcg_pmu_load_gating_prod,
229 .slcg_therm_load_gating_prod =
230 gm20b_slcg_therm_load_gating_prod,
231 .slcg_xbar_load_gating_prod =
232 gm20b_slcg_xbar_load_gating_prod,
233 .blcg_bus_load_gating_prod =
234 gm20b_blcg_bus_load_gating_prod,
235 .blcg_ctxsw_firmware_load_gating_prod =
236 gm20b_blcg_ctxsw_firmware_load_gating_prod,
237 .blcg_fb_load_gating_prod =
238 gm20b_blcg_fb_load_gating_prod,
239 .blcg_fifo_load_gating_prod =
240 gm20b_blcg_fifo_load_gating_prod,
241 .blcg_gr_load_gating_prod =
242 gm20b_blcg_gr_load_gating_prod,
243 .blcg_ltc_load_gating_prod =
244 gm20b_blcg_ltc_load_gating_prod,
245 .blcg_pwr_csb_load_gating_prod =
246 gm20b_blcg_pwr_csb_load_gating_prod,
247 .blcg_xbar_load_gating_prod =
248 gm20b_blcg_xbar_load_gating_prod,
249 .blcg_pmu_load_gating_prod =
250 gm20b_blcg_pmu_load_gating_prod,
251 .pg_gr_load_gating_prod =
252 gr_gm20b_pg_gr_load_gating_prod,
253 },
254 .fifo = {
255 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
256 .bind_channel = vgpu_channel_bind,
257 .unbind_channel = vgpu_channel_unbind,
258 .disable_channel = vgpu_channel_disable,
259 .enable_channel = vgpu_channel_enable,
260 .alloc_inst = vgpu_channel_alloc_inst,
261 .free_inst = vgpu_channel_free_inst,
262 .setup_ramfc = vgpu_channel_setup_ramfc,
263 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
264 .setup_userd = gk20a_fifo_setup_userd,
265 .userd_gp_get = gk20a_fifo_userd_gp_get,
266 .userd_gp_put = gk20a_fifo_userd_gp_put,
267 .userd_pb_get = gk20a_fifo_userd_pb_get,
268 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
269 .preempt_channel = vgpu_fifo_preempt_channel,
270 .preempt_tsg = vgpu_fifo_preempt_tsg,
271 .enable_tsg = vgpu_enable_tsg,
272 .disable_tsg = gk20a_disable_tsg,
273 .tsg_verify_channel_status = NULL,
274 .tsg_verify_status_ctx_reload = NULL,
275 .update_runlist = vgpu_fifo_update_runlist,
276 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
277 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
278 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
279 .get_num_fifos = gm20b_fifo_get_num_fifos,
280 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
281 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
282 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
283 .tsg_open = vgpu_tsg_open,
284 .force_reset_ch = vgpu_fifo_force_reset_ch,
285 .engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
286 .device_info_data_parse = gm20b_device_info_data_parse,
287 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
288 .init_engine_info = vgpu_fifo_init_engine_info,
289 .runlist_entry_size = ram_rl_entry_size_v,
290 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
291 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
292 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
293 .dump_pbdma_status = gk20a_dump_pbdma_status,
294 .dump_eng_status = gk20a_dump_eng_status,
295 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
296 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
297 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
298 .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
299 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
300 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
301 .handle_sched_error = gk20a_fifo_handle_sched_error,
302 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
303 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
304 .tsg_bind_channel = vgpu_tsg_bind_channel,
305 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
306#ifdef CONFIG_TEGRA_GK20A_NVHOST
307 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
308 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
309 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
310 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
311 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
312 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
313#endif
314 },
315 .gr_ctx = {
316 .get_netlist_name = gr_gm20b_get_netlist_name,
317 .is_fw_defined = gr_gm20b_is_firmware_defined,
318 },
319 .mm = {
320 .support_sparse = gm20b_mm_support_sparse,
321 .gmmu_map = vgpu_locked_gmmu_map,
322 .gmmu_unmap = vgpu_locked_gmmu_unmap,
323 .vm_bind_channel = vgpu_vm_bind_channel,
324 .fb_flush = vgpu_mm_fb_flush,
325 .l2_invalidate = vgpu_mm_l2_invalidate,
326 .l2_flush = vgpu_mm_l2_flush,
327 .cbc_clean = gk20a_mm_cbc_clean,
328 .set_big_page_size = gm20b_mm_set_big_page_size,
329 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
330 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
331 .gpu_phys_addr = gm20b_gpu_phys_addr,
332 .get_iommu_bit = gk20a_mm_get_iommu_bit,
333 .get_mmu_levels = gk20a_mm_get_mmu_levels,
334 .init_pdb = gk20a_mm_init_pdb,
335 .init_mm_setup_hw = NULL,
336 .is_bar1_supported = gm20b_mm_is_bar1_supported,
337 .init_inst_block = gk20a_init_inst_block,
338 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
339 .get_kind_invalid = gm20b_get_kind_invalid,
340 .get_kind_pitch = gm20b_get_kind_pitch,
341 },
342 .therm = {
343 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
344 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
345 },
346 .pmu = {
347 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
348 .pmu_get_queue_head = pwr_pmu_queue_head_r,
349 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
350 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
351 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
352 .pmu_queue_head = gk20a_pmu_queue_head,
353 .pmu_queue_tail = gk20a_pmu_queue_tail,
354 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
355 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
356 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
357 .pmu_mutex_release = gk20a_pmu_mutex_release,
358 .write_dmatrfbase = gm20b_write_dmatrfbase,
359 .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
360 .pmu_pg_init_param = NULL,
361 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
362 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
363 .pmu_is_lpwr_feature_supported = NULL,
364 .pmu_lpwr_enable_pg = NULL,
365 .pmu_lpwr_disable_pg = NULL,
366 .pmu_pg_param_post_init = NULL,
367 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
368 .reset_engine = gk20a_pmu_engine_reset,
369 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
370 },
371 .clk = {
372 .init_clk_support = gm20b_init_clk_support,
373 .suspend_clk_support = gm20b_suspend_clk_support,
374#ifdef CONFIG_DEBUG_FS
375 .init_debugfs = gm20b_clk_init_debugfs,
376#endif
377 .get_voltage = gm20b_clk_get_voltage,
378 .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
379 .pll_reg_write = gm20b_clk_pll_reg_write,
380 .get_pll_debug_data = gm20b_clk_get_pll_debug_data,
381 },
382 .regops = {
383 .get_global_whitelist_ranges =
384 gm20b_get_global_whitelist_ranges,
385 .get_global_whitelist_ranges_count =
386 gm20b_get_global_whitelist_ranges_count,
387 .get_context_whitelist_ranges =
388 gm20b_get_context_whitelist_ranges,
389 .get_context_whitelist_ranges_count =
390 gm20b_get_context_whitelist_ranges_count,
391 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
392 .get_runcontrol_whitelist_count =
393 gm20b_get_runcontrol_whitelist_count,
394 .get_runcontrol_whitelist_ranges =
395 gm20b_get_runcontrol_whitelist_ranges,
396 .get_runcontrol_whitelist_ranges_count =
397 gm20b_get_runcontrol_whitelist_ranges_count,
398 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
399 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
400 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
401 .get_qctl_whitelist_ranges_count =
402 gm20b_get_qctl_whitelist_ranges_count,
403 .apply_smpc_war = gm20b_apply_smpc_war,
404 },
405 .mc = {
406 .intr_enable = mc_gk20a_intr_enable,
407 .intr_unit_config = mc_gk20a_intr_unit_config,
408 .isr_stall = mc_gk20a_isr_stall,
409 .intr_stall = mc_gk20a_intr_stall,
410 .intr_stall_pause = mc_gk20a_intr_stall_pause,
411 .intr_stall_resume = mc_gk20a_intr_stall_resume,
412 .intr_nonstall = mc_gk20a_intr_nonstall,
413 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
414 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
415 .enable = gk20a_mc_enable,
416 .disable = gk20a_mc_disable,
417 .reset = gk20a_mc_reset,
418 .boot_0 = gk20a_mc_boot_0,
419 .is_intr1_pending = mc_gk20a_is_intr1_pending,
420 },
421 .debug = {
422 .show_dump = NULL,
423 },
424 .dbg_session_ops = {
425 .exec_reg_ops = vgpu_exec_regops,
426 .dbg_set_powergate = vgpu_dbg_set_powergate,
427 .check_and_set_global_reservation =
428 vgpu_check_and_set_global_reservation,
429 .check_and_set_context_reservation =
430 vgpu_check_and_set_context_reservation,
431 .release_profiler_reservation =
432 vgpu_release_profiler_reservation,
433 .perfbuffer_enable = vgpu_perfbuffer_enable,
434 .perfbuffer_disable = vgpu_perfbuffer_disable,
435 },
436 .bus = {
437 .init_hw = gk20a_bus_init_hw,
438 .isr = gk20a_bus_isr,
439 .read_ptimer = vgpu_read_ptimer,
440 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
441 .bar1_bind = gm20b_bus_bar1_bind,
442 },
443#if defined(CONFIG_GK20A_CYCLE_STATS)
444 .css = {
445 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
446 .disable_snapshot = vgpu_css_release_snapshot_buffer,
447 .check_data_available = vgpu_css_flush_snapshots,
448 .detach_snapshot = vgpu_css_detach,
449 .set_handled_snapshots = NULL,
450 .allocate_perfmon_ids = NULL,
451 .release_perfmon_ids = NULL,
452 },
453#endif
454 .falcon = {
455 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
456 },
457 .priv_ring = {
458 .isr = gk20a_priv_ring_isr,
459 },
460 .fuse = {
461 .check_priv_security = vgpu_gm20b_fuse_check_priv_security,
462 },
463 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
464 .get_litter_value = gm20b_get_litter_value,
465};
466
467int vgpu_gm20b_init_hal(struct gk20a *g)
468{
469 struct gpu_ops *gops = &g->ops;
470
471 gops->ltc = vgpu_gm20b_ops.ltc;
472 gops->ce2 = vgpu_gm20b_ops.ce2;
473 gops->gr = vgpu_gm20b_ops.gr;
474 gops->fb = vgpu_gm20b_ops.fb;
475 gops->clock_gating = vgpu_gm20b_ops.clock_gating;
476 gops->fifo = vgpu_gm20b_ops.fifo;
477 gops->gr_ctx = vgpu_gm20b_ops.gr_ctx;
478 gops->mm = vgpu_gm20b_ops.mm;
479 gops->therm = vgpu_gm20b_ops.therm;
480 gops->pmu = vgpu_gm20b_ops.pmu;
481 /*
482 * clk must be assigned member by member
483 * since some clk ops are assigned during probe prior to HAL init
484 */
485 gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support;
486 gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support;
487 gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage;
488 gops->clk.get_gpcclk_clock_counter =
489 vgpu_gm20b_ops.clk.get_gpcclk_clock_counter;
490 gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write;
491 gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data;
492
493 gops->regops = vgpu_gm20b_ops.regops;
494 gops->mc = vgpu_gm20b_ops.mc;
495 gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops;
496 gops->debug = vgpu_gm20b_ops.debug;
497 gops->bus = vgpu_gm20b_ops.bus;
498#if defined(CONFIG_GK20A_CYCLE_STATS)
499 gops->css = vgpu_gm20b_ops.css;
500#endif
501 gops->falcon = vgpu_gm20b_ops.falcon;
502
503 gops->priv_ring = vgpu_gm20b_ops.priv_ring;
504
505 gops->fuse = vgpu_gm20b_ops.fuse;
506
507 /* Lone functions */
508 gops->chip_init_gpu_characteristics =
509 vgpu_gm20b_ops.chip_init_gpu_characteristics;
510 gops->get_litter_value = vgpu_gm20b_ops.get_litter_value;
511
512 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
513 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
514
515 /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
516 if (gops->fuse.check_priv_security(g))
517 return -EINVAL; /* Do not boot gpu */
518
519 /* priv security dependent ops */
520 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
521 /* Add in ops from gm20b acr */
522 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
523 gops->pmu.prepare_ucode = prepare_ucode_blob;
524 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
525 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
526 gops->pmu.is_priv_load = gm20b_is_priv_load;
527 gops->pmu.get_wpr = gm20b_wpr_info;
528 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
529 gops->pmu.pmu_populate_loader_cfg =
530 gm20b_pmu_populate_loader_cfg;
531 gops->pmu.flcn_populate_bl_dmem_desc =
532 gm20b_flcn_populate_bl_dmem_desc;
533 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
534 gops->pmu.falcon_clear_halt_interrupt_status =
535 clear_halt_interrupt_status;
536 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
537
538 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
539 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
540
541 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
542 } else {
543 /* Inherit from gk20a */
544 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
545 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
546 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
547 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
548
549 gops->pmu.load_lsfalcon_ucode = NULL;
550 gops->pmu.init_wpr_region = NULL;
551
552 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
553 }
554
555 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
556 g->pmu_lsf_pmu_wpr_init_done = 0;
557 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
558
559 g->name = "gm20b";
560
561 return 0;
562}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
index 7900f53f..bb523f1e 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
@@ -433,11 +433,6 @@ static int vgpu_init_hal(struct gk20a *g)
433 int err; 433 int err;
434 434
435 switch (ver) { 435 switch (ver) {
436 case GK20A_GPUID_GM20B:
437 case GK20A_GPUID_GM20B_B:
438 gk20a_dbg_info("gm20b detected");
439 err = vgpu_gm20b_init_hal(g);
440 break;
441 case NVGPU_GPUID_GP10B: 436 case NVGPU_GPUID_GP10B:
442 gk20a_dbg_info("gp10b detected"); 437 gk20a_dbg_info("gp10b detected");
443 err = vgpu_gp10b_init_hal(g); 438 err = vgpu_gp10b_init_hal(g);
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
index ac65dba3..8d1464d4 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
@@ -102,7 +102,6 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
102int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, 102int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
103 size_t size_out); 103 size_t size_out);
104 104
105int vgpu_gm20b_init_hal(struct gk20a *g);
106int vgpu_gp10b_init_hal(struct gk20a *g); 105int vgpu_gp10b_init_hal(struct gk20a *g);
107 106
108int vgpu_init_gpu_characteristics(struct gk20a *g); 107int vgpu_init_gpu_characteristics(struct gk20a *g);
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 13:41:25 -0400