gpu: nvgpu: add broadcast address decode support for volta

With Volta we have more number of broadcast registers than previous chips
and we don't decode them right now in gr_gk20a_decode_priv_addr()

Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all
previous chips
Add and use gr_gv11b_decode_priv_addr() for Volta

gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set
the broadcast flags apporiately

Define below new broadcast types
PRI_BROADCAST_FLAGS_PMMGPC
PRI_BROADCAST_FLAGS_PMM_GPCS
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB
PRI_BROADCAST_FLAGS_PMMFBP
PRI_BROADCAST_FLAGS_PMM_FBPS
PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC
PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP

Bug 200398811
Jira NVGPU-556

Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690026
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

14 files changed, 205 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index efb425c2..164668cb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -461,6 +461,11 @@ struct gpu_ops {
                                         struct aiv_list_gk20a *regs,
                                         u32 *count, u32 *offset,
                                         u32 max_cnt, u32 base, u32 mask);
+                int (*decode_priv_addr)(struct gk20a *g, u32 addr,
+                              int *addr_type,
+                              u32 *gpc_num, u32 *tpc_num,
+                              u32 *ppc_num, u32 *be_num,
+                              u32 *broadcast_flags);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 65144cc5..3912a1df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6247,7 +6247,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
                                                   u32 *priv_offset);
 
 /* This function will decode a priv address and return the partition type and numbers. */
-static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
+int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
                               int  *addr_type, /* enum ctxsw_addr_type */
                               u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
                               u32 *broadcast_flags)
@@ -6365,7 +6365,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g,
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
-        err = gr_gk20a_decode_priv_addr(g, addr, &addr_type,
+        err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
                                         &gpc_num, &tpc_num, &ppc_num, &be_num,
                                         &broadcast_flags);
         gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
@@ -7211,7 +7211,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
-        err = gr_gk20a_decode_priv_addr(g, addr, &addr_type,
+        err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
                                         &gpc_num, &tpc_num, &ppc_num, &be_num,
                                         &broadcast_flags);
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index a80116b7..ee76148a 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -821,4 +821,8 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map,
         struct aiv_list_gk20a *regs,
         u32 *count, u32 *offset,
         u32 max_cnt, u32 base, u32 mask);
+int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
+        int *addr_type,
+        u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+        u32 *broadcast_flags);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
index d0b6df47..af390833 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Context Pri Register Addressing
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -245,17 +245,27 @@ enum ctxsw_addr_type {
         CTXSW_ADDR_TYPE_FBPA = 6,
         CTXSW_ADDR_TYPE_EGPC = 7,
         CTXSW_ADDR_TYPE_ETPC = 8,
+        CTXSW_ADDR_TYPE_ROP  = 9,
+        CTXSW_ADDR_TYPE_FBP  = 10,
 };
 
-#define PRI_BROADCAST_FLAGS_NONE  0
-#define PRI_BROADCAST_FLAGS_GPC   BIT(0)
-#define PRI_BROADCAST_FLAGS_TPC   BIT(1)
-#define PRI_BROADCAST_FLAGS_BE    BIT(2)
-#define PRI_BROADCAST_FLAGS_PPC   BIT(3)
-#define PRI_BROADCAST_FLAGS_LTCS  BIT(4)
-#define PRI_BROADCAST_FLAGS_LTSS  BIT(5)
-#define PRI_BROADCAST_FLAGS_FBPA  BIT(6)
-#define PRI_BROADCAST_FLAGS_EGPC  BIT(7)
-#define PRI_BROADCAST_FLAGS_ETPC  BIT(8)
+#define PRI_BROADCAST_FLAGS_NONE                0
+#define PRI_BROADCAST_FLAGS_GPC                 BIT(0)
+#define PRI_BROADCAST_FLAGS_TPC                 BIT(1)
+#define PRI_BROADCAST_FLAGS_BE                  BIT(2)
+#define PRI_BROADCAST_FLAGS_PPC                 BIT(3)
+#define PRI_BROADCAST_FLAGS_LTCS                BIT(4)
+#define PRI_BROADCAST_FLAGS_LTSS                BIT(5)
+#define PRI_BROADCAST_FLAGS_FBPA                BIT(6)
+#define PRI_BROADCAST_FLAGS_EGPC                BIT(7)
+#define PRI_BROADCAST_FLAGS_ETPC                BIT(8)
+#define PRI_BROADCAST_FLAGS_PMMGPC              BIT(9)
+#define PRI_BROADCAST_FLAGS_PMM_GPCS            BIT(10)
+#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA   BIT(11)
+#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB   BIT(12)
+#define PRI_BROADCAST_FLAGS_PMMFBP              BIT(13)
+#define PRI_BROADCAST_FLAGS_PMM_FBPS            BIT(14)
+#define PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC       BIT(15)
+#define PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP       BIT(16)
 
 #endif /* GR_PRI_GK20A_H */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 82e8826e..65e75374 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -320,6 +320,7 @@ static const struct gpu_ops gm20b_ops = {
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gk20a_decode_priv_addr,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index cad8ed97..4daa510c 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -383,6 +383,7 @@ static const struct gpu_ops gp106_ops = {
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gk20a_decode_priv_addr,
         },
         .fb = {
                 .reset = gp106_fb_reset,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 97c273cb..2f122e20 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -351,6 +351,7 @@ static const struct gpu_ops gp10b_ops = {
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gk20a_decode_priv_addr,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index cf751135..5cafcaae 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -430,6 +430,7 @@ static const struct gpu_ops gv100_ops = {
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
                 .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gv11b_decode_priv_addr,
         },
         .fb = {
                 .reset = gv100_fb_reset,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c43c6e83..61649d06 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -46,6 +46,7 @@
 #include "gv11b/mm_gv11b.h"
 #include "gv11b/subctx_gv11b.h"
 #include "gv11b/gv11b.h"
+#include "gv11b/gr_pri_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
@@ -4400,3 +4401,113 @@ int gr_gv11b_handle_ssync_hww(struct gk20a *g)
                          gr_ssync_hww_esr_reset_active_f());
         return -EFAULT;
 }
+
+/*
+ * This function will decode a priv address and return the partition
+ * type and numbers
+ */
+int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
+        int  *addr_type, /* enum ctxsw_addr_type */
+        u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+        u32 *broadcast_flags)
+{
+        u32 gpc_addr;
+
+        gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
+
+        /* setup defaults */
+        *addr_type = CTXSW_ADDR_TYPE_SYS;
+        *broadcast_flags = PRI_BROADCAST_FLAGS_NONE;
+        *gpc_num = 0;
+        *tpc_num = 0;
+        *ppc_num = 0;
+        *be_num  = 0;
+
+        if (pri_is_gpc_addr(g, addr)) {
+                *addr_type = CTXSW_ADDR_TYPE_GPC;
+                gpc_addr = pri_gpccs_addr_mask(addr);
+                if (pri_is_gpc_addr_shared(g, addr)) {
+                        *addr_type = CTXSW_ADDR_TYPE_GPC;
+                        *broadcast_flags |= PRI_BROADCAST_FLAGS_GPC;
+                } else
+                        *gpc_num = pri_get_gpc_num(g, addr);
+
+                if (pri_is_ppc_addr(g, gpc_addr)) {
+                        *addr_type = CTXSW_ADDR_TYPE_PPC;
+                        if (pri_is_ppc_addr_shared(g, gpc_addr)) {
+                                *broadcast_flags |= PRI_BROADCAST_FLAGS_PPC;
+                                return 0;
+                        }
+                }
+                if (g->ops.gr.is_tpc_addr(g, gpc_addr)) {
+                        *addr_type = CTXSW_ADDR_TYPE_TPC;
+                        if (pri_is_tpc_addr_shared(g, gpc_addr)) {
+                                *broadcast_flags |= PRI_BROADCAST_FLAGS_TPC;
+                                return 0;
+                        }
+                        *tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr);
+                }
+                return 0;
+        } else if (pri_is_be_addr(g, addr)) {
+                *addr_type = CTXSW_ADDR_TYPE_BE;
+                if (pri_is_be_addr_shared(g, addr)) {
+                        *broadcast_flags |= PRI_BROADCAST_FLAGS_BE;
+                        return 0;
+                }
+                *be_num = pri_get_be_num(g, addr);
+                return 0;
+        } else if (pri_is_ltc_addr(addr)) {
+                *addr_type = CTXSW_ADDR_TYPE_LTCS;
+                if (g->ops.gr.is_ltcs_ltss_addr(g, addr))
+                        *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS;
+                else if (g->ops.gr.is_ltcn_ltss_addr(g, addr))
+                        *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS;
+                return 0;
+        } else if (pri_is_fbpa_addr(g, addr)) {
+                *addr_type = CTXSW_ADDR_TYPE_FBPA;
+                if (pri_is_fbpa_addr_shared(g, addr)) {
+                        *broadcast_flags |= PRI_BROADCAST_FLAGS_FBPA;
+                        return 0;
+                }
+                return 0;
+        } else if (g->ops.gr.is_egpc_addr && g->ops.gr.is_egpc_addr(g, addr)) {
+                return g->ops.gr.decode_egpc_addr(g,
+                                addr, addr_type, gpc_num,
+                                tpc_num, broadcast_flags);
+        } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) ==
+                        NV_PERF_PMMGPC_GPCGS_GPCTPCA) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA |
+                                     PRI_BROADCAST_FLAGS_PMMGPC);
+                *addr_type = CTXSW_ADDR_TYPE_GPC;
+                return 0;
+        } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) ==
+                        NV_PERF_PMMGPC_GPCGS_GPCTPCB) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB |
+                                     PRI_BROADCAST_FLAGS_PMMGPC);
+                *addr_type = CTXSW_ADDR_TYPE_GPC;
+                return 0;
+        } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPGS_LTC) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC |
+                                     PRI_BROADCAST_FLAGS_PMMFBP);
+                *addr_type = CTXSW_ADDR_TYPE_LTCS;
+                return 0;
+        } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPGS_ROP) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP |
+                                     PRI_BROADCAST_FLAGS_PMMFBP);
+                *addr_type = CTXSW_ADDR_TYPE_ROP;
+                return 0;
+        } else if (PRI_PMMS_BASE_ADDR_MASK(addr) == NV_PERF_PMMGPC_GPCS) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCS |
+                                     PRI_BROADCAST_FLAGS_PMMGPC);
+                *addr_type = CTXSW_ADDR_TYPE_GPC;
+                return 0;
+        } else if (PRI_PMMS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPS) {
+                *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPS |
+                                     PRI_BROADCAST_FLAGS_PMMFBP);
+                *addr_type = CTXSW_ADDR_TYPE_FBP;
+                return 0;
+        }
+
+        *addr_type = CTXSW_ADDR_TYPE_SYS;
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 018938f6..7d286535 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -234,4 +234,8 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
 int gr_gv11b_handle_ssync_hww(struct gk20a *g);
 u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm);
 
+int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
+        int *addr_type,
+        u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+        u32 *broadcast_flags);
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
new file mode 100644
index 00000000..c71f4c9c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
@@ -0,0 +1,50 @@
+/*
+ * GV11B/GV100 Graphics Context Pri Register Addressing
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef GR_PRI_GV11B_H
+#define GR_PRI_GV11B_H
+
+/*
+ * These convenience macros are generally for use in the management/modificaiton
+ * of the context state store for gr/compute contexts.
+ */
+
+/* Broadcast PMM defines */
+#define NV_PERF_PMMFBP_FBPGS_LTC             0x00250800
+#define NV_PERF_PMMFBP_FBPGS_ROP             0x00250A00
+#define NV_PERF_PMMGPC_GPCGS_GPCTPCA         0x00250000
+#define NV_PERF_PMMGPC_GPCGS_GPCTPCB         0x00250200
+#define NV_PERF_PMMGPC_GPCS                  0x00278000
+#define NV_PERF_PMMFBP_FBPS                  0x0027C000
+
+#define PRI_PMMGS_ADDR_WIDTH                 9
+#define PRI_PMMS_ADDR_WIDTH                  14
+
+/* Get the offset to be added to the chiplet base addr to get the unicast address */
+#define PRI_PMMGS_OFFSET_MASK(addr)    ((addr) & ((1 << PRI_PMMGS_ADDR_WIDTH) - 1))
+#define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMGS_ADDR_WIDTH) - 1)))
+
+#define PRI_PMMS_ADDR_MASK(addr)      ((addr) & ((1 << PRI_PMMS_ADDR_WIDTH) - 1))
+#define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMS_ADDR_WIDTH) - 1)))
+
+#endif /* GR_PRI_GV11B_H */
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 9fccce0b..c33844dc 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -403,6 +403,7 @@ static const struct gpu_ops gv11b_ops = {
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gv11b_decode_priv_addr,
         },
         .fb = {
                 .reset = gv11b_fb_reset,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 4ee50f25..34d0fc16 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -225,6 +225,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                         gr_gp10b_get_max_gfxp_wfi_timeout_count,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gk20a_decode_priv_addr,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index ae30246f..d63b91fc 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -261,6 +261,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                         gr_gv11b_get_max_gfxp_wfi_timeout_count,
                 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
                 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
+                .decode_priv_addr = gr_gv11b_decode_priv_addr,
         },
         .fb = {
                 .reset = gv11b_fb_reset,