gpu: nvgpu: gp10b: Qualify unsigned HW constants

Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.

Change-Id: I33d46bb103d083316266eb1d325ca9f1525bf047
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>

24 files changed, 2754 insertions, 2750 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
index 06a3261d..b06ea66d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
@@ -58,166 +58,166 @@
 
 static inline u32 bus_bar0_window_r(void)
 {
-        return 0x00001700;
+        return 0x00001700U;
 }
 static inline u32 bus_bar0_window_base_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 bus_bar0_window_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
 {
-        return 0x3000000;
+        return 0x3000000U;
 }
 static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 bus_bar1_block_r(void)
 {
-        return 0x00001704;
+        return 0x00001704U;
 }
 static inline u32 bus_bar1_block_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 bus_bar1_block_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 bus_bar1_block_mode_virtual_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 bus_bar2_block_r(void)
 {
-        return 0x00001714;
+        return 0x00001714U;
 }
 static inline u32 bus_bar2_block_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 bus_bar2_block_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 bus_bar2_block_mode_virtual_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 bus_bar1_block_ptr_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 bus_bar2_block_ptr_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 bus_bind_status_r(void)
 {
-        return 0x00001710;
+        return 0x00001710U;
 }
 static inline u32 bus_bind_status_bar1_pending_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 bus_bind_status_bar1_pending_empty_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bind_status_bar1_pending_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 bus_bind_status_bar2_pending_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 bus_bind_status_bar2_pending_empty_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bind_status_bar2_pending_busy_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
 {
-        return (r >> 3) & 0x1;
+        return (r >> 3U) & 0x1U;
 }
 static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 bus_intr_0_r(void)
 {
-        return 0x00001100;
+        return 0x00001100U;
 }
 static inline u32 bus_intr_0_pri_squash_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 bus_intr_0_pri_fecserr_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 bus_intr_0_pri_timeout_m(void)
 {
-        return 0x1 << 3;
+        return 0x1U << 3U;
 }
 static inline u32 bus_intr_en_0_r(void)
 {
-        return 0x00001140;
+        return 0x00001140U;
 }
 static inline u32 bus_intr_en_0_pri_squash_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 bus_intr_en_0_pri_fecserr_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 bus_intr_en_0_pri_timeout_m(void)
 {
-        return 0x1 << 3;
+        return 0x1U << 3U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
index e700f81b..00879c11 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
@@ -58,106 +58,106 @@
 
 static inline u32 ccsr_channel_inst_r(u32 i)
 {
-        return 0x00800000 + i*8;
+        return 0x00800000U + i*8U;
 }
 static inline u32 ccsr_channel_inst__size_1_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 ccsr_channel_inst_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 ccsr_channel_inst_bind_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ccsr_channel_inst_bind_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 ccsr_channel_r(u32 i)
 {
-        return 0x00800004 + i*8;
+        return 0x00800004U + i*8U;
 }
 static inline u32 ccsr_channel__size_1_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 ccsr_channel_enable_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ccsr_channel_enable_set_f(u32 v)
 {
-        return (v & 0x1) << 10;
+        return (v & 0x1U) << 10U;
 }
 static inline u32 ccsr_channel_enable_set_true_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 ccsr_channel_enable_clr_true_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 ccsr_channel_status_v(u32 r)
 {
-        return (r >> 24) & 0xf;
+        return (r >> 24U) & 0xfU;
 }
 static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
 {
-        return 0x0000000a;
+        return 0x0000000aU;
 }
 static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
 {
-        return 0x0000000b;
+        return 0x0000000bU;
 }
 static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
 {
-        return 0x0000000d;
+        return 0x0000000dU;
 }
 static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
 {
-        return 0x0000000e;
+        return 0x0000000eU;
 }
 static inline u32 ccsr_channel_next_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 ccsr_channel_next_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 ccsr_channel_busy_v(u32 r)
 {
-        return (r >> 28) & 0x1;
+        return (r >> 28U) & 0x1U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
index bb3e8b12..c2937710 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
@@ -58,30 +58,30 @@
 
 static inline u32 ce_intr_status_r(u32 i)
 {
-        return 0x00104410 + i*128;
+        return 0x00104410U + i*128U;
 }
 static inline u32 ce_intr_status_blockpipe_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ce_intr_status_blockpipe_reset_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ce_intr_status_launcherr_pending_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 ce_intr_status_launcherr_reset_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
index 0f1fe0ed..b214bdb3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
@@ -58,430 +58,430 @@
 
 static inline u32 ctxsw_prog_fecs_header_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 ctxsw_prog_main_image_patch_count_o(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 ctxsw_prog_main_image_context_id_o(void)
 {
-        return 0x000000f0;
+        return 0x000000f0U;
 }
 static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
 {
-        return 0x00000014;
+        return 0x00000014U;
 }
 static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
 {
-        return 0x00000018;
+        return 0x00000018U;
 }
 static inline u32 ctxsw_prog_main_image_zcull_o(void)
 {
-        return 0x0000001c;
+        return 0x0000001cU;
 }
 static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 ctxsw_prog_main_image_pm_o(void)
 {
-        return 0x00000028;
+        return 0x00000028U;
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
 {
-        return 0x7 << 0;
+        return 0x7U << 0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
-        return 0x7 << 3;
+        return 0x7U << 3U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
 {
-        return 0x0000002c;
+        return 0x0000002cU;
 }
 static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
 {
-        return 0x000000f4;
+        return 0x000000f4U;
 }
 static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
 {
-        return 0x000000d0;
+        return 0x000000d0U;
 }
 static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
 {
-        return 0x000000d4;
+        return 0x000000d4U;
 }
 static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
 {
-        return 0x000000d8;
+        return 0x000000d8U;
 }
 static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
 {
-        return 0x000000dc;
+        return 0x000000dcU;
 }
 static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
 {
-        return 0x000000f8;
+        return 0x000000f8U;
 }
 static inline u32 ctxsw_prog_main_image_magic_value_o(void)
 {
-        return 0x000000fc;
+        return 0x000000fcU;
 }
 static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
 {
-        return 0x600dc0de;
+        return 0x600dc0deU;
 }
 static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
 {
-        return 0x000000f4;
+        return 0x000000f4U;
 }
 static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
 {
-        return (r >> 16) & 0xffff;
+        return (r >> 16U) & 0xffffU;
 }
 static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
 {
-        return 0x000000f8;
+        return 0x000000f8U;
 }
 static inline u32 ctxsw_prog_local_magic_value_o(void)
 {
-        return 0x000000fc;
+        return 0x000000fcU;
 }
 static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
 {
-        return 0xad0becab;
+        return 0xad0becabU;
 }
 static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
 {
-        return 0x000000ec;
+        return 0x000000ecU;
 }
 static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
 {
-        return (r >> 16) & 0xff;
+        return (r >> 16U) & 0xffU;
 }
 static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
 {
-        return 0x000000a0;
+        return 0x000000a0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
 {
-        return (v & 0x3) << 0;
+        return (v & 0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
 {
-        return 0x3 << 0;
+        return 0x3U << 0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
 {
-        return (r >> 0) & 0x3;
+        return (r >> 0U) & 0x3U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
 {
-        return 0x000000a4;
+        return 0x000000a4U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
 {
-        return 0x000000a8;
+        return 0x000000a8U;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_o(void)
 {
-        return 0x0000003c;
+        return 0x0000003cU;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
 {
-        return 0x1 << 3;
+        return 0x1U << 3U;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ctxsw_prog_main_image_pmu_options_o(void)
 {
-        return 0x00000070;
+        return 0x00000070U;
 }
 static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
 {
-        return 0x00000080;
+        return 0x00000080U;
 }
 static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
 {
-        return (v & 0x3) << 0;
+        return (v & 0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
 {
-        return 0x00000068;
+        return 0x00000068U;
 }
 static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
 {
-        return 0x00000084;
+        return 0x00000084U;
 }
 static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
 {
-        return (v & 0x3) << 0;
+        return (v & 0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
 {
-        return 0x000000ac;
+        return 0x000000acU;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
 {
-        return 0x000000b0;
+        return 0x000000b0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
 {
-        return 0xfffffff << 0;
+        return 0xfffffffU << 0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
 {
-        return 0x3 << 28;
+        return 0x3U << 28U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
 {
-        return 0x000000b4;
+        return 0x000000b4U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
 {
-        return 0x00000080;
+        return 0x00000080U;
 }
 static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
 {
-        return 0x600dbeef;
+        return 0x600dbeefU;
 }
 static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
 {
-        return 0x00000018;
+        return 0x00000018U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
 {
-        return 0x0000001c;
+        return 0x0000001cU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
 {
-        return (r >> 0) & 0xffffff;
+        return (r >> 0U) & 0xffffffU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
 {
-        return (v & 0xff) << 24;
+        return (v & 0xffU) << 24U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
 {
-        return 0xff << 24;
+        return 0xffU << 24U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
 {
-        return (r >> 24) & 0xff;
+        return (r >> 24U) & 0xffU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
 {
-        return 0x0000000a;
+        return 0x0000000aU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
 {
-        return 0xa000000;
+        return 0xa000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
 {
-        return 0x0000000b;
+        return 0x0000000bU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
 {
-        return 0xb000000;
+        return 0xb000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
 {
-        return 0xc000000;
+        return 0xc000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
 {
-        return 0x0000000d;
+        return 0x0000000dU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
 {
-        return 0xd000000;
+        return 0xd000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
 {
-        return 0x3000000;
+        return 0x3000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
 {
-        return 0x4000000;
+        return 0x4000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
 {
-        return 0x00000005;
+        return 0x00000005U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
 {
-        return 0x5000000;
+        return 0x5000000U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
 {
-        return 0x000000ff;
+        return 0x000000ffU;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
 {
-        return 0xff000000;
+        return 0xff000000U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
index 4cc54b45..81a6f79c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
@@ -58,430 +58,430 @@
 
 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
-        return 0x00100800;
+        return 0x00100800U;
 }
 static inline u32 fb_mmu_ctrl_r(void)
 {
-        return 0x00100c80;
+        return 0x00100c80U;
 }
 static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
 {
-        return (r >> 15) & 0x1;
+        return (r >> 15U) & 0x1U;
 }
 static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
 {
-        return (r >> 16) & 0xff;
+        return (r >> 16U) & 0xffU;
 }
 static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
 {
-        return (r >> 11) & 0x1;
+        return (r >> 11U) & 0x1U;
 }
 static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_priv_mmu_phy_secure_r(void)
 {
-        return 0x00100ce4;
+        return 0x00100ce4U;
 }
 static inline u32 fb_mmu_invalidate_pdb_r(void)
 {
-        return 0x00100cb8;
+        return 0x00100cb8U;
 }
 static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 fb_mmu_invalidate_r(void)
 {
-        return 0x00100cbc;
+        return 0x00100cbcU;
 }
 static inline u32 fb_mmu_invalidate_all_va_true_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 fb_mmu_invalidate_replay_s(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 fb_mmu_invalidate_replay_f(u32 v)
 {
-        return (v & 0x7) << 3;
+        return (v & 0x7U) << 3U;
 }
 static inline u32 fb_mmu_invalidate_replay_m(void)
 {
-        return 0x7 << 3;
+        return 0x7U << 3U;
 }
 static inline u32 fb_mmu_invalidate_replay_v(u32 r)
 {
-        return (r >> 3) & 0x7;
+        return (r >> 3U) & 0x7U;
 }
 static inline u32 fb_mmu_invalidate_replay_none_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_invalidate_replay_start_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
 {
-        return 0x18;
+        return 0x18U;
 }
 static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
 {
-        return (v & 0x1) << 6;
+        return (v & 0x1U) << 6U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_m(void)
 {
-        return 0x1 << 6;
+        return 0x1U << 6U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
 {
-        return (r >> 6) & 0x1;
+        return (r >> 6U) & 0x1U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 fb_mmu_invalidate_ack_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 fb_mmu_invalidate_ack_f(u32 v)
 {
-        return (v & 0x3) << 7;
+        return (v & 0x3U) << 7U;
 }
 static inline u32 fb_mmu_invalidate_ack_m(void)
 {
-        return 0x3 << 7;
+        return 0x3U << 7U;
 }
 static inline u32 fb_mmu_invalidate_ack_v(u32 r)
 {
-        return (r >> 7) & 0x3;
+        return (r >> 7U) & 0x3U;
 }
 static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
 {
-        return (v & 0x3f) << 9;
+        return (v & 0x3fU) << 9U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
 {
-        return 0x3f << 9;
+        return 0x3fU << 9U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
 {
-        return (r >> 9) & 0x3f;
+        return (r >> 9U) & 0x3fU;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
 {
-        return 5;
+        return 5U;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
 {
-        return (v & 0x1f) << 15;
+        return (v & 0x1fU) << 15U;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
 {
-        return 0x1f << 15;
+        return 0x1fU << 15U;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
 {
-        return (r >> 15) & 0x1f;
+        return (r >> 15U) & 0x1fU;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
 {
-        return (v & 0x1) << 20;
+        return (v & 0x1U) << 20U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
 {
-        return 0x1 << 20;
+        return 0x1U << 20U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
 {
-        return (r >> 20) & 0x1;
+        return (r >> 20U) & 0x1U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
 {
-        return (v & 0x7) << 24;
+        return (v & 0x7U) << 24U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
 {
-        return 0x7 << 24;
+        return 0x7U << 24U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
 {
-        return (r >> 24) & 0x7;
+        return (r >> 24U) & 0x7U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
 {
-        return 0x3000000;
+        return 0x3000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
 {
-        return 0x4000000;
+        return 0x4000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
 {
-        return 0x5000000;
+        return 0x5000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
 {
-        return 0x6000000;
+        return 0x6000000U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
 {
-        return 0x7000000;
+        return 0x7000000U;
 }
 static inline u32 fb_mmu_invalidate_trigger_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 fb_mmu_invalidate_trigger_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 fb_mmu_invalidate_trigger_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 fb_mmu_debug_wr_r(void)
 {
-        return 0x00100cc8;
+        return 0x00100cc8U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
 {
-        return (v & 0x3) << 0;
+        return (v & 0x3U) << 0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_m(void)
 {
-        return 0x3 << 0;
+        return 0x3U << 0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
 {
-        return (r >> 0) & 0x3;
+        return (r >> 0U) & 0x3U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 fb_mmu_debug_wr_vol_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_debug_wr_vol_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fb_mmu_debug_wr_vol_true_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 fb_mmu_debug_rd_r(void)
 {
-        return 0x00100ccc;
+        return 0x00100cccU;
 }
 static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 fb_mmu_debug_rd_vol_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 fb_mmu_debug_ctrl_r(void)
 {
-        return 0x00100cc4;
+        return 0x00100cc4U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
 {
-        return (r >> 16) & 0x1;
+        return (r >> 16U) & 0x1U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_m(void)
 {
-        return 0x1 << 16;
+        return 0x1U << 16U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fb_mmu_vpr_info_r(void)
 {
-        return 0x00100cd0;
+        return 0x00100cd0U;
 }
 static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fb_niso_flush_sysmem_addr_r(void)
 {
-        return 0x00100c10;
+        return 0x00100c10U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
index c2335235..71701626 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
@@ -58,642 +58,642 @@
 
 static inline u32 fifo_bar1_base_r(void)
 {
-        return 0x00002254;
+        return 0x00002254U;
 }
 static inline u32 fifo_bar1_base_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 fifo_bar1_base_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fifo_bar1_base_valid_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 fifo_runlist_base_r(void)
 {
-        return 0x00002270;
+        return 0x00002270U;
 }
 static inline u32 fifo_runlist_base_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 fifo_runlist_base_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 fifo_runlist_r(void)
 {
-        return 0x00002274;
+        return 0x00002274U;
 }
 static inline u32 fifo_runlist_engine_f(u32 v)
 {
-        return (v & 0xf) << 20;
+        return (v & 0xfU) << 20U;
 }
 static inline u32 fifo_eng_runlist_base_r(u32 i)
 {
-        return 0x00002280 + i*8;
+        return 0x00002280U + i*8U;
 }
 static inline u32 fifo_eng_runlist_base__size_1_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_eng_runlist_r(u32 i)
 {
-        return 0x00002284 + i*8;
+        return 0x00002284U + i*8U;
 }
 static inline u32 fifo_eng_runlist__size_1_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_eng_runlist_length_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 fifo_eng_runlist_length_max_v(void)
 {
-        return 0x0000ffff;
+        return 0x0000ffffU;
 }
 static inline u32 fifo_eng_runlist_pending_true_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 fifo_pb_timeslice_r(u32 i)
 {
-        return 0x00002350 + i*4;
+        return 0x00002350U + i*4U;
 }
 static inline u32 fifo_pb_timeslice_timeout_16_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 fifo_pb_timeslice_timescale_0_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fifo_pb_timeslice_enable_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 fifo_pbdma_map_r(u32 i)
 {
-        return 0x00002390 + i*4;
+        return 0x00002390U + i*4U;
 }
 static inline u32 fifo_intr_0_r(void)
 {
-        return 0x00002100;
+        return 0x00002100U;
 }
 static inline u32 fifo_intr_0_bind_error_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 fifo_intr_0_bind_error_reset_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 fifo_intr_0_sched_error_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 fifo_intr_0_sched_error_reset_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 fifo_intr_0_chsw_error_pending_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 fifo_intr_0_chsw_error_reset_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 fifo_intr_0_lb_error_pending_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 fifo_intr_0_lb_error_reset_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
 {
-        return 0x8000000;
+        return 0x8000000U;
 }
 static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
 {
-        return 0x8000000;
+        return 0x8000000U;
 }
 static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 fifo_intr_0_runlist_event_pending_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 fifo_intr_0_channel_intr_pending_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 fifo_intr_en_0_r(void)
 {
-        return 0x00002140;
+        return 0x00002140U;
 }
 static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
 {
-        return (v & 0x1) << 8;
+        return (v & 0x1U) << 8U;
 }
 static inline u32 fifo_intr_en_0_sched_error_m(void)
 {
-        return 0x1 << 8;
+        return 0x1U << 8U;
 }
 static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
 {
-        return (v & 0x1) << 28;
+        return (v & 0x1U) << 28U;
 }
 static inline u32 fifo_intr_en_0_mmu_fault_m(void)
 {
-        return 0x1 << 28;
+        return 0x1U << 28U;
 }
 static inline u32 fifo_intr_en_1_r(void)
 {
-        return 0x00002528;
+        return 0x00002528U;
 }
 static inline u32 fifo_intr_bind_error_r(void)
 {
-        return 0x0000252c;
+        return 0x0000252cU;
 }
 static inline u32 fifo_intr_sched_error_r(void)
 {
-        return 0x0000254c;
+        return 0x0000254cU;
 }
 static inline u32 fifo_intr_sched_error_code_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
 {
-        return 0x0000000a;
+        return 0x0000000aU;
 }
 static inline u32 fifo_intr_chsw_error_r(void)
 {
-        return 0x0000256c;
+        return 0x0000256cU;
 }
 static inline u32 fifo_intr_mmu_fault_id_r(void)
 {
-        return 0x0000259c;
+        return 0x0000259cU;
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
 {
-        return 0x00002800 + i*16;
+        return 0x00002800U + i*16U;
 }
 static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
 {
-        return (r >> 0) & 0xfffffff;
+        return (r >> 0U) & 0xfffffffU;
 }
 static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
 {
-        return 0x00002804 + i*16;
+        return 0x00002804U + i*16U;
 }
 static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
 {
-        return 0x00002808 + i*16;
+        return 0x00002808U + i*16U;
 }
 static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
 {
-        return 0x0000280c + i*16;
+        return 0x0000280cU + i*16U;
 }
 static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r)
 {
-        return (r >> 16) & 0x7;
+        return (r >> 16U) & 0x7U;
 }
 static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
 {
-        return (r >> 20) & 0x1;
+        return (r >> 20U) & 0x1U;
 }
 static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
 {
-        return (r >> 8) & 0x7f;
+        return (r >> 8U) & 0x7fU;
 }
 static inline u32 fifo_intr_pbdma_id_r(void)
 {
-        return 0x000025a0;
+        return 0x000025a0U;
 }
 static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
 {
-        return (v & 0x1) << (0 + i*1);
+        return (v & 0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
 {
-        return (r >> (0 + i*1)) & 0x1;
+        return (r >> (0U + i*1U)) & 0x1U;
 }
 static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_intr_runlist_r(void)
 {
-        return 0x00002a00;
+        return 0x00002a00U;
 }
 static inline u32 fifo_fb_timeout_r(void)
 {
-        return 0x00002a04;
+        return 0x00002a04U;
 }
 static inline u32 fifo_fb_timeout_period_m(void)
 {
-        return 0x3fffffff << 0;
+        return 0x3fffffffU << 0U;
 }
 static inline u32 fifo_fb_timeout_period_max_f(void)
 {
-        return 0x3fffffff;
+        return 0x3fffffffU;
 }
 static inline u32 fifo_error_sched_disable_r(void)
 {
-        return 0x0000262c;
+        return 0x0000262cU;
 }
 static inline u32 fifo_sched_disable_r(void)
 {
-        return 0x00002630;
+        return 0x00002630U;
 }
 static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
 {
-        return (v & 0x1) << (0 + i*1);
+        return (v & 0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_sched_disable_runlist_m(u32 i)
 {
-        return 0x1 << (0 + i*1);
+        return 0x1U << (0U + i*1U);
 }
 static inline u32 fifo_sched_disable_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_preempt_r(void)
 {
-        return 0x00002634;
+        return 0x00002634U;
 }
 static inline u32 fifo_preempt_pending_true_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 fifo_preempt_type_channel_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fifo_preempt_type_tsg_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 fifo_preempt_chid_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 fifo_preempt_id_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 fifo_trigger_mmu_fault_r(u32 i)
 {
-        return 0x00002a30 + i*4;
+        return 0x00002a30U + i*4U;
 }
 static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
 {
-        return (v & 0x1f) << 0;
+        return (v & 0x1fU) << 0U;
 }
 static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
 {
-        return (v & 0x1) << 8;
+        return (v & 0x1U) << 8U;
 }
 static inline u32 fifo_engine_status_r(u32 i)
 {
-        return 0x00002640 + i*8;
+        return 0x00002640U + i*8U;
 }
 static inline u32 fifo_engine_status__size_1_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 fifo_engine_status_id_v(u32 r)
 {
-        return (r >> 0) & 0xfff;
+        return (r >> 0U) & 0xfffU;
 }
 static inline u32 fifo_engine_status_id_type_v(u32 r)
 {
-        return (r >> 12) & 0x1;
+        return (r >> 12U) & 0x1U;
 }
 static inline u32 fifo_engine_status_id_type_chid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_engine_status_id_type_tsgid_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_engine_status_ctx_status_v(u32 r)
 {
-        return (r >> 13) & 0x7;
+        return (r >> 13U) & 0x7U;
 }
 static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_engine_status_ctx_status_valid_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
 {
-        return 0x00000005;
+        return 0x00000005U;
 }
 static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
 {
-        return 0x00000006;
+        return 0x00000006U;
 }
 static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
 {
-        return 0x00000007;
+        return 0x00000007U;
 }
 static inline u32 fifo_engine_status_next_id_v(u32 r)
 {
-        return (r >> 16) & 0xfff;
+        return (r >> 16U) & 0xfffU;
 }
 static inline u32 fifo_engine_status_next_id_type_v(u32 r)
 {
-        return (r >> 28) & 0x1;
+        return (r >> 28U) & 0x1U;
 }
 static inline u32 fifo_engine_status_next_id_type_chid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_engine_status_faulted_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 fifo_engine_status_faulted_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_engine_status_engine_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 fifo_engine_status_engine_idle_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_engine_status_engine_busy_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_engine_status_ctxsw_v(u32 r)
 {
-        return (r >> 15) & 0x1;
+        return (r >> 15U) & 0x1U;
 }
 static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
 {
-        return 0x8000;
+        return 0x8000U;
 }
 static inline u32 fifo_pbdma_status_r(u32 i)
 {
-        return 0x00003080 + i*4;
+        return 0x00003080U + i*4U;
 }
 static inline u32 fifo_pbdma_status__size_1_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_pbdma_status_id_v(u32 r)
 {
-        return (r >> 0) & 0xfff;
+        return (r >> 0U) & 0xfffU;
 }
 static inline u32 fifo_pbdma_status_id_type_v(u32 r)
 {
-        return (r >> 12) & 0x1;
+        return (r >> 12U) & 0x1U;
 }
 static inline u32 fifo_pbdma_status_id_type_chid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
 {
-        return (r >> 13) & 0x7;
+        return (r >> 13U) & 0x7U;
 }
 static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
 {
-        return 0x00000005;
+        return 0x00000005U;
 }
 static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
 {
-        return 0x00000006;
+        return 0x00000006U;
 }
 static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
 {
-        return 0x00000007;
+        return 0x00000007U;
 }
 static inline u32 fifo_pbdma_status_next_id_v(u32 r)
 {
-        return (r >> 16) & 0xfff;
+        return (r >> 16U) & 0xfffU;
 }
 static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
 {
-        return (r >> 28) & 0x1;
+        return (r >> 28U) & 0x1U;
 }
 static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_pbdma_status_chsw_v(u32 r)
 {
-        return (r >> 15) & 0x1;
+        return (r >> 15U) & 0x1U;
 }
 static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_r(void)
 {
-        return 0x00002a70;
+        return 0x00002a70U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
 {
-        return (v & 0xfffff) << 12;
+        return (v & 0xfffffU) << 12U;
 }
 static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_hi_r(void)
 {
-        return 0x00002a74;
+        return 0x00002a74U;
 }
 static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_size_r(void)
 {
-        return 0x00002a78;
+        return 0x00002a78U;
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
 {
-        return (v & 0x1ff) << 0;
+        return (v & 0x1ffU) << 0U;
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
 {
-        return 0x000000c0;
+        return 0x000000c0U;
 }
 static inline u32 fifo_replay_fault_buffer_get_r(void)
 {
-        return 0x00002a7c;
+        return 0x00002a7cU;
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
 {
-        return (v & 0x1ff) << 0;
+        return (v & 0x1ffU) << 0U;
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_put_r(void)
 {
-        return 0x00002a80;
+        return 0x00002a80U;
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
 {
-        return (v & 0x1ff) << 0;
+        return (v & 0x1ffU) << 0U;
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_info_r(void)
 {
-        return 0x00002a84;
+        return 0x00002a84U;
 }
 static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
 {
-        return (v & 0x1) << 28;
+        return (v & 0x1U) << 28U;
 }
 static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
index 69e8437f..ae6eabf1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
@@ -58,130 +58,130 @@
 
 static inline u32 flush_l2_system_invalidate_r(void)
 {
-        return 0x00070004;
+        return 0x00070004U;
 }
 static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_l2_flush_dirty_r(void)
 {
-        return 0x00070010;
+        return 0x00070010U;
 }
 static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_l2_clean_comptags_r(void)
 {
-        return 0x0007000c;
+        return 0x0007000cU;
 }
 static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_fb_flush_r(void)
 {
-        return 0x00070000;
+        return 0x00070000U;
 }
 static inline u32 flush_fb_flush_pending_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 flush_fb_flush_pending_busy_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 flush_fb_flush_pending_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 flush_fb_flush_outstanding_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 flush_fb_flush_outstanding_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
index dc5128c4..29107fb8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
@@ -58,94 +58,94 @@
 
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
-        return 0x00021c38 + i*4;
+        return 0x00021c38U + i*4U;
 }
 static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
 {
-        return 0x00021838 + i*4;
+        return 0x00021838U + i*4U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
 {
-        return 0x00021944;
+        return 0x00021944U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
 {
-        return 0xff << 0;
+        return 0xffU << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
 {
-        return 0x00021948;
+        return 0x00021948U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 fuse_status_opt_fbio_r(void)
 {
-        return 0x00021c14;
+        return 0x00021c14U;
 }
 static inline u32 fuse_status_opt_fbio_data_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 fuse_status_opt_fbio_data_m(void)
 {
-        return 0xffff << 0;
+        return 0xffffU << 0U;
 }
 static inline u32 fuse_status_opt_fbio_data_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
 {
-        return 0x00021d70 + i*4;
+        return 0x00021d70U + i*4U;
 }
 static inline u32 fuse_status_opt_fbp_r(void)
 {
-        return 0x00021d38;
+        return 0x00021d38U;
 }
 static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
-        return (r >> (0 + i*1)) & 0x1;
+        return (r >> (0U + i*1U)) & 0x1U;
 }
 static inline u32 fuse_opt_ecc_en_r(void)
 {
-        return 0x00021228;
+        return 0x00021228U;
 }
 static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
 {
-        return 0x000213f0;
+        return 0x000213f0U;
 }
 static inline u32 fuse_opt_sec_debug_en_r(void)
 {
-        return 0x00021218;
+        return 0x00021218U;
 }
 static inline u32 fuse_opt_priv_sec_en_r(void)
 {
-        return 0x00021434;
+        return 0x00021434U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
index a6dce722..4702f575 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
@@ -58,1226 +58,1226 @@
 
 static inline u32 gmmu_new_pde_is_pte_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pde_is_pte_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pde_aperture_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pde_aperture_invalid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
 {
-        return 0x6;
+        return 0x6U;
 }
 static inline u32 gmmu_new_pde_address_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xfffffffU) << 8U;
 }
 static inline u32 gmmu_new_pde_address_sys_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pde_vol_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pde_vol_true_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gmmu_new_pde_vol_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pde_address_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 gmmu_new_pde__size_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gmmu_new_dual_pde_is_pte_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
 {
-        return 0x6;
+        return 0x6U;
 }
 static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
 {
-        return 0x6;
+        return 0x6U;
 }
 static inline u32 gmmu_new_dual_pde_vol_small_w(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_dual_pde_vol_big_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xfffffffU) << 8U;
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gmmu_new_dual_pde_address_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gmmu_new_dual_pde__size_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gmmu_new_pte__size_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gmmu_new_pte_valid_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_valid_true_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gmmu_new_pte_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pte_privilege_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_privilege_true_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gmmu_new_pte_privilege_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pte_address_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xfffffffU) << 8U;
 }
 static inline u32 gmmu_new_pte_address_sys_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_address_vid_f(u32 v)
 {
-        return (v & 0xffffff) << 8;
+        return (v & 0xffffffU) << 8U;
 }
 static inline u32 gmmu_new_pte_address_vid_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_vol_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_vol_true_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gmmu_new_pte_vol_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pte_aperture_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
 {
-        return 0x6;
+        return 0x6U;
 }
 static inline u32 gmmu_new_pte_read_only_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 gmmu_new_pte_read_only_true_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gmmu_new_pte_comptagline_f(u32 v)
 {
-        return (v & 0x3ffff) << 4;
+        return (v & 0x3ffffU) << 4U;
 }
 static inline u32 gmmu_new_pte_comptagline_w(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gmmu_new_pte_kind_f(u32 v)
 {
-        return (v & 0xff) << 24;
+        return (v & 0xffU) << 24U;
 }
 static inline u32 gmmu_new_pte_kind_w(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gmmu_new_pte_address_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 gmmu_pte_kind_f(u32 v)
 {
-        return (v & 0xff) << 4;
+        return (v & 0xffU) << 4U;
 }
 static inline u32 gmmu_pte_kind_w(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gmmu_pte_kind_invalid_v(void)
 {
-        return 0x000000ff;
+        return 0x000000ffU;
 }
 static inline u32 gmmu_pte_kind_pitch_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gmmu_pte_kind_z16_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gmmu_pte_kind_z16_2c_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
 {
-        return 0x00000005;
+        return 0x00000005U;
 }
 static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
 {
-        return 0x00000006;
+        return 0x00000006U;
 }
 static inline u32 gmmu_pte_kind_z16_2z_v(void)
 {
-        return 0x00000007;
+        return 0x00000007U;
 }
 static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
 {
-        return 0x00000009;
+        return 0x00000009U;
 }
 static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
 {
-        return 0x0000000a;
+        return 0x0000000aU;
 }
 static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
 {
-        return 0x0000000b;
+        return 0x0000000bU;
 }
 static inline u32 gmmu_pte_kind_z16_2cz_v(void)
 {
-        return 0x00000036;
+        return 0x00000036U;
 }
 static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
 {
-        return 0x00000037;
+        return 0x00000037U;
 }
 static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
 {
-        return 0x00000038;
+        return 0x00000038U;
 }
 static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
 {
-        return 0x00000039;
+        return 0x00000039U;
 }
 static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
 {
-        return 0x0000005f;
+        return 0x0000005fU;
 }
 static inline u32 gmmu_pte_kind_z16_4cz_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
 {
-        return 0x0000000d;
+        return 0x0000000dU;
 }
 static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
 {
-        return 0x0000000e;
+        return 0x0000000eU;
 }
 static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
 {
-        return 0x0000000f;
+        return 0x0000000fU;
 }
 static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gmmu_pte_kind_s8z24_v(void)
 {
-        return 0x00000011;
+        return 0x00000011U;
 }
 static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
 {
-        return 0x00000012;
+        return 0x00000012U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
 {
-        return 0x00000013;
+        return 0x00000013U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
 {
-        return 0x00000014;
+        return 0x00000014U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
 {
-        return 0x00000015;
+        return 0x00000015U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
 {
-        return 0x00000016;
+        return 0x00000016U;
 }
 static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
 {
-        return 0x00000017;
+        return 0x00000017U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
 {
-        return 0x00000018;
+        return 0x00000018U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
 {
-        return 0x00000019;
+        return 0x00000019U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
 {
-        return 0x0000001a;
+        return 0x0000001aU;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
 {
-        return 0x0000001b;
+        return 0x0000001bU;
 }
 static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
 {
-        return 0x0000001c;
+        return 0x0000001cU;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
 {
-        return 0x0000001d;
+        return 0x0000001dU;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
 {
-        return 0x0000001e;
+        return 0x0000001eU;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
 {
-        return 0x0000001f;
+        return 0x0000001fU;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
 {
-        return 0x00000021;
+        return 0x00000021U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
 {
-        return 0x00000022;
+        return 0x00000022U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
 {
-        return 0x00000023;
+        return 0x00000023U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
 {
-        return 0x00000024;
+        return 0x00000024U;
 }
 static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
 {
-        return 0x00000025;
+        return 0x00000025U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
 {
-        return 0x00000026;
+        return 0x00000026U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
 {
-        return 0x00000027;
+        return 0x00000027U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
 {
-        return 0x00000028;
+        return 0x00000028U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
 {
-        return 0x00000029;
+        return 0x00000029U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
 {
-        return 0x0000002e;
+        return 0x0000002eU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
 {
-        return 0x0000002f;
+        return 0x0000002fU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
 {
-        return 0x00000030;
+        return 0x00000030U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
 {
-        return 0x00000031;
+        return 0x00000031U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
 {
-        return 0x00000032;
+        return 0x00000032U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
 {
-        return 0x00000033;
+        return 0x00000033U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
 {
-        return 0x00000034;
+        return 0x00000034U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
 {
-        return 0x00000035;
+        return 0x00000035U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
 {
-        return 0x0000003a;
+        return 0x0000003aU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
 {
-        return 0x0000003b;
+        return 0x0000003bU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
 {
-        return 0x0000003c;
+        return 0x0000003cU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
 {
-        return 0x0000003d;
+        return 0x0000003dU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
 {
-        return 0x0000003e;
+        return 0x0000003eU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
 {
-        return 0x0000003f;
+        return 0x0000003fU;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
 {
-        return 0x00000040;
+        return 0x00000040U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
 {
-        return 0x00000041;
+        return 0x00000041U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
 {
-        return 0x00000042;
+        return 0x00000042U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
 {
-        return 0x00000043;
+        return 0x00000043U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
 {
-        return 0x00000044;
+        return 0x00000044U;
 }
 static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
 {
-        return 0x00000045;
+        return 0x00000045U;
 }
 static inline u32 gmmu_pte_kind_z24s8_v(void)
 {
-        return 0x00000046;
+        return 0x00000046U;
 }
 static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
 {
-        return 0x00000047;
+        return 0x00000047U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
 {
-        return 0x00000048;
+        return 0x00000048U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
 {
-        return 0x00000049;
+        return 0x00000049U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
 {
-        return 0x0000004a;
+        return 0x0000004aU;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
 {
-        return 0x0000004b;
+        return 0x0000004bU;
 }
 static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
 {
-        return 0x0000004c;
+        return 0x0000004cU;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
 {
-        return 0x0000004d;
+        return 0x0000004dU;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
 {
-        return 0x0000004e;
+        return 0x0000004eU;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
 {
-        return 0x0000004f;
+        return 0x0000004fU;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
 {
-        return 0x00000050;
+        return 0x00000050U;
 }
 static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
 {
-        return 0x00000051;
+        return 0x00000051U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
 {
-        return 0x00000052;
+        return 0x00000052U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
 {
-        return 0x00000053;
+        return 0x00000053U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
 {
-        return 0x00000054;
+        return 0x00000054U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
 {
-        return 0x00000055;
+        return 0x00000055U;
 }
 static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
 {
-        return 0x00000056;
+        return 0x00000056U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
 {
-        return 0x00000057;
+        return 0x00000057U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
 {
-        return 0x00000058;
+        return 0x00000058U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
 {
-        return 0x00000059;
+        return 0x00000059U;
 }
 static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
 {
-        return 0x0000005a;
+        return 0x0000005aU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
 {
-        return 0x0000005b;
+        return 0x0000005bU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
 {
-        return 0x0000005c;
+        return 0x0000005cU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
 {
-        return 0x0000005d;
+        return 0x0000005dU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
 {
-        return 0x0000005e;
+        return 0x0000005eU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
 {
-        return 0x00000063;
+        return 0x00000063U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
 {
-        return 0x00000064;
+        return 0x00000064U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
 {
-        return 0x00000065;
+        return 0x00000065U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
 {
-        return 0x00000066;
+        return 0x00000066U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
 {
-        return 0x00000067;
+        return 0x00000067U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
 {
-        return 0x00000068;
+        return 0x00000068U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
 {
-        return 0x00000069;
+        return 0x00000069U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
 {
-        return 0x0000006a;
+        return 0x0000006aU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
 {
-        return 0x0000006f;
+        return 0x0000006fU;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
 {
-        return 0x00000070;
+        return 0x00000070U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
 {
-        return 0x00000071;
+        return 0x00000071U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
 {
-        return 0x00000072;
+        return 0x00000072U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
 {
-        return 0x00000073;
+        return 0x00000073U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
 {
-        return 0x00000074;
+        return 0x00000074U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
 {
-        return 0x00000075;
+        return 0x00000075U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
 {
-        return 0x00000076;
+        return 0x00000076U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
 {
-        return 0x00000077;
+        return 0x00000077U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
 {
-        return 0x00000078;
+        return 0x00000078U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
 {
-        return 0x00000079;
+        return 0x00000079U;
 }
 static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
 {
-        return 0x0000007a;
+        return 0x0000007aU;
 }
 static inline u32 gmmu_pte_kind_zf32_v(void)
 {
-        return 0x0000007b;
+        return 0x0000007bU;
 }
 static inline u32 gmmu_pte_kind_zf32_1z_v(void)
 {
-        return 0x0000007c;
+        return 0x0000007cU;
 }
 static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
 {
-        return 0x0000007d;
+        return 0x0000007dU;
 }
 static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
 {
-        return 0x0000007e;
+        return 0x0000007eU;
 }
 static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
 {
-        return 0x0000007f;
+        return 0x0000007fU;
 }
 static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
 {
-        return 0x00000080;
+        return 0x00000080U;
 }
 static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
 {
-        return 0x00000081;
+        return 0x00000081U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
 {
-        return 0x00000082;
+        return 0x00000082U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
 {
-        return 0x00000083;
+        return 0x00000083U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
 {
-        return 0x00000084;
+        return 0x00000084U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
 {
-        return 0x00000085;
+        return 0x00000085U;
 }
 static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
 {
-        return 0x00000086;
+        return 0x00000086U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
 {
-        return 0x00000087;
+        return 0x00000087U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
 {
-        return 0x00000088;
+        return 0x00000088U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
 {
-        return 0x00000089;
+        return 0x00000089U;
 }
 static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
 {
-        return 0x0000008a;
+        return 0x0000008aU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
 {
-        return 0x0000008b;
+        return 0x0000008bU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
 {
-        return 0x0000008c;
+        return 0x0000008cU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
 {
-        return 0x0000008d;
+        return 0x0000008dU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
 {
-        return 0x0000008e;
+        return 0x0000008eU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
 {
-        return 0x0000008f;
+        return 0x0000008fU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
 {
-        return 0x00000090;
+        return 0x00000090U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
 {
-        return 0x00000091;
+        return 0x00000091U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
 {
-        return 0x00000092;
+        return 0x00000092U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
 {
-        return 0x00000097;
+        return 0x00000097U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
 {
-        return 0x00000098;
+        return 0x00000098U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
 {
-        return 0x00000099;
+        return 0x00000099U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
 {
-        return 0x0000009a;
+        return 0x0000009aU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
 {
-        return 0x0000009b;
+        return 0x0000009bU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
 {
-        return 0x0000009c;
+        return 0x0000009cU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
 {
-        return 0x0000009d;
+        return 0x0000009dU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
 {
-        return 0x0000009e;
+        return 0x0000009eU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
 {
-        return 0x0000009f;
+        return 0x0000009fU;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
 {
-        return 0x000000a0;
+        return 0x000000a0U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
 {
-        return 0x000000a1;
+        return 0x000000a1U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
 {
-        return 0x000000a2;
+        return 0x000000a2U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
 {
-        return 0x000000a3;
+        return 0x000000a3U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
 {
-        return 0x000000a4;
+        return 0x000000a4U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
 {
-        return 0x000000a5;
+        return 0x000000a5U;
 }
 static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
 {
-        return 0x000000a6;
+        return 0x000000a6U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
 {
-        return 0x000000a7;
+        return 0x000000a7U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
 {
-        return 0x000000a8;
+        return 0x000000a8U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
 {
-        return 0x000000a9;
+        return 0x000000a9U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
 {
-        return 0x000000aa;
+        return 0x000000aaU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
 {
-        return 0x000000ab;
+        return 0x000000abU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
 {
-        return 0x000000ac;
+        return 0x000000acU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
 {
-        return 0x000000ad;
+        return 0x000000adU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
 {
-        return 0x000000ae;
+        return 0x000000aeU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
 {
-        return 0x000000b3;
+        return 0x000000b3U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
 {
-        return 0x000000b4;
+        return 0x000000b4U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
 {
-        return 0x000000b5;
+        return 0x000000b5U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
 {
-        return 0x000000b6;
+        return 0x000000b6U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
 {
-        return 0x000000b7;
+        return 0x000000b7U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
 {
-        return 0x000000b8;
+        return 0x000000b8U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
 {
-        return 0x000000b9;
+        return 0x000000b9U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
 {
-        return 0x000000ba;
+        return 0x000000baU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
 {
-        return 0x000000bb;
+        return 0x000000bbU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
 {
-        return 0x000000bc;
+        return 0x000000bcU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
 {
-        return 0x000000bd;
+        return 0x000000bdU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
 {
-        return 0x000000be;
+        return 0x000000beU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
 {
-        return 0x000000bf;
+        return 0x000000bfU;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
 {
-        return 0x000000c0;
+        return 0x000000c0U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
 {
-        return 0x000000c1;
+        return 0x000000c1U;
 }
 static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
 {
-        return 0x000000c2;
+        return 0x000000c2U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
 {
-        return 0x000000c3;
+        return 0x000000c3U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
 {
-        return 0x000000c4;
+        return 0x000000c4U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
 {
-        return 0x000000c5;
+        return 0x000000c5U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
 {
-        return 0x000000c6;
+        return 0x000000c6U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
 {
-        return 0x000000c7;
+        return 0x000000c7U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
 {
-        return 0x000000c8;
+        return 0x000000c8U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
 {
-        return 0x000000ce;
+        return 0x000000ceU;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
 {
-        return 0x000000cf;
+        return 0x000000cfU;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
 {
-        return 0x000000d0;
+        return 0x000000d0U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
 {
-        return 0x000000d1;
+        return 0x000000d1U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
 {
-        return 0x000000d2;
+        return 0x000000d2U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
 {
-        return 0x000000d3;
+        return 0x000000d3U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
 {
-        return 0x000000d4;
+        return 0x000000d4U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
 {
-        return 0x000000d5;
+        return 0x000000d5U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
 {
-        return 0x000000d6;
+        return 0x000000d6U;
 }
 static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
 {
-        return 0x000000d7;
+        return 0x000000d7U;
 }
 static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
 {
-        return 0x000000fe;
+        return 0x000000feU;
 }
 static inline u32 gmmu_pte_kind_c32_2c_v(void)
 {
-        return 0x000000d8;
+        return 0x000000d8U;
 }
 static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
 {
-        return 0x000000d9;
+        return 0x000000d9U;
 }
 static inline u32 gmmu_pte_kind_c32_2cba_v(void)
 {
-        return 0x000000da;
+        return 0x000000daU;
 }
 static inline u32 gmmu_pte_kind_c32_2cra_v(void)
 {
-        return 0x000000db;
+        return 0x000000dbU;
 }
 static inline u32 gmmu_pte_kind_c32_2bra_v(void)
 {
-        return 0x000000dc;
+        return 0x000000dcU;
 }
 static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
 {
-        return 0x000000dd;
+        return 0x000000ddU;
 }
 static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
 {
-        return 0x000000de;
+        return 0x000000deU;
 }
 static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
 {
-        return 0x000000cc;
+        return 0x000000ccU;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
 {
-        return 0x000000df;
+        return 0x000000dfU;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
 {
-        return 0x000000e0;
+        return 0x000000e0U;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
 {
-        return 0x000000e1;
+        return 0x000000e1U;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
 {
-        return 0x000000e2;
+        return 0x000000e2U;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
 {
-        return 0x000000e3;
+        return 0x000000e3U;
 }
 static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
 {
-        return 0x0000002c;
+        return 0x0000002cU;
 }
 static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
 {
-        return 0x000000e4;
+        return 0x000000e4U;
 }
 static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
 {
-        return 0x000000e5;
+        return 0x000000e5U;
 }
 static inline u32 gmmu_pte_kind_c64_2c_v(void)
 {
-        return 0x000000e6;
+        return 0x000000e6U;
 }
 static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
 {
-        return 0x000000e7;
+        return 0x000000e7U;
 }
 static inline u32 gmmu_pte_kind_c64_2cba_v(void)
 {
-        return 0x000000e8;
+        return 0x000000e8U;
 }
 static inline u32 gmmu_pte_kind_c64_2cra_v(void)
 {
-        return 0x000000e9;
+        return 0x000000e9U;
 }
 static inline u32 gmmu_pte_kind_c64_2bra_v(void)
 {
-        return 0x000000ea;
+        return 0x000000eaU;
 }
 static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
 {
-        return 0x000000eb;
+        return 0x000000ebU;
 }
 static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
 {
-        return 0x000000ec;
+        return 0x000000ecU;
 }
 static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
 {
-        return 0x000000cd;
+        return 0x000000cdU;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
 {
-        return 0x000000ed;
+        return 0x000000edU;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
 {
-        return 0x000000ee;
+        return 0x000000eeU;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
 {
-        return 0x000000ef;
+        return 0x000000efU;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
 {
-        return 0x000000f0;
+        return 0x000000f0U;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
 {
-        return 0x000000f1;
+        return 0x000000f1U;
 }
 static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
 {
-        return 0x0000002d;
+        return 0x0000002dU;
 }
 static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
 {
-        return 0x000000f2;
+        return 0x000000f2U;
 }
 static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
 {
-        return 0x000000f3;
+        return 0x000000f3U;
 }
 static inline u32 gmmu_pte_kind_c128_2c_v(void)
 {
-        return 0x000000f4;
+        return 0x000000f4U;
 }
 static inline u32 gmmu_pte_kind_c128_2cr_v(void)
 {
-        return 0x000000f5;
+        return 0x000000f5U;
 }
 static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
 {
-        return 0x000000f6;
+        return 0x000000f6U;
 }
 static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
 {
-        return 0x000000f7;
+        return 0x000000f7U;
 }
 static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
 {
-        return 0x000000f8;
+        return 0x000000f8U;
 }
 static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
 {
-        return 0x000000f9;
+        return 0x000000f9U;
 }
 static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
 {
-        return 0x000000fa;
+        return 0x000000faU;
 }
 static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
 {
-        return 0x000000fb;
+        return 0x000000fbU;
 }
 static inline u32 gmmu_pte_kind_x8c24_v(void)
 {
-        return 0x000000fc;
+        return 0x000000fcU;
 }
 static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
 {
-        return 0x000000fd;
+        return 0x000000fdU;
 }
 static inline u32 gmmu_pte_kind_smsked_message_v(void)
 {
-        return 0x000000ca;
+        return 0x000000caU;
 }
 static inline u32 gmmu_pte_kind_smhost_message_v(void)
 {
-        return 0x000000cb;
+        return 0x000000cbU;
 }
 static inline u32 gmmu_pte_kind_s8_v(void)
 {
-        return 0x0000002a;
+        return 0x0000002aU;
 }
 static inline u32 gmmu_pte_kind_s8_2s_v(void)
 {
-        return 0x0000002b;
+        return 0x0000002bU;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index 5fc01634..27760a73 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -58,4278 +58,4282 @@
 
 static inline u32 gr_intr_r(void)
 {
-        return 0x00400100;
+        return 0x00400100U;
 }
 static inline u32 gr_intr_notify_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_intr_notify_reset_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_intr_semaphore_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_intr_semaphore_reset_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_intr_illegal_method_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_intr_illegal_method_reset_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_intr_illegal_notify_pending_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_intr_illegal_notify_reset_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_intr_firmware_method_f(u32 v)
 {
-        return (v & 0x1) << 8;
+        return (v & 0x1U) << 8U;
 }
 static inline u32 gr_intr_firmware_method_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_intr_firmware_method_reset_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_intr_illegal_class_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_intr_illegal_class_reset_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_intr_fecs_error_pending_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 gr_intr_fecs_error_reset_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 gr_intr_class_error_pending_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 gr_intr_class_error_reset_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 gr_intr_exception_pending_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 gr_intr_exception_reset_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 gr_fecs_intr_r(void)
 {
-        return 0x00400144;
+        return 0x00400144U;
 }
 static inline u32 gr_class_error_r(void)
 {
-        return 0x00400110;
+        return 0x00400110U;
 }
 static inline u32 gr_class_error_code_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_intr_nonstall_r(void)
 {
-        return 0x00400120;
+        return 0x00400120U;
 }
 static inline u32 gr_intr_nonstall_trap_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_intr_en_r(void)
 {
-        return 0x0040013c;
+        return 0x0040013cU;
 }
 static inline u32 gr_exception_r(void)
 {
-        return 0x00400108;
+        return 0x00400108U;
 }
 static inline u32 gr_exception_fe_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_exception_gpc_m(void)
 {
-        return 0x1 << 24;
+        return 0x1U << 24U;
 }
 static inline u32 gr_exception_memfmt_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_exception_ds_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_sked_m(void)
+{
+        return 0x1U << 8U;
 }
 static inline u32 gr_exception1_r(void)
 {
-        return 0x00400118;
+        return 0x00400118U;
 }
 static inline u32 gr_exception1_gpc_0_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_exception2_r(void)
 {
-        return 0x0040011c;
+        return 0x0040011cU;
 }
 static inline u32 gr_exception_en_r(void)
 {
-        return 0x00400138;
+        return 0x00400138U;
 }
 static inline u32 gr_exception_en_fe_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_exception1_en_r(void)
 {
-        return 0x00400130;
+        return 0x00400130U;
 }
 static inline u32 gr_exception2_en_r(void)
 {
-        return 0x00400134;
+        return 0x00400134U;
 }
 static inline u32 gr_gpfifo_ctl_r(void)
 {
-        return 0x00400500;
+        return 0x00400500U;
 }
 static inline u32 gr_gpfifo_ctl_access_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
 {
-        return (v & 0x1) << 16;
+        return (v & 0x1U) << 16U;
 }
 static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 gr_gpfifo_status_r(void)
 {
-        return 0x00400504;
+        return 0x00400504U;
 }
 static inline u32 gr_trapped_addr_r(void)
 {
-        return 0x00400704;
+        return 0x00400704U;
 }
 static inline u32 gr_trapped_addr_mthd_v(u32 r)
 {
-        return (r >> 2) & 0xfff;
+        return (r >> 2U) & 0xfffU;
 }
 static inline u32 gr_trapped_addr_subch_v(u32 r)
 {
-        return (r >> 16) & 0x7;
+        return (r >> 16U) & 0x7U;
 }
 static inline u32 gr_trapped_data_lo_r(void)
 {
-        return 0x00400708;
+        return 0x00400708U;
 }
 static inline u32 gr_trapped_data_hi_r(void)
 {
-        return 0x0040070c;
+        return 0x0040070cU;
 }
 static inline u32 gr_status_r(void)
 {
-        return 0x00400700;
+        return 0x00400700U;
 }
 static inline u32 gr_status_fe_method_upper_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 gr_status_fe_method_lower_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 gr_status_fe_method_lower_idle_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_status_fe_gi_v(u32 r)
 {
-        return (r >> 21) & 0x1;
+        return (r >> 21U) & 0x1U;
 }
 static inline u32 gr_status_mask_r(void)
 {
-        return 0x00400610;
+        return 0x00400610U;
 }
 static inline u32 gr_status_1_r(void)
 {
-        return 0x00400604;
+        return 0x00400604U;
 }
 static inline u32 gr_status_2_r(void)
 {
-        return 0x00400608;
+        return 0x00400608U;
 }
 static inline u32 gr_engine_status_r(void)
 {
-        return 0x0040060c;
+        return 0x0040060cU;
 }
 static inline u32 gr_engine_status_value_busy_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_pri_be0_becs_be_exception_r(void)
 {
-        return 0x00410204;
+        return 0x00410204U;
 }
 static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
 {
-        return 0x00410208;
+        return 0x00410208U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
 {
-        return 0x00502c90;
+        return 0x00502c90U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
 {
-        return 0x00502c94;
+        return 0x00502c94U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
 {
-        return 0x00504508;
+        return 0x00504508U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
-        return 0x0050450c;
+        return 0x0050450cU;
 }
 static inline u32 gr_activity_0_r(void)
 {
-        return 0x00400380;
+        return 0x00400380U;
 }
 static inline u32 gr_activity_1_r(void)
 {
-        return 0x00400384;
+        return 0x00400384U;
 }
 static inline u32 gr_activity_2_r(void)
 {
-        return 0x00400388;
+        return 0x00400388U;
 }
 static inline u32 gr_activity_4_r(void)
 {
-        return 0x00400390;
+        return 0x00400390U;
 }
 static inline u32 gr_activity_4_gpc0_s(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 gr_activity_4_gpc0_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_activity_4_gpc0_m(void)
 {
-        return 0x7 << 0;
+        return 0x7U << 0U;
 }
 static inline u32 gr_activity_4_gpc0_v(u32 r)
 {
-        return (r >> 0) & 0x7;
+        return (r >> 0U) & 0x7U;
 }
 static inline u32 gr_activity_4_gpc0_empty_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_activity_4_gpc0_preempted_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
 {
-        return 0x00501000;
+        return 0x00501000U;
 }
 static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
 {
-        return 0x00419000;
+        return 0x00419000U;
 }
 static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
-        return 0x005046a4;
+        return 0x005046a4U;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 {
-        return 0x00419ea4;
+        return 0x00419ea4U;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_pri_sked_activity_r(void)
 {
-        return 0x00407054;
+        return 0x00407054U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
 {
-        return 0x00502c80;
+        return 0x00502c80U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
 {
-        return 0x00502c84;
+        return 0x00502c84U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
 {
-        return 0x00502c88;
+        return 0x00502c88U;
 }
 static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
 {
-        return 0x00502c8c;
+        return 0x00502c8cU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
 {
-        return 0x00504500;
+        return 0x00504500U;
 }
 static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
 {
-        return 0x00504d00;
+        return 0x00504d00U;
 }
 static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
 {
-        return 0x00501d00;
+        return 0x00501d00U;
 }
 static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
 {
-        return 0x0041ac80;
+        return 0x0041ac80U;
 }
 static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
 {
-        return 0x0041ac84;
+        return 0x0041ac84U;
 }
 static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
 {
-        return 0x0041ac88;
+        return 0x0041ac88U;
 }
 static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
 {
-        return 0x0041ac8c;
+        return 0x0041ac8cU;
 }
 static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
 {
-        return 0x0041c500;
+        return 0x0041c500U;
 }
 static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
 {
-        return 0x0041cd00;
+        return 0x0041cd00U;
 }
 static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
 {
-        return 0x00419d00;
+        return 0x00419d00U;
 }
 static inline u32 gr_pri_be0_becs_be_activity0_r(void)
 {
-        return 0x00410200;
+        return 0x00410200U;
 }
 static inline u32 gr_pri_be1_becs_be_activity0_r(void)
 {
-        return 0x00410600;
+        return 0x00410600U;
 }
 static inline u32 gr_pri_bes_becs_be_activity0_r(void)
 {
-        return 0x00408a00;
+        return 0x00408a00U;
 }
 static inline u32 gr_pri_ds_mpipe_status_r(void)
 {
-        return 0x00405858;
+        return 0x00405858U;
 }
 static inline u32 gr_pri_fe_go_idle_info_r(void)
 {
-        return 0x00404194;
+        return 0x00404194U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
 {
-        return 0x00504238;
+        return 0x00504238U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
 {
-        return 0x005046b8;
+        return 0x005046b8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void)
 {
-        return 8;
+        return 8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
 {
-        return 0x005044a0;
+        return 0x005044a0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
 {
-        return 0x005046bc;
+        return 0x005046bcU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
 {
-        return 0x005046c0;
+        return 0x005046c0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
 {
-        return 0x005044a4;
+        return 0x005044a4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
 {
-        return 0xff << 0;
+        return 0xffU << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
 {
-        return 0xff << 8;
+        return 0xffU << 8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
 {
-        return (r >> 8) & 0xff;
+        return (r >> 8U) & 0xffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
 {
-        return 0xff << 16;
+        return 0xffU << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
 {
-        return (r >> 16) & 0xff;
+        return (r >> 16U) & 0xffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
 {
-        return 0x005042c4;
+        return 0x005042c4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
 {
-        return 0x00504218;
+        return 0x00504218U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
 {
-        return 0xffff << 0;
+        return 0xffffU << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
 {
-        return 0xffff << 16;
+        return 0xffffU << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
 {
-        return (r >> 16) & 0xffff;
+        return (r >> 16U) & 0xffffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
 {
-        return 0x005042ec;
+        return 0x005042ecU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
 {
-        return 0xffff << 0;
+        return 0xffffU << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
 {
-        return 0xffff << 16;
+        return 0xffffU << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
 {
-        return (r >> 16) & 0xffff;
+        return (r >> 16U) & 0xffffU;
 }
 static inline u32 gr_pri_be0_crop_status1_r(void)
 {
-        return 0x00410134;
+        return 0x00410134U;
 }
 static inline u32 gr_pri_bes_crop_status1_r(void)
 {
-        return 0x00408934;
+        return 0x00408934U;
 }
 static inline u32 gr_pri_be0_zrop_status_r(void)
 {
-        return 0x00410048;
+        return 0x00410048U;
 }
 static inline u32 gr_pri_be0_zrop_status2_r(void)
 {
-        return 0x0041004c;
+        return 0x0041004cU;
 }
 static inline u32 gr_pri_bes_zrop_status_r(void)
 {
-        return 0x00408848;
+        return 0x00408848U;
 }
 static inline u32 gr_pri_bes_zrop_status2_r(void)
 {
-        return 0x0040884c;
+        return 0x0040884cU;
 }
 static inline u32 gr_pipe_bundle_address_r(void)
 {
-        return 0x00400200;
+        return 0x00400200U;
 }
 static inline u32 gr_pipe_bundle_address_value_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_pipe_bundle_data_r(void)
 {
-        return 0x00400204;
+        return 0x00400204U;
 }
 static inline u32 gr_pipe_bundle_config_r(void)
 {
-        return 0x00400208;
+        return 0x00400208U;
 }
 static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_fe_hww_esr_r(void)
 {
-        return 0x00404000;
+        return 0x00404000U;
 }
 static inline u32 gr_fe_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_fe_hww_esr_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_fe_go_idle_timeout_r(void)
 {
-        return 0x00404154;
+        return 0x00404154U;
 }
 static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
 {
-        return 0x7fffffff;
+        return 0x7fffffffU;
 }
 static inline u32 gr_fe_object_table_r(u32 i)
 {
-        return 0x00404200 + i*4;
+        return 0x00404200U + i*4U;
 }
 static inline u32 gr_fe_object_table_nvclass_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_fe_tpc_fs_r(void)
 {
-        return 0x004041c4;
+        return 0x004041c4U;
 }
 static inline u32 gr_pri_mme_shadow_raw_index_r(void)
 {
-        return 0x00404488;
+        return 0x00404488U;
 }
 static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_pri_mme_shadow_raw_data_r(void)
 {
-        return 0x0040448c;
+        return 0x0040448cU;
 }
 static inline u32 gr_mme_hww_esr_r(void)
 {
-        return 0x00404490;
+        return 0x00404490U;
 }
 static inline u32 gr_mme_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_mme_hww_esr_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_memfmt_hww_esr_r(void)
 {
-        return 0x00404600;
+        return 0x00404600U;
 }
 static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_fecs_cpuctl_r(void)
 {
-        return 0x00409100;
+        return 0x00409100U;
 }
 static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 gr_fecs_cpuctl_alias_r(void)
 {
-        return 0x00409130;
+        return 0x00409130U;
 }
 static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 gr_fecs_dmactl_r(void)
 {
-        return 0x0040910c;
+        return 0x0040910cU;
 }
 static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_fecs_os_r(void)
 {
-        return 0x00409080;
+        return 0x00409080U;
 }
 static inline u32 gr_fecs_idlestate_r(void)
 {
-        return 0x0040904c;
+        return 0x0040904cU;
 }
 static inline u32 gr_fecs_mailbox0_r(void)
 {
-        return 0x00409040;
+        return 0x00409040U;
 }
 static inline u32 gr_fecs_mailbox1_r(void)
 {
-        return 0x00409044;
+        return 0x00409044U;
 }
 static inline u32 gr_fecs_irqstat_r(void)
 {
-        return 0x00409008;
+        return 0x00409008U;
 }
 static inline u32 gr_fecs_irqmode_r(void)
 {
-        return 0x0040900c;
+        return 0x0040900cU;
 }
 static inline u32 gr_fecs_irqmask_r(void)
 {
-        return 0x00409018;
+        return 0x00409018U;
 }
 static inline u32 gr_fecs_irqdest_r(void)
 {
-        return 0x0040901c;
+        return 0x0040901cU;
 }
 static inline u32 gr_fecs_curctx_r(void)
 {
-        return 0x00409050;
+        return 0x00409050U;
 }
 static inline u32 gr_fecs_nxtctx_r(void)
 {
-        return 0x00409054;
+        return 0x00409054U;
 }
 static inline u32 gr_fecs_engctl_r(void)
 {
-        return 0x004090a4;
+        return 0x004090a4U;
 }
 static inline u32 gr_fecs_debug1_r(void)
 {
-        return 0x00409090;
+        return 0x00409090U;
 }
 static inline u32 gr_fecs_debuginfo_r(void)
 {
-        return 0x00409094;
+        return 0x00409094U;
 }
 static inline u32 gr_fecs_icd_cmd_r(void)
 {
-        return 0x00409200;
+        return 0x00409200U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_s(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_m(void)
 {
-        return 0xf << 0;
+        return 0xfU << 0U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
 {
-        return (r >> 0) & 0xf;
+        return (r >> 0U) & 0xfU;
 }
 static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
 {
-        return 0xe;
+        return 0xeU;
 }
 static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
 {
-        return (v & 0x1f) << 8;
+        return (v & 0x1fU) << 8U;
 }
 static inline u32 gr_fecs_icd_rdata_r(void)
 {
-        return 0x0040920c;
+        return 0x0040920cU;
 }
 static inline u32 gr_fecs_imemc_r(u32 i)
 {
-        return 0x00409180 + i*16;
+        return 0x00409180U + i*16U;
 }
 static inline u32 gr_fecs_imemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 gr_fecs_imemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_fecs_imemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 gr_fecs_imemd_r(u32 i)
 {
-        return 0x00409184 + i*16;
+        return 0x00409184U + i*16U;
 }
 static inline u32 gr_fecs_imemt_r(u32 i)
 {
-        return 0x00409188 + i*16;
+        return 0x00409188U + i*16U;
 }
 static inline u32 gr_fecs_imemt_tag_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_fecs_dmemc_r(u32 i)
 {
-        return 0x004091c0 + i*8;
+        return 0x004091c0U + i*8U;
 }
 static inline u32 gr_fecs_dmemc_offs_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 gr_fecs_dmemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 gr_fecs_dmemc_offs_m(void)
 {
-        return 0x3f << 2;
+        return 0x3fU << 2U;
 }
 static inline u32 gr_fecs_dmemc_offs_v(u32 r)
 {
-        return (r >> 2) & 0x3f;
+        return (r >> 2U) & 0x3fU;
 }
 static inline u32 gr_fecs_dmemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 gr_fecs_dmemd_r(u32 i)
 {
-        return 0x004091c4 + i*8;
+        return 0x004091c4U + i*8U;
 }
 static inline u32 gr_fecs_dmatrfbase_r(void)
 {
-        return 0x00409110;
+        return 0x00409110U;
 }
 static inline u32 gr_fecs_dmatrfmoffs_r(void)
 {
-        return 0x00409114;
+        return 0x00409114U;
 }
 static inline u32 gr_fecs_dmatrffboffs_r(void)
 {
-        return 0x0040911c;
+        return 0x0040911cU;
 }
 static inline u32 gr_fecs_dmatrfcmd_r(void)
 {
-        return 0x00409118;
+        return 0x00409118U;
 }
 static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 gr_fecs_bootvec_r(void)
 {
-        return 0x00409104;
+        return 0x00409104U;
 }
 static inline u32 gr_fecs_bootvec_vec_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fecs_falcon_hwcfg_r(void)
 {
-        return 0x00409108;
+        return 0x00409108U;
 }
 static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
 {
-        return 0x0041a108;
+        return 0x0041a108U;
 }
 static inline u32 gr_fecs_falcon_rm_r(void)
 {
-        return 0x00409084;
+        return 0x00409084U;
 }
 static inline u32 gr_fecs_current_ctx_r(void)
 {
-        return 0x00409b00;
+        return 0x00409b00U;
 }
 static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
 {
-        return (r >> 0) & 0xfffffff;
+        return (r >> 0U) & 0xfffffffU;
 }
 static inline u32 gr_fecs_current_ctx_target_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gr_fecs_current_ctx_target_f(u32 v)
 {
-        return (v & 0x3) << 28;
+        return (v & 0x3U) << 28U;
 }
 static inline u32 gr_fecs_current_ctx_target_m(void)
 {
-        return 0x3 << 28;
+        return 0x3U << 28U;
 }
 static inline u32 gr_fecs_current_ctx_target_v(u32 r)
 {
-        return (r >> 28) & 0x3;
+        return (r >> 28U) & 0x3U;
 }
 static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 gr_fecs_current_ctx_valid_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 gr_fecs_current_ctx_valid_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 gr_fecs_current_ctx_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_method_data_r(void)
 {
-        return 0x00409500;
+        return 0x00409500U;
 }
 static inline u32 gr_fecs_method_push_r(void)
 {
-        return 0x00409504;
+        return 0x00409504U;
 }
 static inline u32 gr_fecs_method_push_adr_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
 {
-        return 0x00000009;
+        return 0x00000009U;
 }
 static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
 {
-        return 0x00000015;
+        return 0x00000015U;
 }
 static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
 {
-        return 0x00000016;
+        return 0x00000016U;
 }
 static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
 {
-        return 0x00000025;
+        return 0x00000025U;
 }
 static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
 {
-        return 0x00000030;
+        return 0x00000030U;
 }
 static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
 {
-        return 0x00000031;
+        return 0x00000031U;
 }
 static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
 {
-        return 0x00000032;
+        return 0x00000032U;
 }
 static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
 {
-        return 0x00000038;
+        return 0x00000038U;
 }
 static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
 {
-        return 0x00000039;
+        return 0x00000039U;
 }
 static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
-        return 0x21;
+        return 0x21U;
 }
 static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
 {
-        return 0x0000003d;
+        return 0x0000003dU;
 }
 static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
 {
-        return 0x0000001a;
+        return 0x0000001aU;
 }
 static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
 {
-        return 0x0000003a;
+        return 0x0000003aU;
 }
 static inline u32 gr_fecs_host_int_status_r(void)
 {
-        return 0x00409c18;
+        return 0x00409c18U;
 }
 static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
 {
-        return (v & 0x1) << 16;
+        return (v & 0x1U) << 16U;
 }
 static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
 {
-        return (v & 0x1) << 17;
+        return (v & 0x1U) << 17U;
 }
 static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
-        return (v & 0x1) << 18;
+        return (v & 0x1U) << 18U;
 }
 static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_fecs_host_int_clear_r(void)
 {
-        return 0x00409c20;
+        return 0x00409c20U;
 }
 static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_fecs_host_int_enable_r(void)
 {
-        return 0x00409c24;
+        return 0x00409c24U;
 }
 static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
 {
-        return 0x20000;
+        return 0x20000U;
 }
 static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
 {
-        return 0x40000;
+        return 0x40000U;
 }
 static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
 {
-        return 0x00409614;
+        return 0x00409614U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
 {
-        return (v & 0x1) << 10;
+        return (v & 0x1U) << 10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
 {
-        return 0x1 << 10;
+        return 0x1U << 10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
 {
-        return (r >> 10) & 0x1;
+        return (r >> 10U) & 0x1U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
 {
-        return 0x0040960c;
+        return 0x0040960cU;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
 {
-        return 0x00409800 + i*4;
+        return 0x00409800U + i*4U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
 {
-        return 0x004098c0 + i*4;
+        return 0x004098c0U + i*4U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
 {
-        return 0x00409840 + i*4;
+        return 0x00409840U + i*4U;
 }
 static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fecs_fs_r(void)
 {
-        return 0x00409604;
+        return 0x00409604U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
 {
-        return 5;
+        return 5U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
 {
-        return (v & 0x1f) << 0;
+        return (v & 0x1fU) << 0U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
 {
-        return 0x1f << 0;
+        return 0x1fU << 0U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_s(void)
 {
-        return 5;
+        return 5U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
 {
-        return (v & 0x1f) << 16;
+        return (v & 0x1fU) << 16U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_m(void)
 {
-        return 0x1f << 16;
+        return 0x1fU << 16U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
 {
-        return (r >> 16) & 0x1f;
+        return (r >> 16U) & 0x1fU;
 }
 static inline u32 gr_fecs_cfg_r(void)
 {
-        return 0x00409620;
+        return 0x00409620U;
 }
 static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 gr_fecs_rc_lanes_r(void)
 {
-        return 0x00409880;
+        return 0x00409880U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
 {
-        return (v & 0x3f) << 0;
+        return (v & 0x3fU) << 0U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
 {
-        return 0x3f << 0;
+        return 0x3fU << 0U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
 {
-        return (r >> 0) & 0x3f;
+        return (r >> 0U) & 0x3fU;
 }
 static inline u32 gr_fecs_ctxsw_status_1_r(void)
 {
-        return 0x00409400;
+        return 0x00409400U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
 {
-        return (v & 0x1) << 12;
+        return (v & 0x1U) << 12U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
 {
-        return 0x1 << 12;
+        return 0x1U << 12U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
 {
-        return (r >> 12) & 0x1;
+        return (r >> 12U) & 0x1U;
 }
 static inline u32 gr_fecs_arb_ctx_adr_r(void)
 {
-        return 0x00409a24;
+        return 0x00409a24U;
 }
 static inline u32 gr_fecs_new_ctx_r(void)
 {
-        return 0x00409b04;
+        return 0x00409b04U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_s(void)
 {
-        return 28;
+        return 28U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_m(void)
 {
-        return 0xfffffff << 0;
+        return 0xfffffffU << 0U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
 {
-        return (r >> 0) & 0xfffffff;
+        return (r >> 0U) & 0xfffffffU;
 }
 static inline u32 gr_fecs_new_ctx_target_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gr_fecs_new_ctx_target_f(u32 v)
 {
-        return (v & 0x3) << 28;
+        return (v & 0x3U) << 28U;
 }
 static inline u32 gr_fecs_new_ctx_target_m(void)
 {
-        return 0x3 << 28;
+        return 0x3U << 28U;
 }
 static inline u32 gr_fecs_new_ctx_target_v(u32 r)
 {
-        return (r >> 28) & 0x3;
+        return (r >> 28U) & 0x3U;
 }
 static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 gr_fecs_new_ctx_valid_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 gr_fecs_new_ctx_valid_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_r(void)
 {
-        return 0x00409a0c;
+        return 0x00409a0cU;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
 {
-        return 28;
+        return 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
 {
-        return 0xfffffff << 0;
+        return 0xfffffffU << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
 {
-        return (r >> 0) & 0xfffffff;
+        return (r >> 0U) & 0xfffffffU;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
 {
-        return (v & 0x3) << 28;
+        return (v & 0x3U) << 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
 {
-        return 0x3 << 28;
+        return 0x3U << 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
 {
-        return (r >> 28) & 0x3;
+        return (r >> 28U) & 0x3U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_r(void)
 {
-        return 0x00409a10;
+        return 0x00409a10U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
 {
-        return 5;
+        return 5U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
 {
-        return (v & 0x1f) << 0;
+        return (v & 0x1fU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
 {
-        return 0x1f << 0;
+        return 0x1fU << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
 {
-        return 0x00409c00;
+        return 0x00409c00U;
 }
 static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
 {
-        return 0x00502c04;
+        return 0x00502c04U;
 }
 static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
-        return 0x00502400;
+        return 0x00502400U;
 }
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
-        return 0x00409420;
+        return 0x00409420U;
 }
 static inline u32 gr_fecs_feature_override_ecc_r(void)
 {
-        return 0x00409658;
+        return 0x00409658U;
 }
 static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
 {
-        return (r >> 3) & 0x1;
+        return (r >> 3U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
 {
-        return (r >> 7) & 0x1;
+        return (r >> 7U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
 {
-        return (r >> 11) & 0x1;
+        return (r >> 11U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
 {
-        return (r >> 15) & 0x1;
+        return (r >> 15U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
 {
-        return (r >> 8) & 0x1;
+        return (r >> 8U) & 0x1U;
 }
 static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
 {
-        return (r >> 12) & 0x1;
+        return (r >> 12U) & 0x1U;
 }
 static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
-        return 0x00502420;
+        return 0x00502420U;
 }
 static inline u32 gr_rstr2d_gpc_map0_r(void)
 {
-        return 0x0040780c;
+        return 0x0040780cU;
 }
 static inline u32 gr_rstr2d_gpc_map1_r(void)
 {
-        return 0x00407810;
+        return 0x00407810U;
 }
 static inline u32 gr_rstr2d_gpc_map2_r(void)
 {
-        return 0x00407814;
+        return 0x00407814U;
 }
 static inline u32 gr_rstr2d_gpc_map3_r(void)
 {
-        return 0x00407818;
+        return 0x00407818U;
 }
 static inline u32 gr_rstr2d_gpc_map4_r(void)
 {
-        return 0x0040781c;
+        return 0x0040781cU;
 }
 static inline u32 gr_rstr2d_gpc_map5_r(void)
 {
-        return 0x00407820;
+        return 0x00407820U;
 }
 static inline u32 gr_rstr2d_map_table_cfg_r(void)
 {
-        return 0x004078bc;
+        return 0x004078bcU;
 }
 static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_pd_hww_esr_r(void)
 {
-        return 0x00406018;
+        return 0x00406018U;
 }
 static inline u32 gr_pd_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_pd_hww_esr_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
 {
-        return 0x00406028 + i*4;
+        return 0x00406028U + i*4U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
 {
-        return (v & 0xf) << 4;
+        return (v & 0xfU) << 4U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
 {
-        return (v & 0xf) << 8;
+        return (v & 0xfU) << 8U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
 {
-        return (v & 0xf) << 12;
+        return (v & 0xfU) << 12U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
 {
-        return (v & 0xf) << 16;
+        return (v & 0xfU) << 16U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
 {
-        return (v & 0xf) << 20;
+        return (v & 0xfU) << 20U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
 {
-        return (v & 0xf) << 24;
+        return (v & 0xfU) << 24U;
 }
 static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
 {
-        return (v & 0xf) << 28;
+        return (v & 0xfU) << 28U;
 }
 static inline u32 gr_pd_ab_dist_cfg0_r(void)
 {
-        return 0x004064c0;
+        return 0x004064c0U;
 }
 static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_pd_ab_dist_cfg1_r(void)
 {
-        return 0x004064c4;
+        return 0x004064c4U;
 }
 static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
 {
-        return 0xffff;
+        return 0xffffU;
 }
 static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
 {
-        return (v & 0xffff) << 16;
+        return (v & 0xffffU) << 16U;
 }
 static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
 {
-        return 0x00000080;
+        return 0x00000080U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_r(void)
 {
-        return 0x004064c8;
+        return 0x004064c8U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
 {
-        return (v & 0x1fff) << 0;
+        return (v & 0x1fffU) << 0U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
 {
-        return 0x000001c0;
+        return 0x000001c0U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
 {
-        return (v & 0x1fff) << 16;
+        return (v & 0x1fffU) << 16U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
 {
-        return 0x00000182;
+        return 0x00000182U;
 }
 static inline u32 gr_pd_dist_skip_table_r(u32 i)
 {
-        return 0x004064d0 + i*4;
+        return 0x004064d0U + i*4U;
 }
 static inline u32 gr_pd_dist_skip_table__size_1_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
 {
-        return (v & 0xff) << 16;
+        return (v & 0xffU) << 16U;
 }
 static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
 {
-        return (v & 0xff) << 24;
+        return (v & 0xffU) << 24U;
 }
 static inline u32 gr_ds_debug_r(void)
 {
-        return 0x00405800;
+        return 0x00405800U;
 }
 static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
 {
-        return 0x8000000;
+        return 0x8000000U;
 }
 static inline u32 gr_ds_zbc_color_r_r(void)
 {
-        return 0x00405804;
+        return 0x00405804U;
 }
 static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_color_g_r(void)
 {
-        return 0x00405808;
+        return 0x00405808U;
 }
 static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_color_b_r(void)
 {
-        return 0x0040580c;
+        return 0x0040580cU;
 }
 static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_color_a_r(void)
 {
-        return 0x00405810;
+        return 0x00405810U;
 }
 static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_color_fmt_r(void)
 {
-        return 0x00405814;
+        return 0x00405814U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
 {
-        return (v & 0x7f) << 0;
+        return (v & 0x7fU) << 0U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
 {
-        return 0x00000028;
+        return 0x00000028U;
 }
 static inline u32 gr_ds_zbc_z_r(void)
 {
-        return 0x00405818;
+        return 0x00405818U;
 }
 static inline u32 gr_ds_zbc_z_val_s(void)
 {
-        return 32;
+        return 32U;
 }
 static inline u32 gr_ds_zbc_z_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_z_val_m(void)
 {
-        return 0xffffffff << 0;
+        return 0xffffffffU << 0U;
 }
 static inline u32 gr_ds_zbc_z_val_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 gr_ds_zbc_z_val__init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_ds_zbc_z_val__init_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_zbc_z_fmt_r(void)
 {
-        return 0x0040581c;
+        return 0x0040581cU;
 }
 static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_ds_zbc_tbl_index_r(void)
 {
-        return 0x00405820;
+        return 0x00405820U;
 }
 static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_ds_zbc_tbl_ld_r(void)
 {
-        return 0x00405824;
+        return 0x00405824U;
 }
 static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
 {
-        return 0x00405830;
+        return 0x00405830U;
 }
 static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
 {
-        return (v & 0x3fffff) << 0;
+        return (v & 0x3fffffU) << 0U;
 }
 static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
 {
-        return 0x0040585c;
+        return 0x0040585cU;
 }
 static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_ds_hww_esr_r(void)
 {
-        return 0x00405840;
+        return 0x00405840U;
 }
 static inline u32 gr_ds_hww_esr_reset_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_ds_hww_esr_reset_f(u32 v)
 {
-        return (v & 0x1) << 30;
+        return (v & 0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_reset_m(void)
 {
-        return 0x1 << 30;
+        return 0x1U << 30U;
 }
 static inline u32 gr_ds_hww_esr_reset_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 gr_ds_hww_esr_reset_task_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_ds_hww_esr_reset_task_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_ds_hww_esr_en_enabled_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_ds_hww_esr_2_r(void)
 {
-        return 0x00405848;
+        return 0x00405848U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
 {
-        return (v & 0x1) << 30;
+        return (v & 0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_m(void)
 {
-        return 0x1 << 30;
+        return 0x1U << 30U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_ds_hww_report_mask_r(void)
 {
-        return 0x00405844;
+        return 0x00405844U;
 }
 static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
 {
-        return 0x2000;
+        return 0x2000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
 {
-        return 0x4000;
+        return 0x4000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
 {
-        return 0x8000;
+        return 0x8000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
 {
-        return 0x20000;
+        return 0x20000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
 {
-        return 0x40000;
+        return 0x40000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
 {
-        return 0x400000;
+        return 0x400000U;
 }
 static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 gr_ds_hww_report_mask_2_r(void)
 {
-        return 0x0040584c;
+        return 0x0040584cU;
 }
 static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
 {
-        return 0x00405870 + i*4;
+        return 0x00405870U + i*4U;
 }
 static inline u32 gr_scc_bundle_cb_base_r(void)
 {
-        return 0x00408004;
+        return 0x00408004U;
 }
 static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gr_scc_bundle_cb_size_r(void)
 {
-        return 0x00408008;
+        return 0x00408008U;
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
 {
-        return (v & 0x7ff) << 0;
+        return (v & 0x7ffU) << 0U;
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
 {
-        return 0x00000018;
+        return 0x00000018U;
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_scc_pagepool_base_r(void)
 {
-        return 0x0040800c;
+        return 0x0040800cU;
 }
 static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gr_scc_pagepool_r(void)
 {
-        return 0x00408010;
+        return 0x00408010U;
 }
 static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
 {
-        return (v & 0x3ff) << 0;
+        return (v & 0x3ffU) << 0U;
 }
 static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
 {
-        return 10;
+        return 10U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
 {
-        return (v & 0x3ff) << 10;
+        return (v & 0x3ffU) << 10U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
 {
-        return 0x3ff << 10;
+        return 0x3ffU << 10U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
 {
-        return (r >> 10) & 0x3ff;
+        return (r >> 10U) & 0x3ffU;
 }
 static inline u32 gr_scc_pagepool_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_scc_init_r(void)
 {
-        return 0x0040802c;
+        return 0x0040802cU;
 }
 static inline u32 gr_scc_init_ram_trigger_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_scc_hww_esr_r(void)
 {
-        return 0x00408030;
+        return 0x00408030U;
 }
 static inline u32 gr_scc_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_scc_hww_esr_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_sked_hww_esr_r(void)
 {
-        return 0x00407020;
+        return 0x00407020U;
 }
 static inline u32 gr_sked_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_cwd_fs_r(void)
 {
-        return 0x00405b00;
+        return 0x00405b00U;
 }
 static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
 {
-        return 0x00405b60 + i*4;
+        return 0x00405b60U + i*4U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
 {
-        return (v & 0xf) << 4;
+        return (v & 0xfU) << 4U;
 }
 static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
 {
-        return (v & 0xf) << 8;
+        return (v & 0xfU) << 8U;
 }
 static inline u32 gr_cwd_sm_id_r(u32 i)
 {
-        return 0x00405ba0 + i*4;
+        return 0x00405ba0U + i*4U;
 }
 static inline u32 gr_cwd_sm_id__size_1_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_gpc0_fs_gpc_r(void)
 {
-        return 0x00502608;
+        return 0x00502608U;
 }
 static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
 {
-        return (r >> 16) & 0x1f;
+        return (r >> 16U) & 0x1fU;
 }
 static inline u32 gr_gpc0_cfg_r(void)
 {
-        return 0x00502620;
+        return 0x00502620U;
 }
 static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 gr_gpccs_rc_lanes_r(void)
 {
-        return 0x00502880;
+        return 0x00502880U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
 {
-        return (v & 0x3f) << 0;
+        return (v & 0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
 {
-        return 0x3f << 0;
+        return 0x3fU << 0U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
 {
-        return (r >> 0) & 0x3f;
+        return (r >> 0U) & 0x3fU;
 }
 static inline u32 gr_gpccs_rc_lane_size_r(void)
 {
-        return 0x00502910;
+        return 0x00502910U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_s(void)
 {
-        return 24;
+        return 24U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_m(void)
 {
-        return 0xffffff << 0;
+        return 0xffffffU << 0U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
 {
-        return (r >> 0) & 0xffffff;
+        return (r >> 0U) & 0xffffffU;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_zcull_fs_r(void)
 {
-        return 0x00500910;
+        return 0x00500910U;
 }
 static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
 {
-        return (v & 0x1ff) << 0;
+        return (v & 0x1ffU) << 0U;
 }
 static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
 {
-        return (v & 0xf) << 16;
+        return (v & 0xfU) << 16U;
 }
 static inline u32 gr_gpc0_zcull_ram_addr_r(void)
 {
-        return 0x00500914;
+        return 0x00500914U;
 }
 static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
 {
-        return (v & 0xf) << 8;
+        return (v & 0xfU) << 8U;
 }
 static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
 {
-        return 0x00500918;
+        return 0x00500918U;
 }
 static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
 {
-        return 0x00800000;
+        return 0x00800000U;
 }
 static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
 {
-        return 0x00500920;
+        return 0x00500920U;
 }
 static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
 {
-        return 0x00500a04 + i*32;
+        return 0x00500a04U + i*32U;
 }
 static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
 {
-        return 0x00000040;
+        return 0x00000040U;
 }
 static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
 {
-        return 0x00500c10 + i*4;
+        return 0x00500c10U + i*4U;
 }
 static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
 {
-        return 0x00500c30 + i*4;
+        return 0x00500c30U + i*4U;
 }
 static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
 {
-        return 0x00504088;
+        return 0x00504088U;
 }
 static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
 {
-        return 0x00504698;
+        return 0x00504698U;
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
 {
-        return 0x0050469c;
+        return 0x0050469cU;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
 {
-        return (r >> 8) & 0xfff;
+        return (r >> 8U) & 0xfffU;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
 {
-        return (r >> 20) & 0xfff;
+        return (r >> 20U) & 0xfffU;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
 {
-        return 0x00503018;
+        return 0x00503018U;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
 {
-        return 0x005030c0;
+        return 0x005030c0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
 {
-        return (v & 0x3fffff) << 0;
+        return (v & 0x3fffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 {
-        return 0x3fffff << 0;
+        return 0x3fffffU << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
-        return 0x00030000;
+        return 0x00030000U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
 {
-        return 0x00030a00;
+        return 0x00030a00U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
 {
-        return 0x005030f4;
+        return 0x005030f4U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
 {
-        return 0x005030e4;
+        return 0x005030e4U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
 {
-        return 0xffff << 0;
+        return 0xffffU << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
 {
-        return 0x00000800;
+        return 0x00000800U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
 {
-        return 0x005030f8;
+        return 0x005030f8U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
 {
-        return 0x005030f0;
+        return 0x005030f0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
 {
-        return (v & 0x3fffff) << 0;
+        return (v & 0x3fffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
 {
-        return 0x00030000;
+        return 0x00030000U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
 {
-        return 0x00419b00;
+        return 0x00419b00U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
 {
-        return 0x00419b04;
+        return 0x00419b04U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
 {
-        return 21;
+        return 21U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
 {
-        return (v & 0x1fffff) << 0;
+        return (v & 0x1fffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
 {
-        return 0x1fffff << 0;
+        return 0x1fffffU << 0U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
 {
-        return (r >> 0) & 0x1fffff;
+        return (r >> 0U) & 0x1fffffU;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
 {
-        return 0x00419a3c;
+        return 0x00419a3cU;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
 }
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
-        return 0x0041a0ac;
+        return 0x0041a0acU;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
 {
-        return (v & 0x3f) << 0;
+        return (v & 0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
 {
-        return 0x3f << 0;
+        return 0x3fU << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
 {
-        return (r >> 0) & 0x3f;
+        return (r >> 0U) & 0x3fU;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_s(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
 {
-        return (v & 0x3f) << 6;
+        return (v & 0x3fU) << 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_m(void)
 {
-        return 0x3f << 6;
+        return 0x3fU << 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
 {
-        return (r >> 6) & 0x3f;
+        return (r >> 6U) & 0x3fU;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_s(void)
 {
-        return 12;
+        return 12U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_m(void)
 {
-        return 0xfff << 0;
+        return 0xfffU << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
 {
-        return (r >> 0) & 0xfff;
+        return (r >> 0U) & 0xfffU;
 }
 static inline u32 gr_gpccs_cpuctl_r(void)
 {
-        return 0x0041a100;
+        return 0x0041a100U;
 }
 static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 gr_gpccs_dmactl_r(void)
 {
-        return 0x0041a10c;
+        return 0x0041a10cU;
 }
 static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_gpccs_imemc_r(u32 i)
 {
-        return 0x0041a180 + i*16;
+        return 0x0041a180U + i*16U;
 }
 static inline u32 gr_gpccs_imemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 gr_gpccs_imemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 gr_gpccs_imemd_r(u32 i)
 {
-        return 0x0041a184 + i*16;
+        return 0x0041a184U + i*16U;
 }
 static inline u32 gr_gpccs_imemt_r(u32 i)
 {
-        return 0x0041a188 + i*16;
+        return 0x0041a188U + i*16U;
 }
 static inline u32 gr_gpccs_imemt__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 gr_gpccs_imemt_tag_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpccs_dmemc_r(u32 i)
 {
-        return 0x0041a1c0 + i*8;
+        return 0x0041a1c0U + i*8U;
 }
 static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 gr_gpccs_dmemd_r(u32 i)
 {
-        return 0x0041a1c4 + i*8;
+        return 0x0041a1c4U + i*8U;
 }
 static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
 {
-        return 0x0041a800 + i*4;
+        return 0x0041a800U + i*4U;
 }
 static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
 {
-        return 0x00418e24;
+        return 0x00418e24U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
 {
-        return 32;
+        return 32U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
 {
-        return 0xffffffff << 0;
+        return 0xffffffffU << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
 {
-        return 0x00418e28;
+        return 0x00418e28U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
 {
-        return 11;
+        return 11U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
 {
-        return (v & 0x7ff) << 0;
+        return (v & 0x7ffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
 {
-        return 0x7ff << 0;
+        return 0x7ffU << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 {
-        return (r >> 0) & 0x7ff;
+        return (r >> 0U) & 0x7ffU;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
 {
-        return 0x00000018;
+        return 0x00000018U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
 {
-        return 0x18;
+        return 0x18U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
 {
-        return 0x00500ee4;
+        return 0x00500ee4U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
 {
-        return (v & 0xffff) << 0;
+        return (v & 0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
 {
-        return 0x00000250;
+        return 0x00000250U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
 {
-        return 0x00500ee0;
+        return 0x00500ee0U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
 {
-        return 0x00418eec;
+        return 0x00418eecU;
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
 {
-        return 0x00000100;
+        return 0x00000100U;
 }
 static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
 {
-        return 0x0041befc;
+        return 0x0041befcU;
 }
 static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
 {
-        return 0x00418ea0 + i*4;
+        return 0x00418ea0U + i*4U;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 {
-        return (v & 0x3fffff) << 0;
+        return (v & 0x3fffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-        return 0x3fffff << 0;
+        return 0x3fffffU << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
 {
-        return 0x00418010 + i*4;
+        return 0x00418010U + i*4U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
 {
-        return 0x0041804c + i*4;
+        return 0x0041804cU + i*4U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
 {
-        return 0x00418088 + i*4;
+        return 0x00418088U + i*4U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
 {
-        return 0x004180c4 + i*4;
+        return 0x004180c4U + i*4U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
 {
-        return 0x00500100;
+        return 0x00500100U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
 {
-        return 0x00418110 + i*4;
+        return 0x00418110U + i*4U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
 {
-        return 0x0050014c;
+        return 0x0050014cU;
 }
 static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
 {
-        return 0x00418810;
+        return 0x00418810U;
 }
 static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_crstr_gpc_map0_r(void)
 {
-        return 0x00418b08;
+        return 0x00418b08U;
 }
 static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_gpc_map1_r(void)
 {
-        return 0x00418b0c;
+        return 0x00418b0cU;
 }
 static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_gpc_map2_r(void)
 {
-        return 0x00418b10;
+        return 0x00418b10U;
 }
 static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_gpc_map3_r(void)
 {
-        return 0x00418b14;
+        return 0x00418b14U;
 }
 static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_gpc_map4_r(void)
 {
-        return 0x00418b18;
+        return 0x00418b18U;
 }
 static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_gpc_map5_r(void)
 {
-        return 0x00418b1c;
+        return 0x00418b1cU;
 }
 static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
 {
-        return (v & 0x7) << 5;
+        return (v & 0x7U) << 5U;
 }
 static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
 {
-        return (v & 0x7) << 10;
+        return (v & 0x7U) << 10U;
 }
 static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
 {
-        return (v & 0x7) << 15;
+        return (v & 0x7U) << 15U;
 }
 static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
 {
-        return (v & 0x7) << 25;
+        return (v & 0x7U) << 25U;
 }
 static inline u32 gr_crstr_map_table_cfg_r(void)
 {
-        return 0x00418bb8;
+        return 0x00418bb8U;
 }
 static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
 {
-        return 0x00418980;
+        return 0x00418980U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
 {
-        return (v & 0x7) << 4;
+        return (v & 0x7U) << 4U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
 {
-        return (v & 0x7) << 16;
+        return (v & 0x7U) << 16U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
 {
-        return (v & 0x7) << 24;
+        return (v & 0x7U) << 24U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
 {
-        return (v & 0x7) << 28;
+        return (v & 0x7U) << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
 {
-        return 0x00418984;
+        return 0x00418984U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
 {
-        return (v & 0x7) << 4;
+        return (v & 0x7U) << 4U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
 {
-        return (v & 0x7) << 16;
+        return (v & 0x7U) << 16U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
 {
-        return (v & 0x7) << 24;
+        return (v & 0x7U) << 24U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
 {
-        return (v & 0x7) << 28;
+        return (v & 0x7U) << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
 {
-        return 0x00418988;
+        return 0x00418988U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
 {
-        return (v & 0x7) << 4;
+        return (v & 0x7U) << 4U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
 {
-        return (v & 0x7) << 16;
+        return (v & 0x7U) << 16U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
 {
-        return (v & 0x7) << 24;
+        return (v & 0x7U) << 24U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
 {
-        return (v & 0x7) << 28;
+        return (v & 0x7U) << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
 {
-        return 0x7 << 28;
+        return 0x7U << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
 {
-        return (r >> 28) & 0x7;
+        return (r >> 28U) & 0x7U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
 {
-        return 0x0041898c;
+        return 0x0041898cU;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
 {
-        return (v & 0x7) << 0;
+        return (v & 0x7U) << 0U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
 {
-        return (v & 0x7) << 4;
+        return (v & 0x7U) << 4U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
 {
-        return (v & 0x7) << 16;
+        return (v & 0x7U) << 16U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
 {
-        return (v & 0x7) << 20;
+        return (v & 0x7U) << 20U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
 {
-        return (v & 0x7) << 24;
+        return (v & 0x7U) << 24U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
 {
-        return (v & 0x7) << 28;
+        return (v & 0x7U) << 28U;
 }
 static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
 {
-        return 0x00418c6c;
+        return 0x00418c6cU;
 }
 static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
 {
-        return 0x00419004;
+        return 0x00419004U;
 }
 static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_gcc_pagepool_r(void)
 {
-        return 0x00419008;
+        return 0x00419008U;
 }
 static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
 {
-        return (v & 0x3ff) << 0;
+        return (v & 0x3ffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
 {
-        return 0x0041980c;
+        return 0x0041980cU;
 }
 static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
 {
-        return 0x00419848;
+        return 0x00419848U;
 }
 static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
 {
-        return (v & 0x1) << 28;
+        return (v & 0x1U) << 28U;
 }
 static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
 {
-        return 0x00419c00;
+        return 0x00419c00U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
 {
-        return 0x00419c2c;
+        return 0x00419c2cU;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
 {
-        return (v & 0x1) << 28;
+        return (v & 0x1U) << 28U;
 }
 static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
 {
-        return 0x00419e44;
+        return 0x00419e44U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
 {
-        return 0x2000;
+        return 0x2000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
 {
-        return 0x4000;
+        return 0x4000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
 {
-        return 0x8000;
+        return 0x8000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
 {
-        return 0x20000;
+        return 0x20000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
 {
-        return 0x40000;
+        return 0x40000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
 {
-        return 0x400000;
+        return 0x400000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
 {
-        return 0x00504644;
+        return 0x00504644U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
 {
-        return 0x00419e4c;
+        return 0x00419e4cU;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
 {
-        return 0x0050464c;
+        return 0x0050464cU;
 }
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
 {
-        return 0x00419d0c;
+        return 0x00419d0cU;
 }
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
-        return 0x0050450c;
+        return 0x0050450cU;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
 {
-        return 0x0041ac94;
+        return 0x0041ac94U;
 }
 static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
 {
-        return (v & 0xff) << 16;
+        return (v & 0xffU) << 16U;
 }
 static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
 {
-        return 0x00502c90;
+        return 0x00502c90U;
 }
 static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
 {
-        return (r >> 16) & 0xff;
+        return (r >> 16U) & 0xffU;
 }
 static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
 {
-        return 0x00504508;
+        return 0x00504508U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
-        return 0x00504610;
+        return 0x00504610U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
 {
-        return 0x00504614;
+        return 0x00504614U;
 }
 static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
 {
-        return 0x00504618;
+        return 0x00504618U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
 {
-        return 0x00504624;
+        return 0x00504624U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
 {
-        return 0x00504628;
+        return 0x00504628U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
 {
-        return 0x00504634;
+        return 0x00504634U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
 {
-        return 0x00504638;
+        return 0x00504638U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
 {
-        return 0x00419e24;
+        return 0x00419e24U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
-        return 0x0050460c;
+        return 0x0050460cU;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
 {
-        return 0x00419e50;
+        return 0x00419e50U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
 {
-        return 0x00504650;
+        return 0x00504650U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
 {
-        return 0x00504224;
+        return 0x00504224U;
 }
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
-        return 0x00504648;
+        return 0x00504648U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
 {
-        return 0x1 << 24;
+        return 0x1U << 24U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
 {
-        return 0x7 << 25;
+        return 0x7U << 25U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
 {
-        return 0x00504654;
+        return 0x00504654U;
 }
 static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
 {
-        return 0x00504770;
+        return 0x00504770U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 {
-        return 0x00419f70;
+        return 0x00419f70U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
 {
-        return 0x0050477c;
+        return 0x0050477cU;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 {
-        return 0x00419f7c;
+        return 0x00419f7cU;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
 {
-        return 0x0041be08;
+        return 0x0041be08U;
 }
 static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
 {
-        return 0x0041bf00;
+        return 0x0041bf00U;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
 {
-        return 0x0041bf04;
+        return 0x0041bf04U;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
 {
-        return 0x0041bf08;
+        return 0x0041bf08U;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
 {
-        return 0x0041bf0c;
+        return 0x0041bf0cU;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
 {
-        return 0x0041bf10;
+        return 0x0041bf10U;
 }
 static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
 {
-        return 0x0041bf14;
+        return 0x0041bf14U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
 {
-        return 0x0041bfd0;
+        return 0x0041bfd0U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
 {
-        return (v & 0x1f) << 16;
+        return (v & 0x1fU) << 16U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
 {
-        return (v & 0x7) << 21;
+        return (v & 0x7U) << 21U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 24;
+        return (v & 0x1fU) << 24U;
 }
 static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
 {
-        return 0x0041bfd4;
+        return 0x0041bfd4U;
 }
 static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
 {
-        return 0x0041bfe4;
+        return 0x0041bfe4U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 0;
+        return (v & 0x1fU) << 0U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 5;
+        return (v & 0x1fU) << 5U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 10;
+        return (v & 0x1fU) << 10U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 15;
+        return (v & 0x1fU) << 15U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 20;
+        return (v & 0x1fU) << 20U;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
 {
-        return (v & 0x1f) << 25;
+        return (v & 0x1fU) << 25U;
 }
 static inline u32 gr_bes_zrop_settings_r(void)
 {
-        return 0x00408850;
+        return 0x00408850U;
 }
 static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_be0_crop_debug3_r(void)
 {
-        return 0x00410108;
+        return 0x00410108U;
 }
 static inline u32 gr_bes_crop_debug3_r(void)
 {
-        return 0x00408908;
+        return 0x00408908U;
 }
 static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 gr_bes_crop_settings_r(void)
 {
-        return 0x00408958;
+        return 0x00408958U;
 }
 static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
 {
-        return 0x000000c0;
+        return 0x000000c0U;
 }
 static inline u32 gr_zcull_subregion_qty_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
 {
-        return 0x00504604;
+        return 0x00504604U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
 {
-        return 0x00504608;
+        return 0x00504608U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
 {
-        return 0x0050465c;
+        return 0x0050465cU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
 {
-        return 0x00504660;
+        return 0x00504660U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
 {
-        return 0x00504664;
+        return 0x00504664U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
 {
-        return 0x00504668;
+        return 0x00504668U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
 {
-        return 0x0050466c;
+        return 0x0050466cU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
 {
-        return 0x00504658;
+        return 0x00504658U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
 {
-        return 0x00504730;
+        return 0x00504730U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
 {
-        return 0x00504734;
+        return 0x00504734U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
 {
-        return 0x00504738;
+        return 0x00504738U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
 {
-        return 0x0050473c;
+        return 0x0050473cU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
 {
-        return 0x00504740;
+        return 0x00504740U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
 {
-        return 0x00504744;
+        return 0x00504744U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
 {
-        return 0x00504748;
+        return 0x00504748U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
 {
-        return 0x0050474c;
+        return 0x0050474cU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
 {
-        return 0x00504678;
+        return 0x00504678U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
 {
-        return 0x00504694;
+        return 0x00504694U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
 {
-        return 0x005046f0;
+        return 0x005046f0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
 {
-        return 0x00504700;
+        return 0x00504700U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
 {
-        return 0x005046f4;
+        return 0x005046f4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
 {
-        return 0x00504704;
+        return 0x00504704U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
 {
-        return 0x005046f8;
+        return 0x005046f8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
 {
-        return 0x00504708;
+        return 0x00504708U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
 {
-        return 0x005046fc;
+        return 0x005046fcU;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
 {
-        return 0x0050470c;
+        return 0x0050470cU;
 }
 static inline u32 gr_fe_pwr_mode_r(void)
 {
-        return 0x00404170;
+        return 0x00404170U;
 }
 static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 gr_fe_pwr_mode_req_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 gr_fe_pwr_mode_req_send_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 gr_fe_pwr_mode_req_done_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
 {
-        return 0x00418880;
+        return 0x00418880U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
 {
-        return 0x1 << 11;
+        return 0x1U << 11U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
 {
-        return 0x3 << 3;
+        return 0x3U << 3U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
 {
-        return 0x3 << 5;
+        return 0x3U << 5U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
 {
-        return 0x3 << 28;
+        return 0x3U << 28U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
 {
-        return 0x1 << 30;
+        return 0x1U << 30U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {
-        return 0x00418890;
+        return 0x00418890U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
 {
-        return 0x00418894;
+        return 0x00418894U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
 {
-        return 0x004188b0;
+        return 0x004188b0U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
 {
-        return (r >> 16) & 0x1;
+        return (r >> 16U) & 0x1U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
 {
-        return 0x004188b4;
+        return 0x004188b4U;
 }
 static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
 {
-        return 0x004188b8;
+        return 0x004188b8U;
 }
 static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
 {
-        return 0x004188ac;
+        return 0x004188acU;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
 {
-        return 0x00419e10;
+        return 0x00419e10U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
 {
-        return 0x1 << 3;
+        return 0x1U << 3U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
 {
-        return 0x1 << 30;
+        return 0x1U << 30U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
 {
-        return 0x004041c0;
+        return 0x004041c0U;
 }
 static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_debug_2_r(void)
 {
-        return 0x00400088;
+        return 0x00400088U;
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void)
 {
-        return 0x1 << 23;
+        return 0x1U << 23U;
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r)
 {
-        return (r >> 23) & 0x1;
+        return (r >> 23U) & 0x1U;
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
 {
-        return 0x00419c84;
+        return 0x00419c84U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
 {
-        return 0x7 << 8;
+        return 0x7U << 8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
 {
-        return 0x00419f78;
+        return 0x00419f78U;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
 {
-        return 0x3 << 11;
+        return 0x3U << 11U;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 gr_gpcs_tc_debug0_r(void)
 {
-        return 0x00418708;
+        return 0x00418708U;
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
 {
-        return 0xff << 0;
+        return 0xffU << 0U;
 }
 static inline u32 gr_gpc0_prop_debug1_r(void)
 {
-        return 0x00500400;
+        return 0x00500400U;
 }
 static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v)
 {
-        return (v & 0x3) << 14;
+        return (v & 0x3U) << 14U;
 }
 static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void)
 {
-        return 0x3 << 14;
+        return 0x3U << 14U;
 }
 static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
index 4e922e64..721a48ae 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
@@ -58,530 +58,530 @@
 
 static inline u32 ltc_pltcg_base_v(void)
 {
-        return 0x00140000;
+        return 0x00140000U;
 }
 static inline u32 ltc_pltcg_extent_v(void)
 {
-        return 0x0017ffff;
+        return 0x0017ffffU;
 }
 static inline u32 ltc_ltc0_ltss_v(void)
 {
-        return 0x00140200;
+        return 0x00140200U;
 }
 static inline u32 ltc_ltc0_lts0_v(void)
 {
-        return 0x00140400;
+        return 0x00140400U;
 }
 static inline u32 ltc_ltcs_ltss_v(void)
 {
-        return 0x0017e200;
+        return 0x0017e200U;
 }
 static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
 {
-        return 0x0014046c;
+        return 0x0014046cU;
 }
 static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
 {
-        return 0x00140518;
+        return 0x00140518U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
 {
-        return 0x0017e318;
+        return 0x0017e318U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
 {
-        return 0x1 << 15;
+        return 0x1U << 15U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
 {
-        return 0x00140494;
+        return 0x00140494U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
 {
-        return (r >> 16) & 0x3;
+        return (r >> 16U) & 0x3U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
 {
-        return 0x0017e26c;
+        return 0x0017e26cU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
 {
-        return 0x0014046c;
+        return 0x0014046cU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
 {
-        return 0x0017e270;
+        return 0x0017e270U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
 {
-        return (v & 0x3ffff) << 0;
+        return (v & 0x3ffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
 {
-        return 0x0017e274;
+        return 0x0017e274U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
 {
-        return (v & 0x3ffff) << 0;
+        return (v & 0x3ffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
 {
-        return 0x0003ffff;
+        return 0x0003ffffU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
 {
-        return 0x0017e278;
+        return 0x0017e278U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
 {
-        return 0x0000000b;
+        return 0x0000000bU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
 {
-        return (r >> 0) & 0x3ffffff;
+        return (r >> 0U) & 0x3ffffffU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
 {
-        return 0x0017e27c;
+        return 0x0017e27cU;
 }
 static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
 {
-        return 0x0017e000;
+        return 0x0017e000U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
 {
-        return 0x0017e280;
+        return 0x0017e280U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
 {
-        return (r >> 24) & 0xf;
+        return (r >> 24U) & 0xfU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
 {
-        return (r >> 28) & 0xf;
+        return (r >> 28U) & 0xfU;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
 {
-        return 0x0017e3f4;
+        return 0x0017e3f4U;
 }
 static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
 {
-        return 0x0017e2ac;
+        return 0x0017e2acU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
 {
-        return (v & 0x1f) << 16;
+        return (v & 0x1fU) << 16U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
 {
-        return 0x0017e338;
+        return 0x0017e338U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
 {
-        return 0x0017e33c + i*4;
+        return 0x0017e33cU + i*4U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
 {
-        return 0x0017e34c;
+        return 0x0017e34cU;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
 {
-        return 32;
+        return 32U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
 {
-        return 0xffffffff << 0;
+        return 0xffffffffU << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
 {
-        return 0x0017e2b0;
+        return 0x0017e2b0U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
 {
-        return 0x0017e214;
+        return 0x0017e214U;
 }
 static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
 {
-        return 0x00140214;
+        return 0x00140214U;
 }
 static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
 {
-        return 0x00142214;
+        return 0x00142214U;
 }
 static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_intr_r(void)
 {
-        return 0x0017e20c;
+        return 0x0017e20cU;
 }
 static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
 {
-        return 0x1 << 20;
+        return 0x1U << 20U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
 {
-        return 0x1 << 30;
+        return 0x1U << 30U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 ltc_ltc0_lts0_intr_r(void)
 {
-        return 0x0014040c;
+        return 0x0014040cU;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
 {
-        return 0x0014051c;
+        return 0x0014051cU;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
 {
-        return 0xff << 0;
+        return 0xffU << 0U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
 {
-        return 0xff << 16;
+        return 0xffU << 16U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
 {
-        return (r >> 16) & 0xff;
+        return (r >> 16U) & 0xffU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
 {
-        return 0x0017e2a0;
+        return 0x0017e2a0U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
 {
-        return (r >> 8) & 0xf;
+        return (r >> 8U) & 0xfU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
 {
-        return 0x300;
+        return 0x300U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
 {
-        return (r >> 28) & 0x1;
+        return (r >> 28U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
 {
-        return (r >> 29) & 0x1;
+        return (r >> 29U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
 {
-        return 0x0017e2a4;
+        return 0x0017e2a4U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
 {
-        return (r >> 8) & 0xf;
+        return (r >> 8U) & 0xfU;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
 {
-        return 0x300;
+        return 0x300U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
 {
-        return (r >> 16) & 0x1;
+        return (r >> 16U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
 {
-        return (r >> 28) & 0x1;
+        return (r >> 28U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
 {
-        return (r >> 29) & 0x1;
+        return (r >> 29U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
 {
-        return 0x001402a0;
+        return 0x001402a0U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
 {
-        return 0x001402a4;
+        return 0x001402a4U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
 {
-        return 0x001422a0;
+        return 0x001422a0U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
 {
-        return 0x001422a4;
+        return 0x001422a4U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
 {
-        return 0x0014058c;
+        return 0x0014058cU;
 }
 static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
 {
-        return (r >> 0) & 0xffff;
+        return (r >> 0U) & 0xffffU;
 }
 static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
 {
-        return (r >> 16) & 0x1f;
+        return (r >> 16U) & 0x1fU;
 }
 static inline u32 ltc_ltca_g_axi_pctrl_r(void)
 {
-        return 0x00160000;
+        return 0x00160000U;
 }
 static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
 {
-        return (v & 0xff) << 2;
+        return (v & 0xffU) << 2U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
index 9d1d6189..dbf0ce35 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
@@ -58,194 +58,194 @@
 
 static inline u32 mc_boot_0_r(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 mc_boot_0_architecture_v(u32 r)
 {
-        return (r >> 24) & 0x1f;
+        return (r >> 24U) & 0x1fU;
 }
 static inline u32 mc_boot_0_implementation_v(u32 r)
 {
-        return (r >> 20) & 0xf;
+        return (r >> 20U) & 0xfU;
 }
 static inline u32 mc_boot_0_major_revision_v(u32 r)
 {
-        return (r >> 4) & 0xf;
+        return (r >> 4U) & 0xfU;
 }
 static inline u32 mc_boot_0_minor_revision_v(u32 r)
 {
-        return (r >> 0) & 0xf;
+        return (r >> 0U) & 0xfU;
 }
 static inline u32 mc_intr_r(u32 i)
 {
-        return 0x00000100 + i*4;
+        return 0x00000100U + i*4U;
 }
 static inline u32 mc_intr_pfifo_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 mc_intr_replayable_fault_pending_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 mc_intr_pgraph_pending_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 mc_intr_pmu_pending_f(void)
 {
-        return 0x1000000;
+        return 0x1000000U;
 }
 static inline u32 mc_intr_ltc_pending_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 mc_intr_priv_ring_pending_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 mc_intr_pbus_pending_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 mc_intr_en_r(u32 i)
 {
-        return 0x00000140 + i*4;
+        return 0x00000140U + i*4U;
 }
 static inline u32 mc_intr_en_set_r(u32 i)
 {
-        return 0x00000160 + i*4;
+        return 0x00000160U + i*4U;
 }
 static inline u32 mc_intr_en_clear_r(u32 i)
 {
-        return 0x00000180 + i*4;
+        return 0x00000180U + i*4U;
 }
 static inline u32 mc_enable_r(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 mc_enable_xbar_enabled_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 mc_enable_l2_enabled_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 mc_enable_pmedia_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 mc_enable_pmedia_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 mc_enable_pmedia_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
 }
 static inline u32 mc_enable_pmedia_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 mc_enable_priv_ring_enabled_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 mc_enable_ce0_m(void)
 {
-        return 0x1 << 6;
+        return 0x1U << 6U;
 }
 static inline u32 mc_enable_pfifo_enabled_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 mc_enable_pgraph_enabled_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 mc_enable_pwr_v(u32 r)
 {
-        return (r >> 13) & 0x1;
+        return (r >> 13U) & 0x1U;
 }
 static inline u32 mc_enable_pwr_disabled_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 mc_enable_pwr_enabled_f(void)
 {
-        return 0x2000;
+        return 0x2000U;
 }
 static inline u32 mc_enable_pfb_enabled_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 mc_enable_ce2_m(void)
 {
-        return 0x1 << 21;
+        return 0x1U << 21U;
 }
 static inline u32 mc_enable_ce2_enabled_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 mc_enable_blg_enabled_f(void)
 {
-        return 0x8000000;
+        return 0x8000000U;
 }
 static inline u32 mc_enable_perfmon_enabled_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 mc_enable_hub_enabled_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 mc_intr_ltc_r(void)
 {
-        return 0x000001c0;
+        return 0x000001c0U;
 }
 static inline u32 mc_enable_pb_r(void)
 {
-        return 0x00000204;
+        return 0x00000204U;
 }
 static inline u32 mc_enable_pb_0_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 mc_enable_pb_0_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 mc_enable_pb_0_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 mc_enable_pb_0_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 mc_enable_pb_0_enabled_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
 {
-        return (v & 0x1) << (0 + i*1);
+        return (v & 0x1U) << (0U + i*1U);
 }
 static inline u32 mc_elpg_enable_r(void)
 {
-        return 0x0000020c;
+        return 0x0000020cU;
 }
 static inline u32 mc_elpg_enable_xbar_enabled_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 mc_elpg_enable_pfb_enabled_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 mc_elpg_enable_hub_enabled_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
index f9d413de..d49cc95f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
@@ -58,542 +58,542 @@
 
 static inline u32 pbdma_gp_entry1_r(void)
 {
-        return 0x10000004;
+        return 0x10000004U;
 }
 static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 pbdma_gp_entry1_length_f(u32 v)
 {
-        return (v & 0x1fffff) << 10;
+        return (v & 0x1fffffU) << 10U;
 }
 static inline u32 pbdma_gp_entry1_length_v(u32 r)
 {
-        return (r >> 10) & 0x1fffff;
+        return (r >> 10U) & 0x1fffffU;
 }
 static inline u32 pbdma_gp_base_r(u32 i)
 {
-        return 0x00040048 + i*8192;
+        return 0x00040048U + i*8192U;
 }
 static inline u32 pbdma_gp_base__size_1_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 pbdma_gp_base_offset_f(u32 v)
 {
-        return (v & 0x1fffffff) << 3;
+        return (v & 0x1fffffffU) << 3U;
 }
 static inline u32 pbdma_gp_base_rsvd_s(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 pbdma_gp_base_hi_r(u32 i)
 {
-        return 0x0004004c + i*8192;
+        return 0x0004004cU + i*8192U;
 }
 static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
 {
-        return (v & 0x1f) << 16;
+        return (v & 0x1fU) << 16U;
 }
 static inline u32 pbdma_gp_fetch_r(u32 i)
 {
-        return 0x00040050 + i*8192;
+        return 0x00040050U + i*8192U;
 }
 static inline u32 pbdma_gp_get_r(u32 i)
 {
-        return 0x00040014 + i*8192;
+        return 0x00040014U + i*8192U;
 }
 static inline u32 pbdma_gp_put_r(u32 i)
 {
-        return 0x00040000 + i*8192;
+        return 0x00040000U + i*8192U;
 }
 static inline u32 pbdma_pb_fetch_r(u32 i)
 {
-        return 0x00040054 + i*8192;
+        return 0x00040054U + i*8192U;
 }
 static inline u32 pbdma_pb_fetch_hi_r(u32 i)
 {
-        return 0x00040058 + i*8192;
+        return 0x00040058U + i*8192U;
 }
 static inline u32 pbdma_get_r(u32 i)
 {
-        return 0x00040018 + i*8192;
+        return 0x00040018U + i*8192U;
 }
 static inline u32 pbdma_get_hi_r(u32 i)
 {
-        return 0x0004001c + i*8192;
+        return 0x0004001cU + i*8192U;
 }
 static inline u32 pbdma_put_r(u32 i)
 {
-        return 0x0004005c + i*8192;
+        return 0x0004005cU + i*8192U;
 }
 static inline u32 pbdma_put_hi_r(u32 i)
 {
-        return 0x00040060 + i*8192;
+        return 0x00040060U + i*8192U;
 }
 static inline u32 pbdma_formats_r(u32 i)
 {
-        return 0x0004009c + i*8192;
+        return 0x0004009cU + i*8192U;
 }
 static inline u32 pbdma_formats_gp_fermi0_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_formats_pb_fermi1_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_formats_mp_fermi0_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_pb_header_r(u32 i)
 {
-        return 0x00040084 + i*8192;
+        return 0x00040084U + i*8192U;
 }
 static inline u32 pbdma_pb_header_priv_user_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_pb_header_method_zero_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_pb_header_subchannel_zero_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_pb_header_level_main_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_pb_header_first_true_f(void)
 {
-        return 0x400000;
+        return 0x400000U;
 }
 static inline u32 pbdma_pb_header_type_inc_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 pbdma_pb_header_type_non_inc_f(void)
 {
-        return 0x60000000;
+        return 0x60000000U;
 }
 static inline u32 pbdma_hdr_shadow_r(u32 i)
 {
-        return 0x00040118 + i*8192;
+        return 0x00040118U + i*8192U;
 }
 static inline u32 pbdma_subdevice_r(u32 i)
 {
-        return 0x00040094 + i*8192;
+        return 0x00040094U + i*8192U;
 }
 static inline u32 pbdma_subdevice_id_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 pbdma_subdevice_status_active_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 pbdma_method0_r(u32 i)
 {
-        return 0x000400c0 + i*8192;
+        return 0x000400c0U + i*8192U;
 }
 static inline u32 pbdma_method0_fifo_size_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 pbdma_method0_addr_f(u32 v)
 {
-        return (v & 0xfff) << 2;
+        return (v & 0xfffU) << 2U;
 }
 static inline u32 pbdma_method0_addr_v(u32 r)
 {
-        return (r >> 2) & 0xfff;
+        return (r >> 2U) & 0xfffU;
 }
 static inline u32 pbdma_method0_subch_v(u32 r)
 {
-        return (r >> 16) & 0x7;
+        return (r >> 16U) & 0x7U;
 }
 static inline u32 pbdma_method0_first_true_f(void)
 {
-        return 0x400000;
+        return 0x400000U;
 }
 static inline u32 pbdma_method0_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 pbdma_method1_r(u32 i)
 {
-        return 0x000400c8 + i*8192;
+        return 0x000400c8U + i*8192U;
 }
 static inline u32 pbdma_method2_r(u32 i)
 {
-        return 0x000400d0 + i*8192;
+        return 0x000400d0U + i*8192U;
 }
 static inline u32 pbdma_method3_r(u32 i)
 {
-        return 0x000400d8 + i*8192;
+        return 0x000400d8U + i*8192U;
 }
 static inline u32 pbdma_data0_r(u32 i)
 {
-        return 0x000400c4 + i*8192;
+        return 0x000400c4U + i*8192U;
 }
 static inline u32 pbdma_target_r(u32 i)
 {
-        return 0x000400ac + i*8192;
+        return 0x000400acU + i*8192U;
 }
 static inline u32 pbdma_target_engine_sw_f(void)
 {
-        return 0x1f;
+        return 0x1fU;
 }
 static inline u32 pbdma_acquire_r(u32 i)
 {
-        return 0x00040030 + i*8192;
+        return 0x00040030U + i*8192U;
 }
 static inline u32 pbdma_acquire_retry_man_2_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pbdma_acquire_retry_exp_2_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
 {
-        return (v & 0xf) << 11;
+        return (v & 0xfU) << 11U;
 }
 static inline u32 pbdma_acquire_timeout_exp_max_v(void)
 {
-        return 0x0000000f;
+        return 0x0000000fU;
 }
 static inline u32 pbdma_acquire_timeout_exp_max_f(void)
 {
-        return 0x7800;
+        return 0x7800U;
 }
 static inline u32 pbdma_acquire_timeout_man_f(u32 v)
 {
-        return (v & 0xffff) << 15;
+        return (v & 0xffffU) << 15U;
 }
 static inline u32 pbdma_acquire_timeout_man_max_v(void)
 {
-        return 0x0000ffff;
+        return 0x0000ffffU;
 }
 static inline u32 pbdma_acquire_timeout_man_max_f(void)
 {
-        return 0x7fff8000;
+        return 0x7fff8000U;
 }
 static inline u32 pbdma_acquire_timeout_en_enable_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 pbdma_acquire_timeout_en_disable_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_status_r(u32 i)
 {
-        return 0x00040100 + i*8192;
+        return 0x00040100U + i*8192U;
 }
 static inline u32 pbdma_channel_r(u32 i)
 {
-        return 0x00040120 + i*8192;
+        return 0x00040120U + i*8192U;
 }
 static inline u32 pbdma_signature_r(u32 i)
 {
-        return 0x00040010 + i*8192;
+        return 0x00040010U + i*8192U;
 }
 static inline u32 pbdma_signature_hw_valid_f(void)
 {
-        return 0xface;
+        return 0xfaceU;
 }
 static inline u32 pbdma_signature_sw_zero_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_userd_r(u32 i)
 {
-        return 0x00040008 + i*8192;
+        return 0x00040008U + i*8192U;
 }
 static inline u32 pbdma_userd_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 pbdma_userd_addr_f(u32 v)
 {
-        return (v & 0x7fffff) << 9;
+        return (v & 0x7fffffU) << 9U;
 }
 static inline u32 pbdma_userd_hi_r(u32 i)
 {
-        return 0x0004000c + i*8192;
+        return 0x0004000cU + i*8192U;
 }
 static inline u32 pbdma_userd_hi_addr_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 pbdma_config_r(u32 i)
 {
-        return 0x000400f4 + i*8192;
+        return 0x000400f4U + i*8192U;
 }
 static inline u32 pbdma_config_auth_level_privileged_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_hce_ctrl_r(u32 i)
 {
-        return 0x000400e4 + i*8192;
+        return 0x000400e4U + i*8192U;
 }
 static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 pbdma_intr_0_r(u32 i)
 {
-        return 0x00040108 + i*8192;
+        return 0x00040108U + i*8192U;
 }
 static inline u32 pbdma_intr_0_memreq_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 pbdma_intr_0_memreq_pending_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 pbdma_intr_0_memflush_pending_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 pbdma_intr_0_memop_pending_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 pbdma_intr_0_lbreq_pending_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
 {
-        return 0x200;
+        return 0x200U;
 }
 static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
 {
-        return 0x400;
+        return 0x400U;
 }
 static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
 {
-        return 0x1000;
+        return 0x1000U;
 }
 static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
 {
-        return 0x2000;
+        return 0x2000U;
 }
 static inline u32 pbdma_intr_0_gpptr_pending_f(void)
 {
-        return 0x4000;
+        return 0x4000U;
 }
 static inline u32 pbdma_intr_0_gpentry_pending_f(void)
 {
-        return 0x8000;
+        return 0x8000U;
 }
 static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 static inline u32 pbdma_intr_0_pbptr_pending_f(void)
 {
-        return 0x20000;
+        return 0x20000U;
 }
 static inline u32 pbdma_intr_0_pbentry_pending_f(void)
 {
-        return 0x40000;
+        return 0x40000U;
 }
 static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
 {
-        return 0x80000;
+        return 0x80000U;
 }
 static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
 {
-        return 0x100000;
+        return 0x100000U;
 }
 static inline u32 pbdma_intr_0_method_pending_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
 {
-        return 0x400000;
+        return 0x400000U;
 }
 static inline u32 pbdma_intr_0_device_pending_f(void)
 {
-        return 0x800000;
+        return 0x800000U;
 }
 static inline u32 pbdma_intr_0_semaphore_pending_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 pbdma_intr_0_acquire_pending_f(void)
 {
-        return 0x4000000;
+        return 0x4000000U;
 }
 static inline u32 pbdma_intr_0_pri_pending_f(void)
 {
-        return 0x8000000;
+        return 0x8000000U;
 }
 static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 pbdma_intr_0_pbseg_pending_f(void)
 {
-        return 0x40000000;
+        return 0x40000000U;
 }
 static inline u32 pbdma_intr_0_signature_pending_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 static inline u32 pbdma_intr_1_r(u32 i)
 {
-        return 0x00040148 + i*8192;
+        return 0x00040148U + i*8192U;
 }
 static inline u32 pbdma_intr_en_0_r(u32 i)
 {
-        return 0x0004010c + i*8192;
+        return 0x0004010cU + i*8192U;
 }
 static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_intr_en_1_r(u32 i)
 {
-        return 0x0004014c + i*8192;
+        return 0x0004014cU + i*8192U;
 }
 static inline u32 pbdma_intr_stall_r(u32 i)
 {
-        return 0x0004013c + i*8192;
+        return 0x0004013cU + i*8192U;
 }
 static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
 {
-        return 0x100;
+        return 0x100U;
 }
 static inline u32 pbdma_udma_nop_r(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 pbdma_allowed_syncpoints_r(u32 i)
 {
-        return 0x000400e8 + i*8192;
+        return 0x000400e8U + i*8192U;
 }
 static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v)
 {
-        return (v & 0x7fff) << 16;
+        return (v & 0x7fffU) << 16U;
 }
 static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r)
 {
-        return (r >> 16) & 0x7fff;
+        return (r >> 16U) & 0x7fffU;
 }
 static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v)
 {
-        return (v & 0x1) << 15;
+        return (v & 0x1U) << 15U;
 }
 static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
 {
-        return (v & 0x7fff) << 0;
+        return (v & 0x7fffU) << 0U;
 }
 static inline u32 pbdma_syncpointa_r(u32 i)
 {
-        return 0x000400a4 + i*8192;
+        return 0x000400a4U + i*8192U;
 }
 static inline u32 pbdma_syncpointa_payload_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 pbdma_syncpointb_r(u32 i)
 {
-        return 0x000400a8 + i*8192;
+        return 0x000400a8U + i*8192U;
 }
 static inline u32 pbdma_syncpointb_op_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 pbdma_syncpointb_op_wait_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
 {
-        return (r >> 8) & 0xfff;
+        return (r >> 8U) & 0xfffU;
 }
 static inline u32 pbdma_runlist_timeslice_r(u32 i)
 {
-        return 0x000400f8 + i*8192;
+        return 0x000400f8U + i*8192U;
 }
 static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
 {
-        return 0x80;
+        return 0x80U;
 }
 static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
 {
-        return 0x3000;
+        return 0x3000U;
 }
 static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
 {
-        return 0x10000000;
+        return 0x10000000U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
index 3848ef7a..aa0fafe7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
@@ -58,154 +58,154 @@
 
 static inline u32 perf_pmasys_control_r(void)
 {
-        return 0x001b4000;
+        return 0x001b4000U;
 }
 static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
 {
-        return (r >> 5) & 0x1;
+        return (r >> 5U) & 0x1U;
 }
 static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 perf_pmasys_mem_block_r(void)
 {
-        return 0x001b4070;
+        return 0x001b4070U;
 }
 static inline u32 perf_pmasys_mem_block_base_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 perf_pmasys_mem_block_target_f(u32 v)
 {
-        return (v & 0x3) << 28;
+        return (v & 0x3U) << 28U;
 }
 static inline u32 perf_pmasys_mem_block_target_v(u32 r)
 {
-        return (r >> 28) & 0x3;
+        return (r >> 28U) & 0x3U;
 }
 static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 perf_pmasys_mem_block_valid_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 perf_pmasys_mem_block_valid_true_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 perf_pmasys_mem_block_valid_false_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 perf_pmasys_mem_block_valid_false_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 perf_pmasys_outbase_r(void)
 {
-        return 0x001b4074;
+        return 0x001b4074U;
 }
 static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
 {
-        return (v & 0x7ffffff) << 5;
+        return (v & 0x7ffffffU) << 5U;
 }
 static inline u32 perf_pmasys_outbaseupper_r(void)
 {
-        return 0x001b4078;
+        return 0x001b4078U;
 }
 static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 perf_pmasys_outsize_r(void)
 {
-        return 0x001b407c;
+        return 0x001b407cU;
 }
 static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
 {
-        return (v & 0x7ffffff) << 5;
+        return (v & 0x7ffffffU) << 5U;
 }
 static inline u32 perf_pmasys_mem_bytes_r(void)
 {
-        return 0x001b4084;
+        return 0x001b4084U;
 }
 static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 perf_pmasys_mem_bump_r(void)
 {
-        return 0x001b4088;
+        return 0x001b4088U;
 }
 static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
 {
-        return (v & 0xfffffff) << 4;
+        return (v & 0xfffffffU) << 4U;
 }
 static inline u32 perf_pmasys_enginestatus_r(void)
 {
-        return 0x001b40a4;
+        return 0x001b40a4U;
 }
 static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
index 02c9b67f..aef0e693 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
@@ -58,6 +58,6 @@
 
 static inline u32 pram_data032_r(u32 i)
 {
-        return 0x00700000 + i*4;
+        return 0x00700000U + i*4U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
index 13e875cc..03a3854e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
@@ -58,110 +58,110 @@
 
 static inline u32 pri_ringmaster_command_r(void)
 {
-        return 0x0012004c;
+        return 0x0012004cU;
 }
 static inline u32 pri_ringmaster_command_cmd_m(void)
 {
-        return 0x3f << 0;
+        return 0x3fU << 0U;
 }
 static inline u32 pri_ringmaster_command_cmd_v(u32 r)
 {
-        return (r >> 0) & 0x3f;
+        return (r >> 0U) & 0x3fU;
 }
 static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pri_ringmaster_command_data_r(void)
 {
-        return 0x00120048;
+        return 0x00120048U;
 }
 static inline u32 pri_ringmaster_start_results_r(void)
 {
-        return 0x00120050;
+        return 0x00120050U;
 }
 static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 pri_ringmaster_intr_status0_r(void)
 {
-        return 0x00120058;
+        return 0x00120058U;
 }
 static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
 {
-        return (r >> 8) & 0x1;
+        return (r >> 8U) & 0x1U;
 }
 static inline u32 pri_ringmaster_intr_status1_r(void)
 {
-        return 0x0012005c;
+        return 0x0012005cU;
 }
 static inline u32 pri_ringmaster_global_ctl_r(void)
 {
-        return 0x00120060;
+        return 0x00120060U;
 }
 static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pri_ringmaster_enum_fbp_r(void)
 {
-        return 0x00120074;
+        return 0x00120074U;
 }
 static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 pri_ringmaster_enum_gpc_r(void)
 {
-        return 0x00120078;
+        return 0x00120078U;
 }
 static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 pri_ringmaster_enum_ltc_r(void)
 {
-        return 0x0012006c;
+        return 0x0012006cU;
 }
 static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
index 47f31f81..1bd5a0f7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -58,22 +58,22 @@
 
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
-        return 0x00128300 + i*4;
+        return 0x00128300U + i*4U;
 }
 static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
 {
-        return 0x00128120;
+        return 0x00128120U;
 }
 static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
 {
-        return 0x00128124;
+        return 0x00128124U;
 }
 static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
 {
-        return 0x00128128;
+        return 0x00128128U;
 }
 static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
 {
-        return 0x0012812c;
+        return 0x0012812cU;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
index 90b9d010..c4d9ef1b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -58,34 +58,34 @@
 
 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {
-        return 0x00122300 + i*4;
+        return 0x00122300U + i*4U;
 }
 static inline u32 pri_ringstation_sys_decode_config_r(void)
 {
-        return 0x00122204;
+        return 0x00122204U;
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
 {
-        return 0x7 << 0;
+        return 0x7U << 0U;
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
 {
-        return 0x00122120;
+        return 0x00122120U;
 }
 static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
 {
-        return 0x00122124;
+        return 0x00122124U;
 }
 static inline u32 pri_ringstation_sys_priv_error_info_r(void)
 {
-        return 0x00122128;
+        return 0x00122128U;
 }
 static inline u32 pri_ringstation_sys_priv_error_code_r(void)
 {
-        return 0x0012212c;
+        return 0x0012212cU;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
index 5ba3c25e..f5d60beb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
@@ -58,118 +58,118 @@
 
 static inline u32 proj_gpc_base_v(void)
 {
-        return 0x00500000;
+        return 0x00500000U;
 }
 static inline u32 proj_gpc_shared_base_v(void)
 {
-        return 0x00418000;
+        return 0x00418000U;
 }
 static inline u32 proj_gpc_stride_v(void)
 {
-        return 0x00008000;
+        return 0x00008000U;
 }
 static inline u32 proj_ltc_stride_v(void)
 {
-        return 0x00002000;
+        return 0x00002000U;
 }
 static inline u32 proj_lts_stride_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 proj_fbpa_base_v(void)
 {
-        return 0x00900000;
+        return 0x00900000U;
 }
 static inline u32 proj_fbpa_shared_base_v(void)
 {
-        return 0x009a0000;
+        return 0x009a0000U;
 }
 static inline u32 proj_fbpa_stride_v(void)
 {
-        return 0x00004000;
+        return 0x00004000U;
 }
 static inline u32 proj_ppc_in_gpc_base_v(void)
 {
-        return 0x00003000;
+        return 0x00003000U;
 }
 static inline u32 proj_ppc_in_gpc_shared_base_v(void)
 {
-        return 0x00003e00;
+        return 0x00003e00U;
 }
 static inline u32 proj_ppc_in_gpc_stride_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 proj_rop_base_v(void)
 {
-        return 0x00410000;
+        return 0x00410000U;
 }
 static inline u32 proj_rop_shared_base_v(void)
 {
-        return 0x00408800;
+        return 0x00408800U;
 }
 static inline u32 proj_rop_stride_v(void)
 {
-        return 0x00000400;
+        return 0x00000400U;
 }
 static inline u32 proj_tpc_in_gpc_base_v(void)
 {
-        return 0x00004000;
+        return 0x00004000U;
 }
 static inline u32 proj_tpc_in_gpc_stride_v(void)
 {
-        return 0x00000800;
+        return 0x00000800U;
 }
 static inline u32 proj_tpc_in_gpc_shared_base_v(void)
 {
-        return 0x00001800;
+        return 0x00001800U;
 }
 static inline u32 proj_host_num_engines_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 proj_host_num_pbdma_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_fbps_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_fbpas_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_gpcs_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 proj_scal_litter_num_zcull_banks_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 proj_scal_max_gpcs_v(void)
 {
-        return 0x00000020;
+        return 0x00000020U;
 }
 static inline u32 proj_scal_max_tpc_per_gpc_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
index c47a5de6..73a5c45c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -58,774 +58,774 @@
 
 static inline u32 pwr_falcon_irqsset_r(void)
 {
-        return 0x0010a000;
+        return 0x0010a000U;
 }
 static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 pwr_falcon_irqsclr_r(void)
 {
-        return 0x0010a004;
+        return 0x0010a004U;
 }
 static inline u32 pwr_falcon_irqstat_r(void)
 {
-        return 0x0010a008;
+        return 0x0010a008U;
 }
 static inline u32 pwr_falcon_irqstat_halt_true_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
 {
-        return 0x40;
+        return 0x40U;
 }
 static inline u32 pwr_falcon_irqmode_r(void)
 {
-        return 0x0010a00c;
+        return 0x0010a00cU;
 }
 static inline u32 pwr_falcon_irqmset_r(void)
 {
-        return 0x0010a010;
+        return 0x0010a010U;
 }
 static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
 {
-        return (v & 0x1) << 3;
+        return (v & 0x1U) << 3U;
 }
 static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
 {
-        return (v & 0x1) << 6;
+        return (v & 0x1U) << 6U;
 }
 static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
 {
-        return (v & 0x1) << 7;
+        return (v & 0x1U) << 7U;
 }
 static inline u32 pwr_falcon_irqmclr_r(void)
 {
-        return 0x0010a014;
+        return 0x0010a014U;
 }
 static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
 {
-        return (v & 0x1) << 3;
+        return (v & 0x1U) << 3U;
 }
 static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
 {
-        return (v & 0x1) << 6;
+        return (v & 0x1U) << 6U;
 }
 static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
 {
-        return (v & 0x1) << 7;
+        return (v & 0x1U) << 7U;
 }
 static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 pwr_falcon_irqmask_r(void)
 {
-        return 0x0010a018;
+        return 0x0010a018U;
 }
 static inline u32 pwr_falcon_irqdest_r(void)
 {
-        return 0x0010a01c;
+        return 0x0010a01cU;
 }
 static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
 {
-        return (v & 0x1) << 3;
+        return (v & 0x1U) << 3U;
 }
 static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
 {
-        return (v & 0x1) << 6;
+        return (v & 0x1U) << 6U;
 }
 static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
 {
-        return (v & 0x1) << 7;
+        return (v & 0x1U) << 7U;
 }
 static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
 {
-        return (v & 0x1) << 16;
+        return (v & 0x1U) << 16U;
 }
 static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
 {
-        return (v & 0x1) << 17;
+        return (v & 0x1U) << 17U;
 }
 static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
 {
-        return (v & 0x1) << 18;
+        return (v & 0x1U) << 18U;
 }
 static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
 {
-        return (v & 0x1) << 19;
+        return (v & 0x1U) << 19U;
 }
 static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
 {
-        return (v & 0x1) << 20;
+        return (v & 0x1U) << 20U;
 }
 static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
 {
-        return (v & 0x1) << 21;
+        return (v & 0x1U) << 21U;
 }
 static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
 {
-        return (v & 0x1) << 22;
+        return (v & 0x1U) << 22U;
 }
 static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
 {
-        return (v & 0x1) << 23;
+        return (v & 0x1U) << 23U;
 }
 static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
 {
-        return (v & 0xff) << 24;
+        return (v & 0xffU) << 24U;
 }
 static inline u32 pwr_falcon_curctx_r(void)
 {
-        return 0x0010a050;
+        return 0x0010a050U;
 }
 static inline u32 pwr_falcon_nxtctx_r(void)
 {
-        return 0x0010a054;
+        return 0x0010a054U;
 }
 static inline u32 pwr_falcon_mailbox0_r(void)
 {
-        return 0x0010a040;
+        return 0x0010a040U;
 }
 static inline u32 pwr_falcon_mailbox1_r(void)
 {
-        return 0x0010a044;
+        return 0x0010a044U;
 }
 static inline u32 pwr_falcon_itfen_r(void)
 {
-        return 0x0010a048;
+        return 0x0010a048U;
 }
 static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pwr_falcon_idlestate_r(void)
 {
-        return 0x0010a04c;
+        return 0x0010a04cU;
 }
 static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
 {
-        return (r >> 1) & 0x7fff;
+        return (r >> 1U) & 0x7fffU;
 }
 static inline u32 pwr_falcon_os_r(void)
 {
-        return 0x0010a080;
+        return 0x0010a080U;
 }
 static inline u32 pwr_falcon_engctl_r(void)
 {
-        return 0x0010a0a4;
+        return 0x0010a0a4U;
 }
 static inline u32 pwr_falcon_cpuctl_r(void)
 {
-        return 0x0010a100;
+        return 0x0010a100U;
 }
 static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 {
-        return (v & 0x1) << 6;
+        return (v & 0x1U) << 6U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-        return 0x1 << 6;
+        return 0x1U << 6U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
-        return (r >> 6) & 0x1;
+        return (r >> 6U) & 0x1U;
 }
 static inline u32 pwr_falcon_cpuctl_alias_r(void)
 {
-        return 0x0010a130;
+        return 0x0010a130U;
 }
 static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
 {
-        return (v & 0x1) << 1;
+        return (v & 0x1U) << 1U;
 }
 static inline u32 pwr_pmu_scpctl_stat_r(void)
 {
-        return 0x0010ac08;
+        return 0x0010ac08U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
 {
-        return (v & 0x1) << 20;
+        return (v & 0x1U) << 20U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
 {
-        return 0x1 << 20;
+        return 0x1U << 20U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
 {
-        return (r >> 20) & 0x1;
+        return (r >> 20U) & 0x1U;
 }
 static inline u32 pwr_falcon_imemc_r(u32 i)
 {
-        return 0x0010a180 + i*16;
+        return 0x0010a180U + i*16U;
 }
 static inline u32 pwr_falcon_imemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 pwr_falcon_imemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 pwr_falcon_imemd_r(u32 i)
 {
-        return 0x0010a184 + i*16;
+        return 0x0010a184U + i*16U;
 }
 static inline u32 pwr_falcon_imemt_r(u32 i)
 {
-        return 0x0010a188 + i*16;
+        return 0x0010a188U + i*16U;
 }
 static inline u32 pwr_falcon_sctl_r(void)
 {
-        return 0x0010a240;
+        return 0x0010a240U;
 }
 static inline u32 pwr_falcon_mmu_phys_sec_r(void)
 {
-        return 0x00100ce4;
+        return 0x00100ce4U;
 }
 static inline u32 pwr_falcon_bootvec_r(void)
 {
-        return 0x0010a104;
+        return 0x0010a104U;
 }
 static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 pwr_falcon_dmactl_r(void)
 {
-        return 0x0010a10c;
+        return 0x0010a10cU;
 }
 static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
 {
-        return 0x1 << 1;
+        return 0x1U << 1U;
 }
 static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 pwr_falcon_hwcfg_r(void)
 {
-        return 0x0010a108;
+        return 0x0010a108U;
 }
 static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
 {
-        return (r >> 0) & 0x1ff;
+        return (r >> 0U) & 0x1ffU;
 }
 static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
 {
-        return (r >> 9) & 0x1ff;
+        return (r >> 9U) & 0x1ffU;
 }
 static inline u32 pwr_falcon_dmatrfbase_r(void)
 {
-        return 0x0010a110;
+        return 0x0010a110U;
 }
 static inline u32 pwr_falcon_dmatrfbase1_r(void)
 {
-        return 0x0010a128;
+        return 0x0010a128U;
 }
 static inline u32 pwr_falcon_dmatrfmoffs_r(void)
 {
-        return 0x0010a114;
+        return 0x0010a114U;
 }
 static inline u32 pwr_falcon_dmatrfcmd_r(void)
 {
-        return 0x0010a118;
+        return 0x0010a118U;
 }
 static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
 {
-        return (v & 0x7) << 8;
+        return (v & 0x7U) << 8U;
 }
 static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
 {
-        return (v & 0x7) << 12;
+        return (v & 0x7U) << 12U;
 }
 static inline u32 pwr_falcon_dmatrffboffs_r(void)
 {
-        return 0x0010a11c;
+        return 0x0010a11cU;
 }
 static inline u32 pwr_falcon_exterraddr_r(void)
 {
-        return 0x0010a168;
+        return 0x0010a168U;
 }
 static inline u32 pwr_falcon_exterrstat_r(void)
 {
-        return 0x0010a16c;
+        return 0x0010a16cU;
 }
 static inline u32 pwr_falcon_exterrstat_valid_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
 {
-        return 0x0010a200;
+        return 0x0010a200U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
 {
-        return (v & 0xf) << 0;
+        return (v & 0xfU) << 0U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
 {
-        return 0xf << 0;
+        return 0xfU << 0U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
 {
-        return (r >> 0) & 0xf;
+        return (r >> 0U) & 0xfU;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
 {
-        return 0xe;
+        return 0xeU;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
 {
-        return (v & 0x1f) << 8;
+        return (v & 0x1fU) << 8U;
 }
 static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
 {
-        return 0x0010a20c;
+        return 0x0010a20cU;
 }
 static inline u32 pwr_falcon_dmemc_r(u32 i)
 {
-        return 0x0010a1c0 + i*8;
+        return 0x0010a1c0U + i*8U;
 }
 static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
 {
-        return (v & 0x3f) << 2;
+        return (v & 0x3fU) << 2U;
 }
 static inline u32 pwr_falcon_dmemc_offs_m(void)
 {
-        return 0x3f << 2;
+        return 0x3fU << 2U;
 }
 static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 {
-        return (v & 0xff) << 8;
+        return (v & 0xffU) << 8U;
 }
 static inline u32 pwr_falcon_dmemc_blk_m(void)
 {
-        return 0xff << 8;
+        return 0xffU << 8U;
 }
 static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
 {
-        return (v & 0x1) << 25;
+        return (v & 0x1U) << 25U;
 }
 static inline u32 pwr_falcon_dmemd_r(u32 i)
 {
-        return 0x0010a1c4 + i*8;
+        return 0x0010a1c4U + i*8U;
 }
 static inline u32 pwr_pmu_new_instblk_r(void)
 {
-        return 0x0010a480;
+        return 0x0010a480U;
 }
 static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
 {
-        return (v & 0xfffffff) << 0;
+        return (v & 0xfffffffU) << 0U;
 }
 static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
 {
-        return 0x20000000;
+        return 0x20000000U;
 }
 static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
 {
-        return 0x30000000;
+        return 0x30000000U;
 }
 static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
 {
-        return (v & 0x1) << 30;
+        return (v & 0x1U) << 30U;
 }
 static inline u32 pwr_pmu_mutex_id_r(void)
 {
-        return 0x0010a488;
+        return 0x0010a488U;
 }
 static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 pwr_pmu_mutex_id_value_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
 {
-        return 0x000000ff;
+        return 0x000000ffU;
 }
 static inline u32 pwr_pmu_mutex_id_release_r(void)
 {
-        return 0x0010a48c;
+        return 0x0010a48cU;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_m(void)
 {
-        return 0xff << 0;
+        return 0xffU << 0U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_pmu_mutex_r(u32 i)
 {
-        return 0x0010a580 + i*4;
+        return 0x0010a580U + i*4U;
 }
 static inline u32 pwr_pmu_mutex__size_1_v(void)
 {
-        return 0x00000010;
+        return 0x00000010U;
 }
 static inline u32 pwr_pmu_mutex_value_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 pwr_pmu_mutex_value_v(u32 r)
 {
-        return (r >> 0) & 0xff;
+        return (r >> 0U) & 0xffU;
 }
 static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_pmu_queue_head_r(u32 i)
 {
-        return 0x0010a4a0 + i*4;
+        return 0x0010a4a0U + i*4U;
 }
 static inline u32 pwr_pmu_queue_head__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 pwr_pmu_queue_head_address_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 pwr_pmu_queue_head_address_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 pwr_pmu_queue_tail_r(u32 i)
 {
-        return 0x0010a4b0 + i*4;
+        return 0x0010a4b0U + i*4U;
 }
 static inline u32 pwr_pmu_queue_tail__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 pwr_pmu_msgq_head_r(void)
 {
-        return 0x0010a4c8;
+        return 0x0010a4c8U;
 }
 static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 pwr_pmu_msgq_tail_r(void)
 {
-        return 0x0010a4cc;
+        return 0x0010a4ccU;
 }
 static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
 {
-        return (r >> 0) & 0xffffffff;
+        return (r >> 0U) & 0xffffffffU;
 }
 static inline u32 pwr_pmu_idle_mask_r(u32 i)
 {
-        return 0x0010a504 + i*16;
+        return 0x0010a504U + i*16U;
 }
 static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
 {
-        return 0x200000;
+        return 0x200000U;
 }
 static inline u32 pwr_pmu_idle_count_r(u32 i)
 {
-        return 0x0010a508 + i*16;
+        return 0x0010a508U + i*16U;
 }
 static inline u32 pwr_pmu_idle_count_value_f(u32 v)
 {
-        return (v & 0x7fffffff) << 0;
+        return (v & 0x7fffffffU) << 0U;
 }
 static inline u32 pwr_pmu_idle_count_value_v(u32 r)
 {
-        return (r >> 0) & 0x7fffffff;
+        return (r >> 0U) & 0x7fffffffU;
 }
 static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
 {
-        return 0x0010a50c + i*16;
+        return 0x0010a50cU + i*16U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_m(void)
 {
-        return 0x3 << 0;
+        return 0x3U << 0U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
-        return 0x0010a9f0 + i*8;
+        return 0x0010a9f0U + i*8U;
 }
 static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
 {
-        return 0x0010a9f4 + i*8;
+        return 0x0010a9f4U + i*8U;
 }
 static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
 {
-        return 0x0010aa30 + i*8;
+        return 0x0010aa30U + i*8U;
 }
 static inline u32 pwr_pmu_debug_r(u32 i)
 {
-        return 0x0010a5c0 + i*4;
+        return 0x0010a5c0U + i*4U;
 }
 static inline u32 pwr_pmu_debug__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000004U;
 }
 static inline u32 pwr_pmu_mailbox_r(u32 i)
 {
-        return 0x0010a450 + i*4;
+        return 0x0010a450U + i*4U;
 }
 static inline u32 pwr_pmu_mailbox__size_1_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 pwr_pmu_bar0_addr_r(void)
 {
-        return 0x0010a7a0;
+        return 0x0010a7a0U;
 }
 static inline u32 pwr_pmu_bar0_data_r(void)
 {
-        return 0x0010a7a4;
+        return 0x0010a7a4U;
 }
 static inline u32 pwr_pmu_bar0_ctl_r(void)
 {
-        return 0x0010a7ac;
+        return 0x0010a7acU;
 }
 static inline u32 pwr_pmu_bar0_timeout_r(void)
 {
-        return 0x0010a7a8;
+        return 0x0010a7a8U;
 }
 static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
-        return 0x0010a988;
+        return 0x0010a988U;
 }
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
-        return 0x0010a7b0;
+        return 0x0010a7b0U;
 }
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
-        return 0x0010a6c0 + i*4;
+        return 0x0010a6c0U + i*4U;
 }
 static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
 {
-        return 0x0010a6e8 + i*4;
+        return 0x0010a6e8U + i*4U;
 }
 static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
 {
-        return 0x0010a710 + i*4;
+        return 0x0010a710U + i*4U;
 }
 static inline u32 pwr_pmu_pg_intren_r(u32 i)
 {
-        return 0x0010a760 + i*4;
+        return 0x0010a760U + i*4U;
 }
 static inline u32 pwr_fbif_transcfg_r(u32 i)
 {
-        return 0x0010ae00 + i*4;
+        return 0x0010ae00U + i*4U;
 }
 static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
 {
-        return (v & 0x1) << 2;
+        return (v & 0x1U) << 2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_m(void)
 {
-        return 0x1 << 2;
+        return 0x1U << 2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
index a2644cf4..a94fc0a2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
@@ -58,442 +58,442 @@
 
 static inline u32 ram_in_ramfc_s(void)
 {
-        return 4096;
+        return 4096U;
 }
 static inline u32 ram_in_ramfc_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 ram_in_page_dir_base_target_f(u32 v)
 {
-        return (v & 0x3) << 0;
+        return (v & 0x3U) << 0U;
 }
 static inline u32 ram_in_page_dir_base_target_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
 {
-        return 0x3;
+        return 0x3U;
 }
 static inline u32 ram_in_page_dir_base_vol_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_page_dir_base_vol_true_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
 {
-        return (v & 0x1) << 4;
+        return (v & 0x1U) << 4U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
 {
-        return 0x1 << 4;
+        return 0x1U << 4U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
 {
-        return (v & 0x1) << 5;
+        return (v & 0x1U) << 5U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
 {
-        return 0x1 << 5;
+        return 0x1U << 5U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 ram_in_big_page_size_f(u32 v)
 {
-        return (v & 0x1) << 11;
+        return (v & 0x1U) << 11U;
 }
 static inline u32 ram_in_big_page_size_m(void)
 {
-        return 0x1 << 11;
+        return 0x1U << 11U;
 }
 static inline u32 ram_in_big_page_size_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_big_page_size_128kb_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_in_big_page_size_64kb_f(void)
 {
-        return 0x800;
+        return 0x800U;
 }
 static inline u32 ram_in_page_dir_base_lo_f(u32 v)
 {
-        return (v & 0xfffff) << 12;
+        return (v & 0xfffffU) << 12U;
 }
 static inline u32 ram_in_page_dir_base_lo_w(void)
 {
-        return 128;
+        return 128U;
 }
 static inline u32 ram_in_page_dir_base_hi_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 ram_in_page_dir_base_hi_w(void)
 {
-        return 129;
+        return 129U;
 }
 static inline u32 ram_in_adr_limit_lo_f(u32 v)
 {
-        return (v & 0xfffff) << 12;
+        return (v & 0xfffffU) << 12U;
 }
 static inline u32 ram_in_adr_limit_lo_w(void)
 {
-        return 130;
+        return 130U;
 }
 static inline u32 ram_in_adr_limit_hi_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xffffffffU) << 0U;
 }
 static inline u32 ram_in_adr_limit_hi_w(void)
 {
-        return 131;
+        return 131U;
 }
 static inline u32 ram_in_engine_cs_w(void)
 {
-        return 132;
+        return 132U;
 }
 static inline u32 ram_in_engine_cs_wfi_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ram_in_engine_cs_wfi_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_in_engine_cs_fg_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ram_in_engine_cs_fg_f(void)
 {
-        return 0x8;
+        return 0x8U;
 }
 static inline u32 ram_in_gr_cs_w(void)
 {
-        return 132;
+        return 132U;
 }
 static inline u32 ram_in_gr_cs_wfi_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_in_gr_wfi_target_w(void)
 {
-        return 132;
+        return 132U;
 }
 static inline u32 ram_in_gr_wfi_mode_w(void)
 {
-        return 132;
+        return 132U;
 }
 static inline u32 ram_in_gr_wfi_mode_physical_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 ram_in_gr_wfi_mode_physical_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
 {
-        return (v & 0xfffff) << 12;
+        return (v & 0xfffffU) << 12U;
 }
 static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
 {
-        return 132;
+        return 132U;
 }
 static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0xffU) << 0U;
 }
 static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
 {
-        return 133;
+        return 133U;
 }
 static inline u32 ram_in_base_shift_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 ram_in_alloc_size_v(void)
 {
-        return 0x00001000;
+        return 0x00001000U;
 }
 static inline u32 ram_fc_size_val_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 ram_fc_gp_put_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 ram_fc_userd_w(void)
 {
-        return 2;
+        return 2U;
 }
 static inline u32 ram_fc_userd_hi_w(void)
 {
-        return 3;
+        return 3U;
 }
 static inline u32 ram_fc_signature_w(void)
 {
-        return 4;
+        return 4U;
 }
 static inline u32 ram_fc_gp_get_w(void)
 {
-        return 5;
+        return 5U;
 }
 static inline u32 ram_fc_pb_get_w(void)
 {
-        return 6;
+        return 6U;
 }
 static inline u32 ram_fc_pb_get_hi_w(void)
 {
-        return 7;
+        return 7U;
 }
 static inline u32 ram_fc_pb_top_level_get_w(void)
 {
-        return 8;
+        return 8U;
 }
 static inline u32 ram_fc_pb_top_level_get_hi_w(void)
 {
-        return 9;
+        return 9U;
 }
 static inline u32 ram_fc_acquire_w(void)
 {
-        return 12;
+        return 12U;
 }
 static inline u32 ram_fc_semaphorea_w(void)
 {
-        return 14;
+        return 14U;
 }
 static inline u32 ram_fc_semaphoreb_w(void)
 {
-        return 15;
+        return 15U;
 }
 static inline u32 ram_fc_semaphorec_w(void)
 {
-        return 16;
+        return 16U;
 }
 static inline u32 ram_fc_semaphored_w(void)
 {
-        return 17;
+        return 17U;
 }
 static inline u32 ram_fc_gp_base_w(void)
 {
-        return 18;
+        return 18U;
 }
 static inline u32 ram_fc_gp_base_hi_w(void)
 {
-        return 19;
+        return 19U;
 }
 static inline u32 ram_fc_gp_fetch_w(void)
 {
-        return 20;
+        return 20U;
 }
 static inline u32 ram_fc_pb_fetch_w(void)
 {
-        return 21;
+        return 21U;
 }
 static inline u32 ram_fc_pb_fetch_hi_w(void)
 {
-        return 22;
+        return 22U;
 }
 static inline u32 ram_fc_pb_put_w(void)
 {
-        return 23;
+        return 23U;
 }
 static inline u32 ram_fc_pb_put_hi_w(void)
 {
-        return 24;
+        return 24U;
 }
 static inline u32 ram_fc_pb_header_w(void)
 {
-        return 33;
+        return 33U;
 }
 static inline u32 ram_fc_pb_count_w(void)
 {
-        return 34;
+        return 34U;
 }
 static inline u32 ram_fc_subdevice_w(void)
 {
-        return 37;
+        return 37U;
 }
 static inline u32 ram_fc_formats_w(void)
 {
-        return 39;
+        return 39U;
 }
 static inline u32 ram_fc_allowed_syncpoints_w(void)
 {
-        return 58;
+        return 58U;
 }
 static inline u32 ram_fc_syncpointa_w(void)
 {
-        return 41;
+        return 41U;
 }
 static inline u32 ram_fc_syncpointb_w(void)
 {
-        return 42;
+        return 42U;
 }
 static inline u32 ram_fc_target_w(void)
 {
-        return 43;
+        return 43U;
 }
 static inline u32 ram_fc_hce_ctrl_w(void)
 {
-        return 57;
+        return 57U;
 }
 static inline u32 ram_fc_chid_w(void)
 {
-        return 58;
+        return 58U;
 }
 static inline u32 ram_fc_chid_id_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 ram_fc_chid_id_w(void)
 {
-        return 0;
+        return 0U;
 }
 static inline u32 ram_fc_config_w(void)
 {
-        return 61;
+        return 61U;
 }
 static inline u32 ram_fc_runlist_timeslice_w(void)
 {
-        return 62;
+        return 62U;
 }
 static inline u32 ram_userd_base_shift_v(void)
 {
-        return 0x00000009;
+        return 0x00000009U;
 }
 static inline u32 ram_userd_chan_size_v(void)
 {
-        return 0x00000200;
+        return 0x00000200U;
 }
 static inline u32 ram_userd_put_w(void)
 {
-        return 16;
+        return 16U;
 }
 static inline u32 ram_userd_get_w(void)
 {
-        return 17;
+        return 17U;
 }
 static inline u32 ram_userd_ref_w(void)
 {
-        return 18;
+        return 18U;
 }
 static inline u32 ram_userd_put_hi_w(void)
 {
-        return 19;
+        return 19U;
 }
 static inline u32 ram_userd_ref_threshold_w(void)
 {
-        return 20;
+        return 20U;
 }
 static inline u32 ram_userd_top_level_get_w(void)
 {
-        return 22;
+        return 22U;
 }
 static inline u32 ram_userd_top_level_get_hi_w(void)
 {
-        return 23;
+        return 23U;
 }
 static inline u32 ram_userd_get_hi_w(void)
 {
-        return 24;
+        return 24U;
 }
 static inline u32 ram_userd_gp_get_w(void)
 {
-        return 34;
+        return 34U;
 }
 static inline u32 ram_userd_gp_put_w(void)
 {
-        return 35;
+        return 35U;
 }
 static inline u32 ram_userd_gp_top_level_get_w(void)
 {
-        return 22;
+        return 22U;
 }
 static inline u32 ram_userd_gp_top_level_get_hi_w(void)
 {
-        return 23;
+        return 23U;
 }
 static inline u32 ram_rl_entry_size_v(void)
 {
-        return 0x00000008;
+        return 0x00000008U;
 }
 static inline u32 ram_rl_entry_chid_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 ram_rl_entry_id_f(u32 v)
 {
-        return (v & 0xfff) << 0;
+        return (v & 0xfffU) << 0U;
 }
 static inline u32 ram_rl_entry_type_f(u32 v)
 {
-        return (v & 0x1) << 13;
+        return (v & 0x1U) << 13U;
 }
 static inline u32 ram_rl_entry_type_chid_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 ram_rl_entry_type_tsg_f(void)
 {
-        return 0x2000;
+        return 0x2000U;
 }
 static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
 {
-        return (v & 0xf) << 14;
+        return (v & 0xfU) << 14U;
 }
 static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
 {
-        return 0xc000;
+        return 0xc000U;
 }
 static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
 {
-        return (v & 0xff) << 18;
+        return (v & 0xffU) << 18U;
 }
 static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
 {
-        return 0x2000000;
+        return 0x2000000U;
 }
 static inline u32 ram_rl_entry_tsg_length_f(u32 v)
 {
-        return (v & 0x3f) << 26;
+        return (v & 0x3fU) << 26U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
index 51c926b5..49fb7180 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
@@ -58,358 +58,358 @@
 
 static inline u32 therm_use_a_r(void)
 {
-        return 0x00020798;
+        return 0x00020798U;
 }
 static inline u32 therm_use_a_ext_therm_0_enable_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 therm_use_a_ext_therm_1_enable_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 therm_use_a_ext_therm_2_enable_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 therm_evt_ext_therm_0_r(void)
 {
-        return 0x00020700;
+        return 0x00020700U;
 }
 static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
 {
-        return (v & 0x3f) << 24;
+        return (v & 0x3fU) << 24U;
 }
 static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
 {
-        return (v & 0x3) << 30;
+        return (v & 0x3U) << 30U;
 }
 static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 therm_evt_ext_therm_1_r(void)
 {
-        return 0x00020704;
+        return 0x00020704U;
 }
 static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
 {
-        return (v & 0x3f) << 24;
+        return (v & 0x3fU) << 24U;
 }
 static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
 {
-        return (v & 0x3) << 30;
+        return (v & 0x3U) << 30U;
 }
 static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 therm_evt_ext_therm_2_r(void)
 {
-        return 0x00020708;
+        return 0x00020708U;
 }
 static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
 {
-        return (v & 0x3f) << 24;
+        return (v & 0x3fU) << 24U;
 }
 static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
 {
-        return (v & 0x3) << 30;
+        return (v & 0x3U) << 30U;
 }
 static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 therm_weight_1_r(void)
 {
-        return 0x00020024;
+        return 0x00020024U;
 }
 static inline u32 therm_config1_r(void)
 {
-        return 0x00020050;
+        return 0x00020050U;
 }
 static inline u32 therm_config2_r(void)
 {
-        return 0x00020130;
+        return 0x00020130U;
 }
 static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
 {
-        return (v & 0x1) << 24;
+        return (v & 0x1U) << 24U;
 }
 static inline u32 therm_config2_grad_enable_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 therm_gate_ctrl_r(u32 i)
 {
-        return 0x00020200 + i*4;
+        return 0x00020200U + i*4U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_m(void)
 {
-        return 0x3 << 0;
+        return 0x3U << 0U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_m(void)
 {
-        return 0x3 << 2;
+        return 0x3U << 2U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
 {
-        return 0x4;
+        return 0x4U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_m(void)
 {
-        return 0x3 << 4;
+        return 0x3U << 4U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
 {
-        return 0x10;
+        return 0x10U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
 {
-        return 0x20;
+        return 0x20U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
 {
-        return (v & 0x1f) << 8;
+        return (v & 0x1fU) << 8U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
 {
-        return 0x1f << 8;
+        return 0x1fU << 8U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 {
-        return (v & 0x7) << 13;
+        return (v & 0x7U) << 13U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
 {
-        return 0x7 << 13;
+        return 0x7U << 13U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 {
-        return (v & 0xf) << 16;
+        return (v & 0xfU) << 16U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
 {
-        return 0xf << 16;
+        return 0xfU << 16U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 {
-        return (v & 0xf) << 20;
+        return (v & 0xfU) << 20U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
 {
-        return 0xf << 20;
+        return 0xfU << 20U;
 }
 static inline u32 therm_fecs_idle_filter_r(void)
 {
-        return 0x00020288;
+        return 0x00020288U;
 }
 static inline u32 therm_fecs_idle_filter_value_m(void)
 {
-        return 0xffffffff << 0;
+        return 0xffffffffU << 0U;
 }
 static inline u32 therm_hubmmu_idle_filter_r(void)
 {
-        return 0x0002028c;
+        return 0x0002028cU;
 }
 static inline u32 therm_hubmmu_idle_filter_value_m(void)
 {
-        return 0xffffffff << 0;
+        return 0xffffffffU << 0U;
 }
 static inline u32 therm_clk_slowdown_r(u32 i)
 {
-        return 0x00020160 + i*4;
+        return 0x00020160U + i*4U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
 {
-        return (v & 0x3f) << 16;
+        return (v & 0x3fU) << 16U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_m(void)
 {
-        return 0x3f << 16;
+        return 0x3fU << 16U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
 {
-        return (r >> 16) & 0x3f;
+        return (r >> 16U) & 0x3fU;
 }
 static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 therm_grad_stepping_table_r(u32 i)
 {
-        return 0x000202c8 + i*4;
+        return 0x000202c8U + i*4U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
 {
-        return (v & 0x3f) << 0;
+        return (v & 0x3fU) << 0U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
 {
-        return 0x3f << 0;
+        return 0x3fU << 0U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
 {
-        return 0x2;
+        return 0x2U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
 {
-        return 0x6;
+        return 0x6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
 {
-        return 0xe;
+        return 0xeU;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
 {
-        return (v & 0x3f) << 6;
+        return (v & 0x3fU) << 6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
 {
-        return 0x3f << 6;
+        return 0x3fU << 6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 {
-        return (v & 0x3f) << 12;
+        return (v & 0x3fU) << 12U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
 {
-        return 0x3f << 12;
+        return 0x3fU << 12U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 {
-        return (v & 0x3f) << 18;
+        return (v & 0x3fU) << 18U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
 {
-        return 0x3f << 18;
+        return 0x3fU << 18U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 {
-        return (v & 0x3f) << 24;
+        return (v & 0x3fU) << 24U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
 {
-        return 0x3f << 24;
+        return 0x3fU << 24U;
 }
 static inline u32 therm_grad_stepping0_r(void)
 {
-        return 0x000202c0;
+        return 0x000202c0U;
 }
 static inline u32 therm_grad_stepping0_feature_s(void)
 {
-        return 1;
+        return 1U;
 }
 static inline u32 therm_grad_stepping0_feature_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1U) << 0U;
 }
 static inline u32 therm_grad_stepping0_feature_m(void)
 {
-        return 0x1 << 0;
+        return 0x1U << 0U;
 }
 static inline u32 therm_grad_stepping0_feature_v(u32 r)
 {
-        return (r >> 0) & 0x1;
+        return (r >> 0U) & 0x1U;
 }
 static inline u32 therm_grad_stepping0_feature_enable_f(void)
 {
-        return 0x1;
+        return 0x1U;
 }
 static inline u32 therm_grad_stepping1_r(void)
 {
-        return 0x000202c4;
+        return 0x000202c4U;
 }
 static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
 {
-        return (v & 0x1ffff) << 0;
+        return (v & 0x1ffffU) << 0U;
 }
 static inline u32 therm_clk_timing_r(u32 i)
 {
-        return 0x000203c0 + i*4;
+        return 0x000203c0U + i*4U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
 {
-        return (v & 0x1) << 16;
+        return (v & 0x1U) << 16U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_m(void)
 {
-        return 0x1 << 16;
+        return 0x1U << 16U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
 {
-        return 0x10000;
+        return 0x10000U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
index dd73eba1..db752648 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
@@ -58,58 +58,58 @@
 
 static inline u32 timer_pri_timeout_r(void)
 {
-        return 0x00009080;
+        return 0x00009080U;
 }
 static inline u32 timer_pri_timeout_period_f(u32 v)
 {
-        return (v & 0xffffff) << 0;
+        return (v & 0xffffffU) << 0U;
 }
 static inline u32 timer_pri_timeout_period_m(void)
 {
-        return 0xffffff << 0;
+        return 0xffffffU << 0U;
 }
 static inline u32 timer_pri_timeout_period_v(u32 r)
 {
-        return (r >> 0) & 0xffffff;
+        return (r >> 0U) & 0xffffffU;
 }
 static inline u32 timer_pri_timeout_en_f(u32 v)
 {
-        return (v & 0x1) << 31;
+        return (v & 0x1U) << 31U;
 }
 static inline u32 timer_pri_timeout_en_m(void)
 {
-        return 0x1 << 31;
+        return 0x1U << 31U;
 }
 static inline u32 timer_pri_timeout_en_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 timer_pri_timeout_en_en_enabled_f(void)
 {
-        return 0x80000000;
+        return 0x80000000U;
 }
 static inline u32 timer_pri_timeout_en_en_disabled_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 timer_pri_timeout_save_0_r(void)
 {
-        return 0x00009084;
+        return 0x00009084U;
 }
 static inline u32 timer_pri_timeout_save_1_r(void)
 {
-        return 0x00009088;
+        return 0x00009088U;
 }
 static inline u32 timer_pri_timeout_fecs_errcode_r(void)
 {
-        return 0x0000908c;
+        return 0x0000908cU;
 }
 static inline u32 timer_time_0_r(void)
 {
-        return 0x00009400;
+        return 0x00009400U;
 }
 static inline u32 timer_time_1_r(void)
 {
-        return 0x00009410;
+        return 0x00009410U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
index 0bd55037..8d336077 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
@@ -58,174 +58,174 @@
 
 static inline u32 top_num_gpcs_r(void)
 {
-        return 0x00022430;
+        return 0x00022430U;
 }
 static inline u32 top_num_gpcs_value_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 top_tpc_per_gpc_r(void)
 {
-        return 0x00022434;
+        return 0x00022434U;
 }
 static inline u32 top_tpc_per_gpc_value_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 top_num_fbps_r(void)
 {
-        return 0x00022438;
+        return 0x00022438U;
 }
 static inline u32 top_num_fbps_value_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 top_ltc_per_fbp_r(void)
 {
-        return 0x00022450;
+        return 0x00022450U;
 }
 static inline u32 top_ltc_per_fbp_value_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 top_slices_per_ltc_r(void)
 {
-        return 0x0002245c;
+        return 0x0002245cU;
 }
 static inline u32 top_slices_per_ltc_value_v(u32 r)
 {
-        return (r >> 0) & 0x1f;
+        return (r >> 0U) & 0x1fU;
 }
 static inline u32 top_num_ltcs_r(void)
 {
-        return 0x00022454;
+        return 0x00022454U;
 }
 static inline u32 top_device_info_r(u32 i)
 {
-        return 0x00022700 + i*4;
+        return 0x00022700U + i*4U;
 }
 static inline u32 top_device_info__size_1_v(void)
 {
-        return 0x00000040;
+        return 0x00000040U;
 }
 static inline u32 top_device_info_chain_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 top_device_info_chain_enable_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 top_device_info_engine_enum_v(u32 r)
 {
-        return (r >> 26) & 0xf;
+        return (r >> 26U) & 0xfU;
 }
 static inline u32 top_device_info_runlist_enum_v(u32 r)
 {
-        return (r >> 21) & 0xf;
+        return (r >> 21U) & 0xfU;
 }
 static inline u32 top_device_info_intr_enum_v(u32 r)
 {
-        return (r >> 15) & 0x1f;
+        return (r >> 15U) & 0x1fU;
 }
 static inline u32 top_device_info_reset_enum_v(u32 r)
 {
-        return (r >> 9) & 0x1f;
+        return (r >> 9U) & 0x1fU;
 }
 static inline u32 top_device_info_type_enum_v(u32 r)
 {
-        return (r >> 2) & 0x1fffffff;
+        return (r >> 2U) & 0x1fffffffU;
 }
 static inline u32 top_device_info_type_enum_graphics_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 top_device_info_type_enum_graphics_f(void)
 {
-        return 0x0;
+        return 0x0U;
 }
 static inline u32 top_device_info_type_enum_copy2_v(void)
 {
-        return 0x00000003;
+        return 0x00000003U;
 }
 static inline u32 top_device_info_type_enum_copy2_f(void)
 {
-        return 0xc;
+        return 0xcU;
 }
 static inline u32 top_device_info_type_enum_lce_v(void)
 {
-        return 0x00000013;
+        return 0x00000013U;
 }
 static inline u32 top_device_info_type_enum_lce_f(void)
 {
-        return 0x4c;
+        return 0x4cU;
 }
 static inline u32 top_device_info_engine_v(u32 r)
 {
-        return (r >> 5) & 0x1;
+        return (r >> 5U) & 0x1U;
 }
 static inline u32 top_device_info_runlist_v(u32 r)
 {
-        return (r >> 4) & 0x1;
+        return (r >> 4U) & 0x1U;
 }
 static inline u32 top_device_info_intr_v(u32 r)
 {
-        return (r >> 3) & 0x1;
+        return (r >> 3U) & 0x1U;
 }
 static inline u32 top_device_info_reset_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 top_device_info_entry_v(u32 r)
 {
-        return (r >> 0) & 0x3;
+        return (r >> 0U) & 0x3U;
 }
 static inline u32 top_device_info_entry_not_valid_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 top_device_info_entry_enum_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 top_device_info_entry_engine_type_v(void)
 {
-        return 0x00000002;
+        return 0x00000002U;
 }
 static inline u32 top_device_info_entry_data_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 static inline u32 top_device_info_data_type_v(u32 r)
 {
-        return (r >> 30) & 0x1;
+        return (r >> 30U) & 0x1U;
 }
 static inline u32 top_device_info_data_type_enum2_v(void)
 {
-        return 0x00000000;
+        return 0x00000000U;
 }
 static inline u32 top_device_info_data_inst_id_v(u32 r)
 {
-        return (r >> 26) & 0xf;
+        return (r >> 26U) & 0xfU;
 }
 static inline u32 top_device_info_data_pri_base_v(u32 r)
 {
-        return (r >> 12) & 0xfff;
+        return (r >> 12U) & 0xfffU;
 }
 static inline u32 top_device_info_data_pri_base_align_v(void)
 {
-        return 0x0000000c;
+        return 0x0000000cU;
 }
 static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
 {
-        return (r >> 3) & 0x1f;
+        return (r >> 3U) & 0x1fU;
 }
 static inline u32 top_device_info_data_fault_id_v(u32 r)
 {
-        return (r >> 2) & 0x1;
+        return (r >> 2U) & 0x1U;
 }
 static inline u32 top_device_info_data_fault_id_valid_v(void)
 {
-        return 0x00000001;
+        return 0x00000001U;
 }
 #endif