gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs

TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using
combination of timeslice and interleave levels to decide the priority

Hence remove the IOCTLs and all corresponding APIs

Jira NVGPU-393

Change-Id: I7cf0785689269536eca0c278c774b0e9e74f8c2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598581
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

17 files changed, 0 insertions, 149 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 6feb6fb7..31651795 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -1314,21 +1314,6 @@ long gk20a_channel_ioctl(struct file *filp,
                 ((struct nvgpu_get_param_args *)buf)->value =
                         ch->has_timedout;
                 break;
-        case NVGPU_IOCTL_CHANNEL_SET_PRIORITY:
-                err = gk20a_busy(ch->g);
-                if (err) {
-                        dev_err(dev,
-                                "%s: failed to host gk20a for ioctl cmd: 0x%x",
-                                __func__, cmd);
-                        break;
-                }
-                err = ch->g->ops.fifo.channel_set_priority(ch,
-                        ((struct nvgpu_set_priority_args *)buf)->priority);
-
-                gk20a_idle(ch->g);
-                gk20a_channel_trace_sched_param(
-                        trace_gk20a_channel_set_priority, ch);
-                break;
         case NVGPU_IOCTL_CHANNEL_ENABLE:
                 err = gk20a_busy(ch->g);
                 if (err) {
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
index eb223382..b17d7e74 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
@@ -296,33 +296,6 @@ int nvgpu_ioctl_tsg_dev_release(struct inode *inode, struct file *filp)
         return 0;
 }
 
-static int gk20a_tsg_ioctl_set_priority(struct gk20a *g,
-        struct tsg_gk20a *tsg, struct nvgpu_set_priority_args *arg)
-{
-        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-        struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
-        int err;
-
-        nvgpu_mutex_acquire(&sched->control_lock);
-        if (sched->control_locked) {
-                err = -EPERM;
-                goto done;
-        }
-
-        err = gk20a_busy(g);
-        if (err) {
-                nvgpu_err(g, "failed to power on gpu");
-                goto done;
-        }
-
-        err = gk20a_tsg_set_priority(g, tsg, arg->priority);
-
-        gk20a_idle(g);
-done:
-        nvgpu_mutex_release(&sched->control_lock);
-        return err;
-}
-
 static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
         struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg)
 {
@@ -475,13 +448,6 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
                 break;
                 }
 
-        case NVGPU_IOCTL_TSG_SET_PRIORITY:
-                {
-                err = gk20a_tsg_ioctl_set_priority(g, tsg,
-                        (struct nvgpu_set_priority_args *)buf);
-                break;
-                }
-
         case NVGPU_IOCTL_TSG_EVENT_ID_CTRL:
                 {
                 err = gk20a_tsg_event_id_ctrl(g, tsg,
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index 86dc46c5..db87c4c4 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -262,7 +262,6 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
                         gk20a_ce_create_context(g,
                                 gk20a_fifo_get_fast_ce_runlist_id(g),
                                 -1,
-                                -1,
                                 -1);
 
                 if (g->mm.vidmem.ce_ctx_id == (u32)~0)
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 04ee84f4..99c518b5 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -427,7 +427,6 @@ void gk20a_ce_suspend(struct gk20a *g)
 /* CE app utility functions */
 u32 gk20a_ce_create_context(struct gk20a *g,
                 int runlist_id,
-                int priority,
                 int timeslice,
                 int runlist_level)
 {
@@ -507,16 +506,6 @@ u32 gk20a_ce_create_context(struct gk20a *g,
 
         memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size);
 
-        /* -1 means default channel priority */
-        if (priority != -1) {
-                err = gk20a_fifo_set_priority(ce_ctx->ch, priority);
-                if (err) {
-                        nvgpu_err(g,
-                                "ce: could not set the channel priority for CE context");
-                        goto end;
-                }
-        }
-
         /* -1 means default channel timeslice value */
         if (timeslice != -1) {
                 err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice);
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
index 5c3a1cfc..1d9d8c72 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -128,7 +128,6 @@ void gk20a_ce_destroy(struct gk20a *g);
 /* CE app utility functions */
 u32 gk20a_ce_create_context(struct gk20a *g,
                 int runlist_id,
-                int priority,
                 int timeslice,
                 int runlist_level);
 int gk20a_ce_execute_ops(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 1ea7d6b3..648a8c86 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3962,32 +3962,6 @@ int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
         return channel_gk20a_set_schedule_params(ch);
 }
 
-int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority)
-{
-        if (gk20a_is_channel_marked_as_tsg(ch)) {
-                nvgpu_err(ch->g, "invalid operation for TSG!");
-                return -EINVAL;
-        }
-
-        /* set priority of graphics channel */
-        switch (priority) {
-        case NVGPU_PRIORITY_LOW:
-                ch->timeslice_us = ch->g->timeslice_low_priority_us;
-                break;
-        case NVGPU_PRIORITY_MEDIUM:
-                ch->timeslice_us = ch->g->timeslice_medium_priority_us;
-                break;
-        case NVGPU_PRIORITY_HIGH:
-                ch->timeslice_us = ch->g->timeslice_high_priority_us;
-                break;
-        default:
-                pr_err("Unsupported priority");
-                return -EINVAL;
-        }
-
-        return channel_gk20a_set_schedule_params(ch);
-}
-
 void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c)
 {
         struct gk20a *g = c->g;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index fa1d9f72..3587ffa8 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -383,7 +383,6 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id,
 int gk20a_fifo_setup_ramfc(struct channel_gk20a *c,
                         u64 gpfifo_base, u32 gpfifo_entries,
                         unsigned long timeout, u32 flags);
-int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority);
 int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice);
 void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c);
 int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fb12d0d2..3381d974 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -513,7 +513,6 @@ struct gpu_ops {
                 int (*wait_engine_idle)(struct gk20a *g);
                 u32 (*get_num_fifos)(struct gk20a *g);
                 u32 (*get_pbdma_signature)(struct gk20a *g);
-                int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority);
                 int (*set_runlist_interleave)(struct gk20a *g, u32 id,
                                         bool is_tsg, u32 runlist_id,
                                         u32 new_level);
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 5af01a05..636ee8a0 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -200,29 +200,6 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid)
         return 0;
 }
 
-int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
-                                u32 priority)
-{
-        u32 timeslice_us;
-
-        switch (priority) {
-        case NVGPU_PRIORITY_LOW:
-                timeslice_us = g->timeslice_low_priority_us;
-                break;
-        case NVGPU_PRIORITY_MEDIUM:
-                timeslice_us = g->timeslice_medium_priority_us;
-                break;
-        case NVGPU_PRIORITY_HIGH:
-                timeslice_us = g->timeslice_high_priority_us;
-                break;
-        default:
-                pr_err("Unsupported priority");
-                return -EINVAL;
-        }
-
-        return gk20a_tsg_set_timeslice(tsg, timeslice_us);
-}
-
 int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
 {
         struct gk20a *g = tsg->g;
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 42df76c9..227b6b6c 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -385,7 +385,6 @@ static const struct gpu_ops gm20b_ops = {
                 .alloc_inst = gk20a_fifo_alloc_inst,
                 .free_inst = gk20a_fifo_free_inst,
                 .setup_ramfc = gk20a_fifo_setup_ramfc,
-                .channel_set_priority = gk20a_fifo_set_priority,
                 .channel_set_timeslice = gk20a_fifo_set_timeslice,
                 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 09c82af8..e9ee77fc 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -440,7 +440,6 @@ static const struct gpu_ops gp106_ops = {
                 .alloc_inst = gk20a_fifo_alloc_inst,
                 .free_inst = gk20a_fifo_free_inst,
                 .setup_ramfc = channel_gp10b_setup_ramfc,
-                .channel_set_priority = gk20a_fifo_set_priority,
                 .channel_set_timeslice = gk20a_fifo_set_timeslice,
                 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index d0aedd1b..9b3d1a2c 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -408,7 +408,6 @@ static const struct gpu_ops gp10b_ops = {
                 .alloc_inst = gk20a_fifo_alloc_inst,
                 .free_inst = gk20a_fifo_free_inst,
                 .setup_ramfc = channel_gp10b_setup_ramfc,
-                .channel_set_priority = gk20a_fifo_set_priority,
                 .channel_set_timeslice = gk20a_fifo_set_timeslice,
                 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index fa9388f2..66b2dbef 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -607,25 +607,6 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g)
         return 0;
 }
 
-int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority)
-{
-        struct tegra_vgpu_cmd_msg msg;
-        struct tegra_vgpu_channel_priority_params *p =
-                        &msg.params.channel_priority;
-        int err;
-
-        gk20a_dbg_info("channel %d set priority %u", ch->chid, priority);
-
-        msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY;
-        msg.handle = vgpu_get_handle(ch->g);
-        p->handle = ch->virt_ctx;
-        p->priority = priority;
-        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-        WARN_ON(err || msg.ret);
-
-        return err ? err : msg.ret;
-}
-
 static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
                                         u32 tsgid,
                                         u32 runlist_id,
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
index aa95cc41..7633ad95 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
@@ -46,7 +46,6 @@ int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
 int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
                                 u32 chid, bool add, bool wait_for_finish);
 int vgpu_fifo_wait_engine_idle(struct gk20a *g);
-int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority);
 int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
                                         u32 id,
                                         bool is_tsg,
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
index 37a34950..a3eb59ac 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -264,7 +264,6 @@ static const struct gpu_ops vgpu_gm20b_ops = {
                 .alloc_inst = vgpu_channel_alloc_inst,
                 .free_inst = vgpu_channel_free_inst,
                 .setup_ramfc = vgpu_channel_setup_ramfc,
-                .channel_set_priority = vgpu_channel_set_priority,
                 .channel_set_timeslice = vgpu_channel_set_timeslice,
                 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 693709ef..55448f3b 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -289,7 +289,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .alloc_inst = vgpu_channel_alloc_inst,
                 .free_inst = vgpu_channel_free_inst,
                 .setup_ramfc = vgpu_channel_setup_ramfc,
-                .channel_set_priority = vgpu_channel_set_priority,
                 .channel_set_timeslice = vgpu_channel_set_timeslice,
                 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 9d1a5bdb..20a6de29 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -1008,8 +1008,6 @@ struct nvgpu_gpu_set_event_filter_args {
         _IO(NVGPU_TSG_IOCTL_MAGIC, 4)
 #define NVGPU_IOCTL_TSG_PREEMPT \
         _IO(NVGPU_TSG_IOCTL_MAGIC, 5)
-#define NVGPU_IOCTL_TSG_SET_PRIORITY \
-        _IOW(NVGPU_TSG_IOCTL_MAGIC, 6, struct nvgpu_set_priority_args)
 #define NVGPU_IOCTL_TSG_EVENT_ID_CTRL \
         _IOWR(NVGPU_TSG_IOCTL_MAGIC, 7, struct nvgpu_event_id_ctrl_args)
 #define NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \
@@ -1356,9 +1354,6 @@ struct nvgpu_dbg_gpu_profiler_reserve_args {
 
 #define NVGPU_IOCTL_MAGIC 'H'
 #define NVGPU_NO_TIMEOUT ((u32)~0)
-#define NVGPU_PRIORITY_LOW 50
-#define NVGPU_PRIORITY_MEDIUM 100
-#define NVGPU_PRIORITY_HIGH 150
 #define NVGPU_TIMEOUT_FLAG_DISABLE_DUMP         0
 
 /* this is also the hardware memory format */
@@ -1499,10 +1494,6 @@ struct nvgpu_set_timeout_ex_args {
         __u32 flags;
 };
 
-struct nvgpu_set_priority_args {
-        __u32 priority;
-} __packed;
-
 #define NVGPU_ZCULL_MODE_GLOBAL         0
 #define NVGPU_ZCULL_MODE_NO_CTXSW               1
 #define NVGPU_ZCULL_MODE_SEPARATE_BUFFER        2
@@ -1630,8 +1621,6 @@ struct nvgpu_boosted_ctx_args {
         _IOW(NVGPU_IOCTL_MAGIC, 11, struct nvgpu_set_timeout_args)
 #define NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT        \
         _IOR(NVGPU_IOCTL_MAGIC, 12, struct nvgpu_get_param_args)
-#define NVGPU_IOCTL_CHANNEL_SET_PRIORITY        \
-        _IOW(NVGPU_IOCTL_MAGIC, 13, struct nvgpu_set_priority_args)
 #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX      \
         _IOWR(NVGPU_IOCTL_MAGIC, 18, struct nvgpu_set_timeout_ex_args)
 #define NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO        \