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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-03-23 11:41:04 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:16 -0500
commit3d0f9a751784ac9eb27f9f989f3b584ff5dc8f17 (patch)
tree4c1df46e81b17f47ddc8731beb95c7f351de7788
parent21eda905ea69a0e090f6e29c444a9129c65f0b1f (diff)
gpu: nvgpu: Add support for gp104 and gp106
Add support for chips gp104 and gp106. Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120465 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/Makefile6
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c35
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h26
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c111
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.h26
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c215
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.h21
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_bus_gp106.h193
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h125
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h81
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h289
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_fb_gp106.h489
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h681
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_flush_gp106.h181
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h129
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h1261
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_gr_gp106.h4001
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h553
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_mc_gp106.h245
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h505
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_perf_gp106.h205
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h145
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h69
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_proj_gp106.h149
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h841
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ram_gp106.h477
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_timer_gp106.h109
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_top_gp106.h169
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_xve_gp106.h69
-rw-r--r--drivers/gpu/nvgpu/gp106/pmu_gp106.c46
-rw-r--r--drivers/gpu/nvgpu/gp106/pmu_gp106.h19
-rw-r--r--drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h11
-rw-r--r--include/uapi/linux/nvgpu-t18x.h2
33 files changed, 11482 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 13d52f84..75329a8d 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -18,7 +18,11 @@ nvgpu-y += \
18 $(nvgpu-t18x)/gp10b/therm_gp10b.o \ 18 $(nvgpu-t18x)/gp10b/therm_gp10b.o \
19 $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \ 19 $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \
20 $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \ 20 $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \
21 $(nvgpu-t18x)/gp10b/gp10b.o 21 $(nvgpu-t18x)/gp10b/gp10b.o \
22 $(nvgpu-t18x)/gp106/hal_gp106.o \
23 $(nvgpu-t18x)/gp106/pmu_gp106.o \
24 $(nvgpu-t18x)/gp106/gr_gp106.o \
25 $(nvgpu-t18x)/gp106/gr_ctx_gp106.o
22 26
23nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o 27nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
24 28
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
new file mode 100644
index 00000000..34e1f859
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
@@ -0,0 +1,35 @@
1/*
2 * GP106 Graphics Context
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gr_ctx_gp106.h"
18
19static int gr_gp106_get_netlist_name(int index, char *name)
20{
21 sprintf(name, GP106_NETLIST_IMAGE_FW_NAME);
22 return 0;
23}
24
25static bool gr_gp106_is_firmware_defined(void)
26{
27 return true;
28}
29
30void gp106_init_gr_ctx(struct gpu_ops *gops)
31{
32 gops->gr_ctx.get_netlist_name = gr_gp106_get_netlist_name;
33 gops->gr_ctx.is_fw_defined = gr_gp106_is_firmware_defined;
34 gops->gr_ctx.use_dma_for_fw_bootstrap = false;
35}
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h
new file mode 100644
index 00000000..d14a9126
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __GR_CTX_GP106_H__
17#define __GR_CTX_GP106_H__
18
19#include "gk20a/gr_ctx_gk20a.h"
20
21/* production netlist, one and only one from below */
22#define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C
23
24void gp106_init_gr_ctx(struct gpu_ops *gops);
25
26#endif /*__GR_CTX_GP106_H__*/
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
new file mode 100644
index 00000000..e4768e0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -0,0 +1,111 @@
1/*
2 * GP106 GPU GR
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
17
18#include "gk20a/gr_gk20a.h"
19
20#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
21#include "gp10b/gr_gp10b.h"
22#include "gr_gp106.h"
23#include "hw_gr_gp106.h"
24
25static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
26{
27 bool valid = false;
28
29 switch (class_num) {
30 case PASCAL_COMPUTE_A:
31 case PASCAL_COMPUTE_B:
32 case PASCAL_A:
33 case PASCAL_B:
34 case PASCAL_DMA_COPY_A:
35 valid = true;
36 break;
37
38 case MAXWELL_COMPUTE_B:
39 case MAXWELL_B:
40 case FERMI_TWOD_A:
41 case KEPLER_DMA_COPY_A:
42 case MAXWELL_DMA_COPY_A:
43 valid = true;
44 break;
45
46 default:
47 break;
48 }
49 gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
50 return valid;
51}
52
53static u32 gr_gp106_pagepool_default_size(struct gk20a *g)
54{
55 return gr_scc_pagepool_total_pages_hwmax_value_v();
56}
57
58static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
59 u32 class_num, u32 offset, u32 data)
60{
61 gk20a_dbg_fn("");
62
63 if (class_num == PASCAL_COMPUTE_B) {
64 switch (offset << 2) {
65 case NVC0C0_SET_SHADER_EXCEPTIONS:
66 gk20a_gr_set_shader_exceptions(g, data);
67 break;
68 default:
69 goto fail;
70 }
71 }
72
73 if (class_num == PASCAL_B) {
74 switch (offset << 2) {
75 case NVC097_SET_SHADER_EXCEPTIONS:
76 gk20a_gr_set_shader_exceptions(g, data);
77 break;
78 case NVC097_SET_CIRCULAR_BUFFER_SIZE:
79 g->ops.gr.set_circular_buffer_size(g, data);
80 break;
81 case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
82 g->ops.gr.set_alpha_circular_buffer_size(g, data);
83 break;
84 default:
85 goto fail;
86 }
87 }
88 return 0;
89
90fail:
91 return -EINVAL;
92}
93
94static void gr_gp106_cb_size_default(struct gk20a *g)
95{
96 struct gr_gk20a *gr = &g->gr;
97
98 if (!gr->attrib_cb_default_size)
99 gr->attrib_cb_default_size = 0x800;
100 gr->alpha_cb_default_size =
101 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
102}
103
104void gp106_init_gr(struct gpu_ops *gops)
105{
106 gp10b_init_gr(gops);
107 gops->gr.is_valid_class = gr_gp106_is_valid_class;
108 gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size;
109 gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
110 gops->gr.cb_size_default = gr_gp106_cb_size_default;
111}
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h
new file mode 100644
index 00000000..4fe22ee9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h
@@ -0,0 +1,26 @@
1/*
2 * GP106 GPU GR
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GR_GP106_H_
17#define _NVGPU_GR_GP106_H_
18
19enum {
20 PASCAL_B = 0xC197,
21 PASCAL_COMPUTE_B = 0xC1C0,
22};
23
24void gp106_init_gr(struct gpu_ops *gops);
25
26#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
new file mode 100644
index 00000000..5c9e012d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -0,0 +1,215 @@
1/*
2 * GP106 HAL interface
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18
19#include <linux/types.h>
20
21#include "gk20a/gk20a.h"
22
23#include "gp10b/gr_gp10b.h"
24#include "gp10b/mc_gp10b.h"
25#include "gp10b/ltc_gp10b.h"
26#include "gp10b/mm_gp10b.h"
27#include "gp10b/ce2_gp10b.h"
28#include "gp10b/fb_gp10b.h"
29#include "gp10b/fifo_gp10b.h"
30#include "gp10b/gp10b_gating_reglist.h"
31#include "gp10b/regops_gp10b.h"
32#include "gp10b/cde_gp10b.h"
33#include "gp10b/therm_gp10b.h"
34
35#include "gm206/bios_gm206.h"
36
37#include "gm20b/gr_gm20b.h"
38#include "gm20b/fifo_gm20b.h"
39#include "gm20b/pmu_gm20b.h"
40#include "gm20b/clk_gm20b.h"
41
42#include "gp106/pmu_gp106.h"
43#include "gp106/gr_ctx_gp106.h"
44#include "gp106/gr_gp106.h"
45#include "nvgpu_gpuid_t18x.h"
46#include "hw_proj_gp106.h"
47
48static struct gpu_ops gp106_ops = {
49 .clock_gating = {
50 .slcg_bus_load_gating_prod =
51 gp10b_slcg_bus_load_gating_prod,
52 .slcg_ce2_load_gating_prod =
53 gp10b_slcg_ce2_load_gating_prod,
54 .slcg_chiplet_load_gating_prod =
55 gp10b_slcg_chiplet_load_gating_prod,
56 .slcg_ctxsw_firmware_load_gating_prod =
57 gp10b_slcg_ctxsw_firmware_load_gating_prod,
58 .slcg_fb_load_gating_prod =
59 gp10b_slcg_fb_load_gating_prod,
60 .slcg_fifo_load_gating_prod =
61 gp10b_slcg_fifo_load_gating_prod,
62 .slcg_gr_load_gating_prod =
63 gr_gp10b_slcg_gr_load_gating_prod,
64 .slcg_ltc_load_gating_prod =
65 ltc_gp10b_slcg_ltc_load_gating_prod,
66 .slcg_perf_load_gating_prod =
67 gp10b_slcg_perf_load_gating_prod,
68 .slcg_priring_load_gating_prod =
69 gp10b_slcg_priring_load_gating_prod,
70 .slcg_pmu_load_gating_prod =
71 gp10b_slcg_pmu_load_gating_prod,
72 .slcg_therm_load_gating_prod =
73 gp10b_slcg_therm_load_gating_prod,
74 .slcg_xbar_load_gating_prod =
75 gp10b_slcg_xbar_load_gating_prod,
76 .blcg_bus_load_gating_prod =
77 gp10b_blcg_bus_load_gating_prod,
78 .blcg_ce_load_gating_prod =
79 gp10b_blcg_ce_load_gating_prod,
80 .blcg_ctxsw_firmware_load_gating_prod =
81 gp10b_blcg_ctxsw_firmware_load_gating_prod,
82 .blcg_fb_load_gating_prod =
83 gp10b_blcg_fb_load_gating_prod,
84 .blcg_fifo_load_gating_prod =
85 gp10b_blcg_fifo_load_gating_prod,
86 .blcg_gr_load_gating_prod =
87 gp10b_blcg_gr_load_gating_prod,
88 .blcg_ltc_load_gating_prod =
89 gp10b_blcg_ltc_load_gating_prod,
90 .blcg_pwr_csb_load_gating_prod =
91 gp10b_blcg_pwr_csb_load_gating_prod,
92 .blcg_pmu_load_gating_prod =
93 gp10b_blcg_pmu_load_gating_prod,
94 .blcg_xbar_load_gating_prod =
95 gp10b_blcg_xbar_load_gating_prod,
96 .pg_gr_load_gating_prod =
97 gr_gp10b_pg_gr_load_gating_prod,
98 }
99};
100
101static int gp106_get_litter_value(struct gk20a *g,
102 enum nvgpu_litter_value value)
103{
104 int ret = -EINVAL;
105
106 switch (value) {
107 case GPU_LIT_NUM_GPCS:
108 ret = proj_scal_litter_num_gpcs_v();
109 break;
110 case GPU_LIT_NUM_PES_PER_GPC:
111 ret = proj_scal_litter_num_pes_per_gpc_v();
112 break;
113 case GPU_LIT_NUM_ZCULL_BANKS:
114 ret = proj_scal_litter_num_zcull_banks_v();
115 break;
116 case GPU_LIT_NUM_TPC_PER_GPC:
117 ret = proj_scal_litter_num_tpc_per_gpc_v();
118 break;
119 case GPU_LIT_NUM_FBPS:
120 ret = proj_scal_litter_num_fbps_v();
121 break;
122 case GPU_LIT_GPC_BASE:
123 ret = proj_gpc_base_v();
124 break;
125 case GPU_LIT_GPC_STRIDE:
126 ret = proj_gpc_stride_v();
127 break;
128 case GPU_LIT_GPC_SHARED_BASE:
129 ret = proj_gpc_shared_base_v();
130 break;
131 case GPU_LIT_TPC_IN_GPC_BASE:
132 ret = proj_tpc_in_gpc_base_v();
133 break;
134 case GPU_LIT_TPC_IN_GPC_STRIDE:
135 ret = proj_tpc_in_gpc_stride_v();
136 break;
137 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
138 ret = proj_tpc_in_gpc_shared_base_v();
139 break;
140 case GPU_LIT_PPC_IN_GPC_STRIDE:
141 ret = proj_ppc_in_gpc_stride_v();
142 break;
143 case GPU_LIT_ROP_BASE:
144 ret = proj_rop_base_v();
145 break;
146 case GPU_LIT_ROP_STRIDE:
147 ret = proj_rop_stride_v();
148 break;
149 case GPU_LIT_ROP_SHARED_BASE:
150 ret = proj_rop_shared_base_v();
151 break;
152 case GPU_LIT_HOST_NUM_PBDMA:
153 ret = proj_host_num_pbdma_v();
154 break;
155 case GPU_LIT_LTC_STRIDE:
156 ret = proj_ltc_stride_v();
157 break;
158 case GPU_LIT_LTS_STRIDE:
159 ret = proj_lts_stride_v();
160 break;
161 case GPU_LIT_NUM_FBPAS:
162 ret = proj_scal_litter_num_fbpas_v();
163 break;
164 case GPU_LIT_FBPA_STRIDE:
165 ret = proj_fbpa_stride_v();
166 break;
167 default:
168 BUG();
169 break;
170 }
171
172 return ret;
173}
174
175int gp106_init_hal(struct gk20a *g)
176{
177 struct gpu_ops *gops = &g->ops;
178 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
179
180 gk20a_dbg_fn("");
181
182 *gops = gp106_ops;
183
184 gops->privsecurity = 0;
185 gops->securegpccs = 0;
186
187 gp10b_init_mc(gops);
188 gp106_init_gr(gops);
189 gp10b_init_ltc(gops);
190 gp10b_init_fb(gops);
191 gp10b_init_fifo(gops);
192 gp10b_init_ce2(gops);
193 gp106_init_gr_ctx(gops);
194 gp10b_init_mm(gops);
195 gp106_init_pmu_ops(gops);
196 gk20a_init_debug_ops(gops);
197 gp10b_init_regops(gops);
198 gp10b_init_cde_ops(gops);
199 gp10b_init_therm_ops(gops);
200 gm206_init_bios(gops);
201 gops->name = "gp106";
202 gops->get_litter_value = gp106_get_litter_value;
203 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
204
205 c->twod_class = FERMI_TWOD_A;
206 c->threed_class = PASCAL_B;
207 c->compute_class = PASCAL_COMPUTE_B;
208 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
209 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
210 c->dma_copy_class = PASCAL_DMA_COPY_A;
211
212 gk20a_dbg_fn("done");
213
214 return 0;
215}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.h b/drivers/gpu/nvgpu/gp106/hal_gp106.h
new file mode 100644
index 00000000..af91267b
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.h
@@ -0,0 +1,21 @@
1/*
2 * GP106 Tegra HAL interface
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_HAL_GP106_H
17#define _NVGPU_HAL_GP106_H
18struct gk20a;
19
20int gp106_init_hal(struct gk20a *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h b/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h
new file mode 100644
index 00000000..6d80b6a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h
@@ -0,0 +1,193 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_bus_gp106_h_
51#define _hw_bus_gp106_h_
52
53static inline u32 bus_bar1_block_r(void)
54{
55 return 0x00001704;
56}
57static inline u32 bus_bar1_block_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 bus_bar1_block_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
66{
67 return 0x20000000;
68}
69static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
70{
71 return 0x30000000;
72}
73static inline u32 bus_bar1_block_mode_virtual_f(void)
74{
75 return 0x80000000;
76}
77static inline u32 bus_bar2_block_r(void)
78{
79 return 0x00001714;
80}
81static inline u32 bus_bar2_block_ptr_f(u32 v)
82{
83 return (v & 0xfffffff) << 0;
84}
85static inline u32 bus_bar2_block_target_vid_mem_f(void)
86{
87 return 0x0;
88}
89static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
90{
91 return 0x20000000;
92}
93static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
94{
95 return 0x30000000;
96}
97static inline u32 bus_bar2_block_mode_virtual_f(void)
98{
99 return 0x80000000;
100}
101static inline u32 bus_bar1_block_ptr_shift_v(void)
102{
103 return 0x0000000c;
104}
105static inline u32 bus_bar2_block_ptr_shift_v(void)
106{
107 return 0x0000000c;
108}
109static inline u32 bus_bind_status_r(void)
110{
111 return 0x00001710;
112}
113static inline u32 bus_bind_status_bar1_pending_v(u32 r)
114{
115 return (r >> 0) & 0x1;
116}
117static inline u32 bus_bind_status_bar1_pending_empty_f(void)
118{
119 return 0x0;
120}
121static inline u32 bus_bind_status_bar1_pending_busy_f(void)
122{
123 return 0x1;
124}
125static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
126{
127 return (r >> 1) & 0x1;
128}
129static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
130{
131 return 0x0;
132}
133static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
134{
135 return 0x2;
136}
137static inline u32 bus_bind_status_bar2_pending_v(u32 r)
138{
139 return (r >> 2) & 0x1;
140}
141static inline u32 bus_bind_status_bar2_pending_empty_f(void)
142{
143 return 0x0;
144}
145static inline u32 bus_bind_status_bar2_pending_busy_f(void)
146{
147 return 0x4;
148}
149static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
150{
151 return (r >> 3) & 0x1;
152}
153static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
154{
155 return 0x0;
156}
157static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
158{
159 return 0x8;
160}
161static inline u32 bus_intr_0_r(void)
162{
163 return 0x00001100;
164}
165static inline u32 bus_intr_0_pri_squash_m(void)
166{
167 return 0x1 << 1;
168}
169static inline u32 bus_intr_0_pri_fecserr_m(void)
170{
171 return 0x1 << 2;
172}
173static inline u32 bus_intr_0_pri_timeout_m(void)
174{
175 return 0x1 << 3;
176}
177static inline u32 bus_intr_en_0_r(void)
178{
179 return 0x00001140;
180}
181static inline u32 bus_intr_en_0_pri_squash_m(void)
182{
183 return 0x1 << 1;
184}
185static inline u32 bus_intr_en_0_pri_fecserr_m(void)
186{
187 return 0x1 << 2;
188}
189static inline u32 bus_intr_en_0_pri_timeout_m(void)
190{
191 return 0x1 << 3;
192}
193#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h
new file mode 100644
index 00000000..65146d39
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h
@@ -0,0 +1,125 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ccsr_gp106_h_
51#define _hw_ccsr_gp106_h_
52
53static inline u32 ccsr_channel_inst_r(u32 i)
54{
55 return 0x00800000 + i*8;
56}
57static inline u32 ccsr_channel_inst__size_1_v(void)
58{
59 return 0x00001000;
60}
61static inline u32 ccsr_channel_inst_ptr_f(u32 v)
62{
63 return (v & 0xfffffff) << 0;
64}
65static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
66{
67 return 0x0;
68}
69static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
70{
71 return 0x20000000;
72}
73static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
74{
75 return 0x30000000;
76}
77static inline u32 ccsr_channel_inst_bind_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 ccsr_channel_inst_bind_true_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 ccsr_channel_r(u32 i)
86{
87 return 0x00800004 + i*8;
88}
89static inline u32 ccsr_channel__size_1_v(void)
90{
91 return 0x00001000;
92}
93static inline u32 ccsr_channel_enable_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 ccsr_channel_enable_set_f(u32 v)
98{
99 return (v & 0x1) << 10;
100}
101static inline u32 ccsr_channel_enable_set_true_f(void)
102{
103 return 0x400;
104}
105static inline u32 ccsr_channel_enable_clr_true_f(void)
106{
107 return 0x800;
108}
109static inline u32 ccsr_channel_status_v(u32 r)
110{
111 return (r >> 24) & 0xf;
112}
113static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
114{
115 return 0x00000002;
116}
117static inline u32 ccsr_channel_busy_v(u32 r)
118{
119 return (r >> 28) & 0x1;
120}
121static inline u32 ccsr_channel_next_v(u32 r)
122{
123 return (r >> 1) & 0x1;
124}
125#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h
new file mode 100644
index 00000000..d56b930b
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ce2_gp106_h_
51#define _hw_ce2_gp106_h_
52
53static inline u32 ce2_intr_status_r(u32 i)
54{
55 return 0x00104410 + i*128;
56}
57static inline u32 ce2_intr_status_blockpipe_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 ce2_intr_status_blockpipe_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 ce2_intr_status_launcherr_pending_f(void)
74{
75 return 0x4;
76}
77static inline u32 ce2_intr_status_launcherr_reset_f(void)
78{
79 return 0x4;
80}
81#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h
new file mode 100644
index 00000000..ed3e6009
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ctxsw_prog_gp106_h_
51#define _hw_ctxsw_prog_gp106_h_
52
53static inline u32 ctxsw_prog_fecs_header_v(void)
54{
55 return 0x00000100;
56}
57static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
58{
59 return 0x00000008;
60}
61static inline u32 ctxsw_prog_main_image_patch_count_o(void)
62{
63 return 0x00000010;
64}
65static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
66{
67 return 0x00000014;
68}
69static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
70{
71 return 0x00000018;
72}
73static inline u32 ctxsw_prog_main_image_zcull_o(void)
74{
75 return 0x0000001c;
76}
77static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
82{
83 return 0x00000002;
84}
85static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
86{
87 return 0x00000020;
88}
89static inline u32 ctxsw_prog_main_image_pm_o(void)
90{
91 return 0x00000028;
92}
93static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
94{
95 return 0x7 << 0;
96}
97static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
98{
99 return 0x0;
100}
101static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
102{
103 return 0x7 << 3;
104}
105static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
106{
107 return 0x8;
108}
109static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
110{
111 return 0x0;
112}
113static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
114{
115 return 0x0000002c;
116}
117static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
118{
119 return 0x000000f4;
120}
121static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
122{
123 return 0x000000d0;
124}
125static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
126{
127 return 0x000000d4;
128}
129static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
130{
131 return 0x000000d8;
132}
133static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
134{
135 return 0x000000dc;
136}
137static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
138{
139 return 0x000000f8;
140}
141static inline u32 ctxsw_prog_main_image_magic_value_o(void)
142{
143 return 0x000000fc;
144}
145static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
146{
147 return 0x600dc0de;
148}
149static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
150{
151 return 0x0000000c;
152}
153static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
154{
155 return (r >> 0) & 0xffff;
156}
157static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
158{
159 return 0x000000f4;
160}
161static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
162{
163 return (r >> 0) & 0xffff;
164}
165static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
166{
167 return (r >> 16) & 0xffff;
168}
169static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
170{
171 return 0x000000f8;
172}
173static inline u32 ctxsw_prog_local_magic_value_o(void)
174{
175 return 0x000000fc;
176}
177static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
178{
179 return 0xad0becab;
180}
181static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
182{
183 return 0x000000ec;
184}
185static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
186{
187 return (r >> 0) & 0xffff;
188}
189static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
190{
191 return (r >> 16) & 0xff;
192}
193static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
194{
195 return 0x00000100;
196}
197static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
198{
199 return 0x00000004;
200}
201static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
202{
203 return 0x00000000;
204}
205static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
206{
207 return 0x00000002;
208}
209static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
210{
211 return 0x000000a0;
212}
213static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
214{
215 return 2;
216}
217static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
218{
219 return (v & 0x3) << 0;
220}
221static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
222{
223 return 0x3 << 0;
224}
225static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
226{
227 return (r >> 0) & 0x3;
228}
229static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
230{
231 return 0x0;
232}
233static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
234{
235 return 0x2;
236}
237static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
238{
239 return 0x000000a4;
240}
241static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
242{
243 return 0x000000a8;
244}
245static inline u32 ctxsw_prog_main_image_misc_options_o(void)
246{
247 return 0x0000003c;
248}
249static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
250{
251 return 0x1 << 3;
252}
253static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
254{
255 return 0x0;
256}
257static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
258{
259 return 0x00000080;
260}
261static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
262{
263 return (v & 0x3) << 0;
264}
265static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
266{
267 return 0x1;
268}
269static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
270{
271 return 0x00000068;
272}
273static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
274{
275 return 0x00000084;
276}
277static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
278{
279 return (v & 0x3) << 0;
280}
281static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
282{
283 return 0x1;
284}
285static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
286{
287 return 0x2;
288}
289#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h
new file mode 100644
index 00000000..42d32ab3
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h
@@ -0,0 +1,489 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fb_gp106_h_
51#define _hw_fb_gp106_h_
52
53static inline u32 fb_fbhub_num_active_ltcs_r(void)
54{
55 return 0x00100800;
56}
57static inline u32 fb_mmu_ctrl_r(void)
58{
59 return 0x00100c80;
60}
61static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
62{
63 return (v & 0x1) << 0;
64}
65static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
66{
67 return 0x0;
68}
69static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
70{
71 return 0x1;
72}
73static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
74{
75 return (r >> 15) & 0x1;
76}
77static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
82{
83 return (r >> 16) & 0xff;
84}
85static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
86{
87 return (r >> 11) & 0x1;
88}
89static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
90{
91 return 0x800;
92}
93static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
94{
95 return 0x0;
96}
97static inline u32 fb_priv_mmu_phy_secure_r(void)
98{
99 return 0x00100ce4;
100}
101static inline u32 fb_mmu_invalidate_pdb_r(void)
102{
103 return 0x00100cb8;
104}
105static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
106{
107 return 0x0;
108}
109static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
110{
111 return 0x2;
112}
113static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
114{
115 return (v & 0xfffffff) << 4;
116}
117static inline u32 fb_mmu_invalidate_r(void)
118{
119 return 0x00100cbc;
120}
121static inline u32 fb_mmu_invalidate_all_va_true_f(void)
122{
123 return 0x1;
124}
125static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
126{
127 return 0x2;
128}
129static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
130{
131 return 1;
132}
133static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
138{
139 return 0x1 << 2;
140}
141static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
142{
143 return (r >> 2) & 0x1;
144}
145static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
146{
147 return 0x4;
148}
149static inline u32 fb_mmu_invalidate_replay_s(void)
150{
151 return 3;
152}
153static inline u32 fb_mmu_invalidate_replay_f(u32 v)
154{
155 return (v & 0x7) << 3;
156}
157static inline u32 fb_mmu_invalidate_replay_m(void)
158{
159 return 0x7 << 3;
160}
161static inline u32 fb_mmu_invalidate_replay_v(u32 r)
162{
163 return (r >> 3) & 0x7;
164}
165static inline u32 fb_mmu_invalidate_replay_none_f(void)
166{
167 return 0x0;
168}
169static inline u32 fb_mmu_invalidate_replay_start_f(void)
170{
171 return 0x8;
172}
173static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
174{
175 return 0x10;
176}
177static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
178{
179 return 0x18;
180}
181static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
182{
183 return 0x20;
184}
185static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
186{
187 return 0x20;
188}
189static inline u32 fb_mmu_invalidate_sys_membar_s(void)
190{
191 return 1;
192}
193static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 fb_mmu_invalidate_sys_membar_m(void)
198{
199 return 0x1 << 6;
200}
201static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
202{
203 return (r >> 6) & 0x1;
204}
205static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
206{
207 return 0x40;
208}
209static inline u32 fb_mmu_invalidate_ack_s(void)
210{
211 return 2;
212}
213static inline u32 fb_mmu_invalidate_ack_f(u32 v)
214{
215 return (v & 0x3) << 7;
216}
217static inline u32 fb_mmu_invalidate_ack_m(void)
218{
219 return 0x3 << 7;
220}
221static inline u32 fb_mmu_invalidate_ack_v(u32 r)
222{
223 return (r >> 7) & 0x3;
224}
225static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
226{
227 return 0x0;
228}
229static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
230{
231 return 0x100;
232}
233static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
234{
235 return 0x80;
236}
237static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
238{
239 return 6;
240}
241static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
242{
243 return (v & 0x3f) << 9;
244}
245static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
246{
247 return 0x3f << 9;
248}
249static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
250{
251 return (r >> 9) & 0x3f;
252}
253static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
254{
255 return 5;
256}
257static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
258{
259 return (v & 0x1f) << 15;
260}
261static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
262{
263 return 0x1f << 15;
264}
265static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
266{
267 return (r >> 15) & 0x1f;
268}
269static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
270{
271 return 1;
272}
273static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
274{
275 return (v & 0x1) << 20;
276}
277static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
278{
279 return 0x1 << 20;
280}
281static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
282{
283 return (r >> 20) & 0x1;
284}
285static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
286{
287 return 0x0;
288}
289static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
290{
291 return 0x100000;
292}
293static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
294{
295 return 3;
296}
297static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
298{
299 return (v & 0x7) << 24;
300}
301static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
302{
303 return 0x7 << 24;
304}
305static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
306{
307 return (r >> 24) & 0x7;
308}
309static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
310{
311 return 0x0;
312}
313static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
314{
315 return 0x1000000;
316}
317static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
318{
319 return 0x2000000;
320}
321static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
322{
323 return 0x3000000;
324}
325static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
326{
327 return 0x4000000;
328}
329static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
330{
331 return 0x5000000;
332}
333static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
334{
335 return 0x6000000;
336}
337static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
338{
339 return 0x7000000;
340}
341static inline u32 fb_mmu_invalidate_trigger_s(void)
342{
343 return 1;
344}
345static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
346{
347 return (v & 0x1) << 31;
348}
349static inline u32 fb_mmu_invalidate_trigger_m(void)
350{
351 return 0x1 << 31;
352}
353static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
354{
355 return (r >> 31) & 0x1;
356}
357static inline u32 fb_mmu_invalidate_trigger_true_f(void)
358{
359 return 0x80000000;
360}
361static inline u32 fb_mmu_debug_wr_r(void)
362{
363 return 0x00100cc8;
364}
365static inline u32 fb_mmu_debug_wr_aperture_s(void)
366{
367 return 2;
368}
369static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
370{
371 return (v & 0x3) << 0;
372}
373static inline u32 fb_mmu_debug_wr_aperture_m(void)
374{
375 return 0x3 << 0;
376}
377static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
378{
379 return (r >> 0) & 0x3;
380}
381static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
382{
383 return 0x0;
384}
385static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
386{
387 return 0x2;
388}
389static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
390{
391 return 0x3;
392}
393static inline u32 fb_mmu_debug_wr_vol_false_f(void)
394{
395 return 0x0;
396}
397static inline u32 fb_mmu_debug_wr_vol_true_v(void)
398{
399 return 0x00000001;
400}
401static inline u32 fb_mmu_debug_wr_vol_true_f(void)
402{
403 return 0x4;
404}
405static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
406{
407 return (v & 0xfffffff) << 4;
408}
409static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
410{
411 return 0x0000000c;
412}
413static inline u32 fb_mmu_debug_rd_r(void)
414{
415 return 0x00100ccc;
416}
417static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
418{
419 return 0x0;
420}
421static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
422{
423 return 0x2;
424}
425static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
426{
427 return 0x3;
428}
429static inline u32 fb_mmu_debug_rd_vol_false_f(void)
430{
431 return 0x0;
432}
433static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
434{
435 return (v & 0xfffffff) << 4;
436}
437static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
438{
439 return 0x0000000c;
440}
441static inline u32 fb_mmu_debug_ctrl_r(void)
442{
443 return 0x00100cc4;
444}
445static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
446{
447 return (r >> 16) & 0x1;
448}
449static inline u32 fb_mmu_debug_ctrl_debug_m(void)
450{
451 return 0x1 << 16;
452}
453static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
454{
455 return 0x00000001;
456}
457static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
458{
459 return 0x10000;
460}
461static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
462{
463 return 0x00000000;
464}
465static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
466{
467 return 0x0;
468}
469static inline u32 fb_mmu_vpr_info_r(void)
470{
471 return 0x00100cd0;
472}
473static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
474{
475 return (r >> 2) & 0x1;
476}
477static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
478{
479 return 0x00000000;
480}
481static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
482{
483 return 0x00000001;
484}
485static inline u32 fb_niso_flush_sysmem_addr_r(void)
486{
487 return 0x00100c10;
488}
489#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h
new file mode 100644
index 00000000..763b58df
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h
@@ -0,0 +1,681 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fifo_gp106_h_
51#define _hw_fifo_gp106_h_
52
53static inline u32 fifo_bar1_base_r(void)
54{
55 return 0x00002254;
56}
57static inline u32 fifo_bar1_base_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
62{
63 return 0x0000000c;
64}
65static inline u32 fifo_bar1_base_valid_false_f(void)
66{
67 return 0x0;
68}
69static inline u32 fifo_bar1_base_valid_true_f(void)
70{
71 return 0x10000000;
72}
73static inline u32 fifo_runlist_base_r(void)
74{
75 return 0x00002270;
76}
77static inline u32 fifo_runlist_base_ptr_f(u32 v)
78{
79 return (v & 0xfffffff) << 0;
80}
81static inline u32 fifo_runlist_base_target_vid_mem_f(void)
82{
83 return 0x0;
84}
85static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
86{
87 return 0x20000000;
88}
89static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
90{
91 return 0x30000000;
92}
93static inline u32 fifo_runlist_r(void)
94{
95 return 0x00002274;
96}
97static inline u32 fifo_runlist_engine_f(u32 v)
98{
99 return (v & 0xf) << 20;
100}
101static inline u32 fifo_eng_runlist_base_r(u32 i)
102{
103 return 0x00002280 + i*8;
104}
105static inline u32 fifo_eng_runlist_base__size_1_v(void)
106{
107 return 0x00000007;
108}
109static inline u32 fifo_eng_runlist_r(u32 i)
110{
111 return 0x00002284 + i*8;
112}
113static inline u32 fifo_eng_runlist__size_1_v(void)
114{
115 return 0x00000007;
116}
117static inline u32 fifo_eng_runlist_length_f(u32 v)
118{
119 return (v & 0xffff) << 0;
120}
121static inline u32 fifo_eng_runlist_length_max_v(void)
122{
123 return 0x0000ffff;
124}
125static inline u32 fifo_eng_runlist_pending_true_f(void)
126{
127 return 0x100000;
128}
129static inline u32 fifo_pb_timeslice_r(u32 i)
130{
131 return 0x00002350 + i*4;
132}
133static inline u32 fifo_pb_timeslice_timeout_16_f(void)
134{
135 return 0x10;
136}
137static inline u32 fifo_pb_timeslice_timescale_0_f(void)
138{
139 return 0x0;
140}
141static inline u32 fifo_pb_timeslice_enable_true_f(void)
142{
143 return 0x10000000;
144}
145static inline u32 fifo_pbdma_map_r(u32 i)
146{
147 return 0x00002390 + i*4;
148}
149static inline u32 fifo_intr_0_r(void)
150{
151 return 0x00002100;
152}
153static inline u32 fifo_intr_0_bind_error_pending_f(void)
154{
155 return 0x1;
156}
157static inline u32 fifo_intr_0_bind_error_reset_f(void)
158{
159 return 0x1;
160}
161static inline u32 fifo_intr_0_sched_error_pending_f(void)
162{
163 return 0x100;
164}
165static inline u32 fifo_intr_0_sched_error_reset_f(void)
166{
167 return 0x100;
168}
169static inline u32 fifo_intr_0_chsw_error_pending_f(void)
170{
171 return 0x10000;
172}
173static inline u32 fifo_intr_0_chsw_error_reset_f(void)
174{
175 return 0x10000;
176}
177static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
178{
179 return 0x800000;
180}
181static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
182{
183 return 0x800000;
184}
185static inline u32 fifo_intr_0_lb_error_pending_f(void)
186{
187 return 0x1000000;
188}
189static inline u32 fifo_intr_0_lb_error_reset_f(void)
190{
191 return 0x1000000;
192}
193static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
194{
195 return 0x2000000;
196}
197static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
198{
199 return 0x8000000;
200}
201static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
202{
203 return 0x8000000;
204}
205static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
206{
207 return 0x10000000;
208}
209static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
210{
211 return 0x20000000;
212}
213static inline u32 fifo_intr_0_runlist_event_pending_f(void)
214{
215 return 0x40000000;
216}
217static inline u32 fifo_intr_0_channel_intr_pending_f(void)
218{
219 return 0x80000000;
220}
221static inline u32 fifo_intr_en_0_r(void)
222{
223 return 0x00002140;
224}
225static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
226{
227 return (v & 0x1) << 8;
228}
229static inline u32 fifo_intr_en_0_sched_error_m(void)
230{
231 return 0x1 << 8;
232}
233static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
234{
235 return (v & 0x1) << 28;
236}
237static inline u32 fifo_intr_en_0_mmu_fault_m(void)
238{
239 return 0x1 << 28;
240}
241static inline u32 fifo_intr_en_1_r(void)
242{
243 return 0x00002528;
244}
245static inline u32 fifo_intr_bind_error_r(void)
246{
247 return 0x0000252c;
248}
249static inline u32 fifo_intr_sched_error_r(void)
250{
251 return 0x0000254c;
252}
253static inline u32 fifo_intr_sched_error_code_f(u32 v)
254{
255 return (v & 0xff) << 0;
256}
257static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
258{
259 return 0x0000000a;
260}
261static inline u32 fifo_intr_chsw_error_r(void)
262{
263 return 0x0000256c;
264}
265static inline u32 fifo_intr_mmu_fault_id_r(void)
266{
267 return 0x0000259c;
268}
269static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
274{
275 return 0x0;
276}
277static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
278{
279 return 0x00002800 + i*16;
280}
281static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
282{
283 return (r >> 0) & 0xfffffff;
284}
285static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
286{
287 return 0x0000000c;
288}
289static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
290{
291 return 0x00002804 + i*16;
292}
293static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
294{
295 return 0x00002808 + i*16;
296}
297static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
298{
299 return 0x0000280c + i*16;
300}
301static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
302{
303 return (r >> 0) & 0x1f;
304}
305static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
306{
307 return (r >> 20) & 0x1;
308}
309static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
310{
311 return 0x00000000;
312}
313static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
314{
315 return 0x00000001;
316}
317static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
318{
319 return (r >> 8) & 0x7f;
320}
321static inline u32 fifo_intr_pbdma_id_r(void)
322{
323 return 0x000025a0;
324}
325static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
326{
327 return (v & 0x1) << (0 + i*1);
328}
329static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
330{
331 return 0x00000004;
332}
333static inline u32 fifo_intr_runlist_r(void)
334{
335 return 0x00002a00;
336}
337static inline u32 fifo_fb_timeout_r(void)
338{
339 return 0x00002a04;
340}
341static inline u32 fifo_fb_timeout_period_m(void)
342{
343 return 0x3fffffff << 0;
344}
345static inline u32 fifo_fb_timeout_period_max_f(void)
346{
347 return 0x3fffffff;
348}
349static inline u32 fifo_error_sched_disable_r(void)
350{
351 return 0x0000262c;
352}
353static inline u32 fifo_sched_disable_r(void)
354{
355 return 0x00002630;
356}
357static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
358{
359 return (v & 0x1) << (0 + i*1);
360}
361static inline u32 fifo_sched_disable_runlist_m(u32 i)
362{
363 return 0x1 << (0 + i*1);
364}
365static inline u32 fifo_sched_disable_true_v(void)
366{
367 return 0x00000001;
368}
369static inline u32 fifo_preempt_r(void)
370{
371 return 0x00002634;
372}
373static inline u32 fifo_preempt_pending_true_f(void)
374{
375 return 0x100000;
376}
377static inline u32 fifo_preempt_type_channel_f(void)
378{
379 return 0x0;
380}
381static inline u32 fifo_preempt_type_tsg_f(void)
382{
383 return 0x1000000;
384}
385static inline u32 fifo_preempt_chid_f(u32 v)
386{
387 return (v & 0xfff) << 0;
388}
389static inline u32 fifo_preempt_id_f(u32 v)
390{
391 return (v & 0xfff) << 0;
392}
393static inline u32 fifo_trigger_mmu_fault_r(u32 i)
394{
395 return 0x00002a30 + i*4;
396}
397static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
398{
399 return (v & 0x1f) << 0;
400}
401static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
402{
403 return (v & 0x1) << 8;
404}
405static inline u32 fifo_engine_status_r(u32 i)
406{
407 return 0x00002640 + i*8;
408}
409static inline u32 fifo_engine_status__size_1_v(void)
410{
411 return 0x00000009;
412}
413static inline u32 fifo_engine_status_id_v(u32 r)
414{
415 return (r >> 0) & 0xfff;
416}
417static inline u32 fifo_engine_status_id_type_v(u32 r)
418{
419 return (r >> 12) & 0x1;
420}
421static inline u32 fifo_engine_status_id_type_chid_v(void)
422{
423 return 0x00000000;
424}
425static inline u32 fifo_engine_status_id_type_tsgid_v(void)
426{
427 return 0x00000001;
428}
429static inline u32 fifo_engine_status_ctx_status_v(u32 r)
430{
431 return (r >> 13) & 0x7;
432}
433static inline u32 fifo_engine_status_ctx_status_valid_v(void)
434{
435 return 0x00000001;
436}
437static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
438{
439 return 0x00000005;
440}
441static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
442{
443 return 0x00000006;
444}
445static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
446{
447 return 0x00000007;
448}
449static inline u32 fifo_engine_status_next_id_v(u32 r)
450{
451 return (r >> 16) & 0xfff;
452}
453static inline u32 fifo_engine_status_next_id_type_v(u32 r)
454{
455 return (r >> 28) & 0x1;
456}
457static inline u32 fifo_engine_status_next_id_type_chid_v(void)
458{
459 return 0x00000000;
460}
461static inline u32 fifo_engine_status_faulted_v(u32 r)
462{
463 return (r >> 30) & 0x1;
464}
465static inline u32 fifo_engine_status_faulted_true_v(void)
466{
467 return 0x00000001;
468}
469static inline u32 fifo_engine_status_engine_v(u32 r)
470{
471 return (r >> 31) & 0x1;
472}
473static inline u32 fifo_engine_status_engine_idle_v(void)
474{
475 return 0x00000000;
476}
477static inline u32 fifo_engine_status_engine_busy_v(void)
478{
479 return 0x00000001;
480}
481static inline u32 fifo_engine_status_ctxsw_v(u32 r)
482{
483 return (r >> 15) & 0x1;
484}
485static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
486{
487 return 0x00000001;
488}
489static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
490{
491 return 0x8000;
492}
493static inline u32 fifo_pbdma_status_r(u32 i)
494{
495 return 0x00003080 + i*4;
496}
497static inline u32 fifo_pbdma_status__size_1_v(void)
498{
499 return 0x00000004;
500}
501static inline u32 fifo_pbdma_status_id_v(u32 r)
502{
503 return (r >> 0) & 0xfff;
504}
505static inline u32 fifo_pbdma_status_id_type_v(u32 r)
506{
507 return (r >> 12) & 0x1;
508}
509static inline u32 fifo_pbdma_status_id_type_chid_v(void)
510{
511 return 0x00000000;
512}
513static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
514{
515 return 0x00000001;
516}
517static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
518{
519 return (r >> 13) & 0x7;
520}
521static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
522{
523 return 0x00000001;
524}
525static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
526{
527 return 0x00000005;
528}
529static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
530{
531 return 0x00000006;
532}
533static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
534{
535 return 0x00000007;
536}
537static inline u32 fifo_pbdma_status_next_id_v(u32 r)
538{
539 return (r >> 16) & 0xfff;
540}
541static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
542{
543 return (r >> 28) & 0x1;
544}
545static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
546{
547 return 0x00000000;
548}
549static inline u32 fifo_pbdma_status_chsw_v(u32 r)
550{
551 return (r >> 15) & 0x1;
552}
553static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
554{
555 return 0x00000001;
556}
557static inline u32 fifo_replay_fault_buffer_lo_r(void)
558{
559 return 0x00002a70;
560}
561static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
562{
563 return (r >> 0) & 0x1;
564}
565static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
566{
567 return 0x00000001;
568}
569static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
570{
571 return 0x00000000;
572}
573static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
574{
575 return (v & 0xfffff) << 12;
576}
577static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
578{
579 return 0x00000000;
580}
581static inline u32 fifo_replay_fault_buffer_hi_r(void)
582{
583 return 0x00002a74;
584}
585static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
586{
587 return (v & 0xff) << 0;
588}
589static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
590{
591 return 0x00000000;
592}
593static inline u32 fifo_replay_fault_buffer_size_r(void)
594{
595 return 0x00002a78;
596}
597static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
598{
599 return (v & 0x3fff) << 0;
600}
601static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
602{
603 return 0x00001200;
604}
605static inline u32 fifo_replay_fault_buffer_get_r(void)
606{
607 return 0x00002a7c;
608}
609static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
610{
611 return (v & 0x3fff) << 0;
612}
613static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
614{
615 return 0x00000000;
616}
617static inline u32 fifo_replay_fault_buffer_put_r(void)
618{
619 return 0x00002a80;
620}
621static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
622{
623 return (v & 0x3fff) << 0;
624}
625static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
626{
627 return 0x00000000;
628}
629static inline u32 fifo_replay_fault_buffer_info_r(void)
630{
631 return 0x00002a84;
632}
633static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
634{
635 return (v & 0x1) << 0;
636}
637static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
638{
639 return 0x00000000;
640}
641static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
642{
643 return 0x00000001;
644}
645static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
646{
647 return 0x00000001;
648}
649static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
650{
651 return (v & 0x1) << 24;
652}
653static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
654{
655 return 0x00000000;
656}
657static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
658{
659 return 0x00000001;
660}
661static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
662{
663 return 0x00000001;
664}
665static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
666{
667 return (v & 0x1) << 28;
668}
669static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
670{
671 return 0x00000000;
672}
673static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
674{
675 return 0x00000001;
676}
677static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
678{
679 return 0x00000001;
680}
681#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h b/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h
new file mode 100644
index 00000000..83bd65bb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h
@@ -0,0 +1,181 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_flush_gp106_h_
51#define _hw_flush_gp106_h_
52
53static inline u32 flush_l2_system_invalidate_r(void)
54{
55 return 0x00070004;
56}
57static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
58{
59 return (r >> 0) & 0x1;
60}
61static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
66{
67 return 0x1;
68}
69static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
70{
71 return (r >> 1) & 0x1;
72}
73static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 flush_l2_flush_dirty_r(void)
78{
79 return 0x00070010;
80}
81static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
82{
83 return (r >> 0) & 0x1;
84}
85static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
90{
91 return 0x0;
92}
93static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
94{
95 return 0x00000001;
96}
97static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
98{
99 return 0x1;
100}
101static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
102{
103 return (r >> 1) & 0x1;
104}
105static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
110{
111 return 0x0;
112}
113static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 flush_l2_clean_comptags_r(void)
118{
119 return 0x0007000c;
120}
121static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
122{
123 return (r >> 0) & 0x1;
124}
125static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
126{
127 return 0x00000000;
128}
129static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
130{
131 return 0x0;
132}
133static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
138{
139 return 0x1;
140}
141static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
142{
143 return (r >> 1) & 0x1;
144}
145static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 flush_fb_flush_r(void)
158{
159 return 0x00070000;
160}
161static inline u32 flush_fb_flush_pending_v(u32 r)
162{
163 return (r >> 0) & 0x1;
164}
165static inline u32 flush_fb_flush_pending_busy_v(void)
166{
167 return 0x00000001;
168}
169static inline u32 flush_fb_flush_pending_busy_f(void)
170{
171 return 0x1;
172}
173static inline u32 flush_fb_flush_outstanding_v(u32 r)
174{
175 return (r >> 1) & 0x1;
176}
177static inline u32 flush_fb_flush_outstanding_true_v(void)
178{
179 return 0x00000001;
180}
181#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h
new file mode 100644
index 00000000..0d4c0362
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fuse_gp106_h_
51#define _hw_fuse_gp106_h_
52
53static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
54{
55 return 0x00021c38 + i*4;
56}
57static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
58{
59 return 0x00021838 + i*4;
60}
61static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
62{
63 return 0x00021944;
64}
65static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
66{
67 return (v & 0x3) << 0;
68}
69static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
70{
71 return 0x3 << 0;
72}
73static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
74{
75 return (r >> 0) & 0x3;
76}
77static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
78{
79 return 0x00021948;
80}
81static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
82{
83 return (v & 0x1) << 0;
84}
85static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
86{
87 return 0x1 << 0;
88}
89static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
90{
91 return (r >> 0) & 0x1;
92}
93static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
94{
95 return 0x1;
96}
97static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
98{
99 return 0x0;
100}
101static inline u32 fuse_status_opt_fbio_r(void)
102{
103 return 0x00021c14;
104}
105static inline u32 fuse_status_opt_fbio_data_f(u32 v)
106{
107 return (v & 0xffff) << 0;
108}
109static inline u32 fuse_status_opt_fbio_data_m(void)
110{
111 return 0xffff << 0;
112}
113static inline u32 fuse_status_opt_fbio_data_v(u32 r)
114{
115 return (r >> 0) & 0xffff;
116}
117static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
118{
119 return 0x00021d70 + i*4;
120}
121static inline u32 fuse_status_opt_fbp_r(void)
122{
123 return 0x00021d38;
124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{
127 return (r >> (0 + i*0)) & 0x1;
128}
129#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h
new file mode 100644
index 00000000..96ab77df
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h
@@ -0,0 +1,1261 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gmmu_gp106_h_
51#define _hw_gmmu_gp106_h_
52
53static inline u32 gmmu_new_pde_is_pte_w(void)
54{
55 return 0;
56}
57static inline u32 gmmu_new_pde_is_pte_false_f(void)
58{
59 return 0x0;
60}
61static inline u32 gmmu_new_pde_aperture_w(void)
62{
63 return 0;
64}
65static inline u32 gmmu_new_pde_aperture_invalid_f(void)
66{
67 return 0x0;
68}
69static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
70{
71 return 0x2;
72}
73static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
74{
75 return 0x4;
76}
77static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
78{
79 return 0x6;
80}
81static inline u32 gmmu_new_pde_address_sys_f(u32 v)
82{
83 return (v & 0xffffff) << 8;
84}
85static inline u32 gmmu_new_pde_address_sys_w(void)
86{
87 return 0;
88}
89static inline u32 gmmu_new_pde_vol_w(void)
90{
91 return 0;
92}
93static inline u32 gmmu_new_pde_vol_true_f(void)
94{
95 return 0x8;
96}
97static inline u32 gmmu_new_pde_vol_false_f(void)
98{
99 return 0x0;
100}
101static inline u32 gmmu_new_pde_address_shift_v(void)
102{
103 return 0x0000000c;
104}
105static inline u32 gmmu_new_pde__size_v(void)
106{
107 return 0x00000008;
108}
109static inline u32 gmmu_new_dual_pde_is_pte_w(void)
110{
111 return 0;
112}
113static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
114{
115 return 0x0;
116}
117static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
118{
119 return 0;
120}
121static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
122{
123 return 0x0;
124}
125static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
126{
127 return 0x2;
128}
129static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
130{
131 return 0x4;
132}
133static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
134{
135 return 0x6;
136}
137static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
138{
139 return (v & 0xfffffff) << 4;
140}
141static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
142{
143 return 0;
144}
145static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
146{
147 return 2;
148}
149static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
150{
151 return 0x0;
152}
153static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
154{
155 return 0x2;
156}
157static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
158{
159 return 0x4;
160}
161static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
162{
163 return 0x6;
164}
165static inline u32 gmmu_new_dual_pde_vol_small_w(void)
166{
167 return 2;
168}
169static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
170{
171 return 0x8;
172}
173static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
174{
175 return 0x0;
176}
177static inline u32 gmmu_new_dual_pde_vol_big_w(void)
178{
179 return 0;
180}
181static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
182{
183 return 0x8;
184}
185static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
186{
187 return 0x0;
188}
189static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
190{
191 return (v & 0xffffff) << 8;
192}
193static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
194{
195 return 2;
196}
197static inline u32 gmmu_new_dual_pde_address_shift_v(void)
198{
199 return 0x0000000c;
200}
201static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
202{
203 return 0x00000008;
204}
205static inline u32 gmmu_new_dual_pde__size_v(void)
206{
207 return 0x00000010;
208}
209static inline u32 gmmu_new_pte__size_v(void)
210{
211 return 0x00000008;
212}
213static inline u32 gmmu_new_pte_valid_w(void)
214{
215 return 0;
216}
217static inline u32 gmmu_new_pte_valid_true_f(void)
218{
219 return 0x1;
220}
221static inline u32 gmmu_new_pte_valid_false_f(void)
222{
223 return 0x0;
224}
225static inline u32 gmmu_new_pte_privilege_w(void)
226{
227 return 0;
228}
229static inline u32 gmmu_new_pte_privilege_true_f(void)
230{
231 return 0x20;
232}
233static inline u32 gmmu_new_pte_privilege_false_f(void)
234{
235 return 0x0;
236}
237static inline u32 gmmu_new_pte_address_sys_f(u32 v)
238{
239 return (v & 0xffffff) << 8;
240}
241static inline u32 gmmu_new_pte_address_sys_w(void)
242{
243 return 0;
244}
245static inline u32 gmmu_new_pte_vol_w(void)
246{
247 return 0;
248}
249static inline u32 gmmu_new_pte_vol_true_f(void)
250{
251 return 0x8;
252}
253static inline u32 gmmu_new_pte_vol_false_f(void)
254{
255 return 0x0;
256}
257static inline u32 gmmu_new_pte_aperture_w(void)
258{
259 return 0;
260}
261static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
262{
263 return 0x0;
264}
265static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
266{
267 return 0x4;
268}
269static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
270{
271 return 0x6;
272}
273static inline u32 gmmu_new_pte_read_only_w(void)
274{
275 return 0;
276}
277static inline u32 gmmu_new_pte_read_only_true_f(void)
278{
279 return 0x40;
280}
281static inline u32 gmmu_new_pte_comptagline_f(u32 v)
282{
283 return (v & 0x3ffff) << 4;
284}
285static inline u32 gmmu_new_pte_comptagline_w(void)
286{
287 return 1;
288}
289static inline u32 gmmu_new_pte_kind_f(u32 v)
290{
291 return (v & 0xff) << 24;
292}
293static inline u32 gmmu_new_pte_kind_w(void)
294{
295 return 1;
296}
297static inline u32 gmmu_new_pte_address_shift_v(void)
298{
299 return 0x0000000c;
300}
301static inline u32 gmmu_pte_kind_f(u32 v)
302{
303 return (v & 0xff) << 4;
304}
305static inline u32 gmmu_pte_kind_w(void)
306{
307 return 1;
308}
309static inline u32 gmmu_pte_kind_invalid_v(void)
310{
311 return 0x000000ff;
312}
313static inline u32 gmmu_pte_kind_pitch_v(void)
314{
315 return 0x00000000;
316}
317static inline u32 gmmu_pte_kind_z16_v(void)
318{
319 return 0x00000001;
320}
321static inline u32 gmmu_pte_kind_z16_2c_v(void)
322{
323 return 0x00000002;
324}
325static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
326{
327 return 0x00000003;
328}
329static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
330{
331 return 0x00000004;
332}
333static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
334{
335 return 0x00000005;
336}
337static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
338{
339 return 0x00000006;
340}
341static inline u32 gmmu_pte_kind_z16_2z_v(void)
342{
343 return 0x00000007;
344}
345static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
346{
347 return 0x00000008;
348}
349static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
350{
351 return 0x00000009;
352}
353static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
354{
355 return 0x0000000a;
356}
357static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
358{
359 return 0x0000000b;
360}
361static inline u32 gmmu_pte_kind_z16_2cz_v(void)
362{
363 return 0x00000036;
364}
365static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
366{
367 return 0x00000037;
368}
369static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
370{
371 return 0x00000038;
372}
373static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
374{
375 return 0x00000039;
376}
377static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
378{
379 return 0x0000005f;
380}
381static inline u32 gmmu_pte_kind_z16_4cz_v(void)
382{
383 return 0x0000000c;
384}
385static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
386{
387 return 0x0000000d;
388}
389static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
390{
391 return 0x0000000e;
392}
393static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
394{
395 return 0x0000000f;
396}
397static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
398{
399 return 0x00000010;
400}
401static inline u32 gmmu_pte_kind_s8z24_v(void)
402{
403 return 0x00000011;
404}
405static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
406{
407 return 0x00000012;
408}
409static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
410{
411 return 0x00000013;
412}
413static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
414{
415 return 0x00000014;
416}
417static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
418{
419 return 0x00000015;
420}
421static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
422{
423 return 0x00000016;
424}
425static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
426{
427 return 0x00000017;
428}
429static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
430{
431 return 0x00000018;
432}
433static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
434{
435 return 0x00000019;
436}
437static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
438{
439 return 0x0000001a;
440}
441static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
442{
443 return 0x0000001b;
444}
445static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
446{
447 return 0x0000001c;
448}
449static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
450{
451 return 0x0000001d;
452}
453static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
454{
455 return 0x0000001e;
456}
457static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
458{
459 return 0x0000001f;
460}
461static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
462{
463 return 0x00000020;
464}
465static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
466{
467 return 0x00000021;
468}
469static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
470{
471 return 0x00000022;
472}
473static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
474{
475 return 0x00000023;
476}
477static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
478{
479 return 0x00000024;
480}
481static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
482{
483 return 0x00000025;
484}
485static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
486{
487 return 0x00000026;
488}
489static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
490{
491 return 0x00000027;
492}
493static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
494{
495 return 0x00000028;
496}
497static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
498{
499 return 0x00000029;
500}
501static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
502{
503 return 0x0000002e;
504}
505static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
506{
507 return 0x0000002f;
508}
509static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
510{
511 return 0x00000030;
512}
513static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
514{
515 return 0x00000031;
516}
517static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
518{
519 return 0x00000032;
520}
521static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
522{
523 return 0x00000033;
524}
525static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
526{
527 return 0x00000034;
528}
529static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
530{
531 return 0x00000035;
532}
533static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
534{
535 return 0x0000003a;
536}
537static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
538{
539 return 0x0000003b;
540}
541static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
542{
543 return 0x0000003c;
544}
545static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
546{
547 return 0x0000003d;
548}
549static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
550{
551 return 0x0000003e;
552}
553static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
554{
555 return 0x0000003f;
556}
557static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
558{
559 return 0x00000040;
560}
561static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
562{
563 return 0x00000041;
564}
565static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
566{
567 return 0x00000042;
568}
569static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
570{
571 return 0x00000043;
572}
573static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
574{
575 return 0x00000044;
576}
577static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
578{
579 return 0x00000045;
580}
581static inline u32 gmmu_pte_kind_z24s8_v(void)
582{
583 return 0x00000046;
584}
585static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
586{
587 return 0x00000047;
588}
589static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
590{
591 return 0x00000048;
592}
593static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
594{
595 return 0x00000049;
596}
597static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
598{
599 return 0x0000004a;
600}
601static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
602{
603 return 0x0000004b;
604}
605static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
606{
607 return 0x0000004c;
608}
609static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
610{
611 return 0x0000004d;
612}
613static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
614{
615 return 0x0000004e;
616}
617static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
618{
619 return 0x0000004f;
620}
621static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
622{
623 return 0x00000050;
624}
625static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
626{
627 return 0x00000051;
628}
629static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
630{
631 return 0x00000052;
632}
633static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
634{
635 return 0x00000053;
636}
637static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
638{
639 return 0x00000054;
640}
641static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
642{
643 return 0x00000055;
644}
645static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
646{
647 return 0x00000056;
648}
649static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
650{
651 return 0x00000057;
652}
653static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
654{
655 return 0x00000058;
656}
657static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
658{
659 return 0x00000059;
660}
661static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
662{
663 return 0x0000005a;
664}
665static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
666{
667 return 0x0000005b;
668}
669static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
670{
671 return 0x0000005c;
672}
673static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
674{
675 return 0x0000005d;
676}
677static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
678{
679 return 0x0000005e;
680}
681static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
682{
683 return 0x00000063;
684}
685static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
686{
687 return 0x00000064;
688}
689static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
690{
691 return 0x00000065;
692}
693static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
694{
695 return 0x00000066;
696}
697static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
698{
699 return 0x00000067;
700}
701static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
702{
703 return 0x00000068;
704}
705static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
706{
707 return 0x00000069;
708}
709static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
710{
711 return 0x0000006a;
712}
713static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
714{
715 return 0x0000006f;
716}
717static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
718{
719 return 0x00000070;
720}
721static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
722{
723 return 0x00000071;
724}
725static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
726{
727 return 0x00000072;
728}
729static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
730{
731 return 0x00000073;
732}
733static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
734{
735 return 0x00000074;
736}
737static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
738{
739 return 0x00000075;
740}
741static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
742{
743 return 0x00000076;
744}
745static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
746{
747 return 0x00000077;
748}
749static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
750{
751 return 0x00000078;
752}
753static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
754{
755 return 0x00000079;
756}
757static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
758{
759 return 0x0000007a;
760}
761static inline u32 gmmu_pte_kind_zf32_v(void)
762{
763 return 0x0000007b;
764}
765static inline u32 gmmu_pte_kind_zf32_1z_v(void)
766{
767 return 0x0000007c;
768}
769static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
770{
771 return 0x0000007d;
772}
773static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
774{
775 return 0x0000007e;
776}
777static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
778{
779 return 0x0000007f;
780}
781static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
782{
783 return 0x00000080;
784}
785static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
786{
787 return 0x00000081;
788}
789static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
790{
791 return 0x00000082;
792}
793static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
794{
795 return 0x00000083;
796}
797static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
798{
799 return 0x00000084;
800}
801static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
802{
803 return 0x00000085;
804}
805static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
806{
807 return 0x00000086;
808}
809static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
810{
811 return 0x00000087;
812}
813static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
814{
815 return 0x00000088;
816}
817static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
818{
819 return 0x00000089;
820}
821static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
822{
823 return 0x0000008a;
824}
825static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
826{
827 return 0x0000008b;
828}
829static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
830{
831 return 0x0000008c;
832}
833static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
834{
835 return 0x0000008d;
836}
837static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
838{
839 return 0x0000008e;
840}
841static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
842{
843 return 0x0000008f;
844}
845static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
846{
847 return 0x00000090;
848}
849static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
850{
851 return 0x00000091;
852}
853static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
854{
855 return 0x00000092;
856}
857static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
858{
859 return 0x00000097;
860}
861static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
862{
863 return 0x00000098;
864}
865static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
866{
867 return 0x00000099;
868}
869static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
870{
871 return 0x0000009a;
872}
873static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
874{
875 return 0x0000009b;
876}
877static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
878{
879 return 0x0000009c;
880}
881static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
882{
883 return 0x0000009d;
884}
885static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
886{
887 return 0x0000009e;
888}
889static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
890{
891 return 0x0000009f;
892}
893static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
894{
895 return 0x000000a0;
896}
897static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
898{
899 return 0x000000a1;
900}
901static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
902{
903 return 0x000000a2;
904}
905static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
906{
907 return 0x000000a3;
908}
909static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
910{
911 return 0x000000a4;
912}
913static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
914{
915 return 0x000000a5;
916}
917static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
918{
919 return 0x000000a6;
920}
921static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
922{
923 return 0x000000a7;
924}
925static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
926{
927 return 0x000000a8;
928}
929static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
930{
931 return 0x000000a9;
932}
933static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
934{
935 return 0x000000aa;
936}
937static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
938{
939 return 0x000000ab;
940}
941static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
942{
943 return 0x000000ac;
944}
945static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
946{
947 return 0x000000ad;
948}
949static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
950{
951 return 0x000000ae;
952}
953static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
954{
955 return 0x000000b3;
956}
957static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
958{
959 return 0x000000b4;
960}
961static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
962{
963 return 0x000000b5;
964}
965static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
966{
967 return 0x000000b6;
968}
969static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
970{
971 return 0x000000b7;
972}
973static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
974{
975 return 0x000000b8;
976}
977static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
978{
979 return 0x000000b9;
980}
981static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
982{
983 return 0x000000ba;
984}
985static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
986{
987 return 0x000000bb;
988}
989static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
990{
991 return 0x000000bc;
992}
993static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
994{
995 return 0x000000bd;
996}
997static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
998{
999 return 0x000000be;
1000}
1001static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
1002{
1003 return 0x000000bf;
1004}
1005static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
1006{
1007 return 0x000000c0;
1008}
1009static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
1010{
1011 return 0x000000c1;
1012}
1013static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
1014{
1015 return 0x000000c2;
1016}
1017static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
1018{
1019 return 0x000000c3;
1020}
1021static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
1022{
1023 return 0x000000c4;
1024}
1025static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
1026{
1027 return 0x000000c5;
1028}
1029static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
1030{
1031 return 0x000000c6;
1032}
1033static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
1034{
1035 return 0x000000c7;
1036}
1037static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
1038{
1039 return 0x000000c8;
1040}
1041static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
1042{
1043 return 0x000000ce;
1044}
1045static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
1046{
1047 return 0x000000cf;
1048}
1049static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
1050{
1051 return 0x000000d0;
1052}
1053static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1054{
1055 return 0x000000d1;
1056}
1057static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1058{
1059 return 0x000000d2;
1060}
1061static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1062{
1063 return 0x000000d3;
1064}
1065static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1066{
1067 return 0x000000d4;
1068}
1069static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1070{
1071 return 0x000000d5;
1072}
1073static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1074{
1075 return 0x000000d6;
1076}
1077static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1078{
1079 return 0x000000d7;
1080}
1081static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1082{
1083 return 0x000000fe;
1084}
1085static inline u32 gmmu_pte_kind_c32_2c_v(void)
1086{
1087 return 0x000000d8;
1088}
1089static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1090{
1091 return 0x000000d9;
1092}
1093static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1094{
1095 return 0x000000da;
1096}
1097static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1098{
1099 return 0x000000db;
1100}
1101static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1102{
1103 return 0x000000dc;
1104}
1105static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1106{
1107 return 0x000000dd;
1108}
1109static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1110{
1111 return 0x000000de;
1112}
1113static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1114{
1115 return 0x000000df;
1116}
1117static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1118{
1119 return 0x000000e0;
1120}
1121static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1122{
1123 return 0x000000e1;
1124}
1125static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1126{
1127 return 0x000000e2;
1128}
1129static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1130{
1131 return 0x000000e3;
1132}
1133static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
1134{
1135 return 0x0000002c;
1136}
1137static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1138{
1139 return 0x000000e4;
1140}
1141static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1142{
1143 return 0x000000e5;
1144}
1145static inline u32 gmmu_pte_kind_c64_2c_v(void)
1146{
1147 return 0x000000e6;
1148}
1149static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1150{
1151 return 0x000000e7;
1152}
1153static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1154{
1155 return 0x000000e8;
1156}
1157static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1158{
1159 return 0x000000e9;
1160}
1161static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1162{
1163 return 0x000000ea;
1164}
1165static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1166{
1167 return 0x000000eb;
1168}
1169static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1170{
1171 return 0x000000ec;
1172}
1173static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1174{
1175 return 0x000000ed;
1176}
1177static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1178{
1179 return 0x000000ee;
1180}
1181static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1182{
1183 return 0x000000ef;
1184}
1185static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1186{
1187 return 0x000000f0;
1188}
1189static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1190{
1191 return 0x000000f1;
1192}
1193static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
1194{
1195 return 0x0000002d;
1196}
1197static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1198{
1199 return 0x000000f2;
1200}
1201static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1202{
1203 return 0x000000f3;
1204}
1205static inline u32 gmmu_pte_kind_c128_2c_v(void)
1206{
1207 return 0x000000f4;
1208}
1209static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1210{
1211 return 0x000000f5;
1212}
1213static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1214{
1215 return 0x000000f6;
1216}
1217static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1218{
1219 return 0x000000f7;
1220}
1221static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1222{
1223 return 0x000000f8;
1224}
1225static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1226{
1227 return 0x000000f9;
1228}
1229static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1230{
1231 return 0x000000fa;
1232}
1233static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1234{
1235 return 0x000000fb;
1236}
1237static inline u32 gmmu_pte_kind_x8c24_v(void)
1238{
1239 return 0x000000fc;
1240}
1241static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1242{
1243 return 0x000000fd;
1244}
1245static inline u32 gmmu_pte_kind_smsked_message_v(void)
1246{
1247 return 0x000000ca;
1248}
1249static inline u32 gmmu_pte_kind_smhost_message_v(void)
1250{
1251 return 0x000000cb;
1252}
1253static inline u32 gmmu_pte_kind_s8_v(void)
1254{
1255 return 0x0000002a;
1256}
1257static inline u32 gmmu_pte_kind_s8_2s_v(void)
1258{
1259 return 0x0000002b;
1260}
1261#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h
new file mode 100644
index 00000000..e5e1c527
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h
@@ -0,0 +1,4001 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gr_gp106_h_
51#define _hw_gr_gp106_h_
52
53static inline u32 gr_intr_r(void)
54{
55 return 0x00400100;
56}
57static inline u32 gr_intr_notify_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 gr_intr_notify_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 gr_intr_semaphore_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 gr_intr_semaphore_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 gr_intr_illegal_method_pending_f(void)
74{
75 return 0x10;
76}
77static inline u32 gr_intr_illegal_method_reset_f(void)
78{
79 return 0x10;
80}
81static inline u32 gr_intr_illegal_notify_pending_f(void)
82{
83 return 0x40;
84}
85static inline u32 gr_intr_illegal_notify_reset_f(void)
86{
87 return 0x40;
88}
89static inline u32 gr_intr_firmware_method_f(u32 v)
90{
91 return (v & 0x1) << 8;
92}
93static inline u32 gr_intr_firmware_method_pending_f(void)
94{
95 return 0x100;
96}
97static inline u32 gr_intr_firmware_method_reset_f(void)
98{
99 return 0x100;
100}
101static inline u32 gr_intr_illegal_class_pending_f(void)
102{
103 return 0x20;
104}
105static inline u32 gr_intr_illegal_class_reset_f(void)
106{
107 return 0x20;
108}
109static inline u32 gr_intr_fecs_error_pending_f(void)
110{
111 return 0x80000;
112}
113static inline u32 gr_intr_fecs_error_reset_f(void)
114{
115 return 0x80000;
116}
117static inline u32 gr_intr_class_error_pending_f(void)
118{
119 return 0x100000;
120}
121static inline u32 gr_intr_class_error_reset_f(void)
122{
123 return 0x100000;
124}
125static inline u32 gr_intr_exception_pending_f(void)
126{
127 return 0x200000;
128}
129static inline u32 gr_intr_exception_reset_f(void)
130{
131 return 0x200000;
132}
133static inline u32 gr_fecs_intr_r(void)
134{
135 return 0x00400144;
136}
137static inline u32 gr_class_error_r(void)
138{
139 return 0x00400110;
140}
141static inline u32 gr_class_error_code_v(u32 r)
142{
143 return (r >> 0) & 0xffff;
144}
145static inline u32 gr_intr_nonstall_r(void)
146{
147 return 0x00400120;
148}
149static inline u32 gr_intr_nonstall_trap_pending_f(void)
150{
151 return 0x2;
152}
153static inline u32 gr_intr_en_r(void)
154{
155 return 0x0040013c;
156}
157static inline u32 gr_exception_r(void)
158{
159 return 0x00400108;
160}
161static inline u32 gr_exception_fe_m(void)
162{
163 return 0x1 << 0;
164}
165static inline u32 gr_exception_gpc_m(void)
166{
167 return 0x1 << 24;
168}
169static inline u32 gr_exception_memfmt_m(void)
170{
171 return 0x1 << 1;
172}
173static inline u32 gr_exception_ds_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 gr_exception1_r(void)
178{
179 return 0x00400118;
180}
181static inline u32 gr_exception1_gpc_0_pending_f(void)
182{
183 return 0x1;
184}
185static inline u32 gr_exception2_r(void)
186{
187 return 0x0040011c;
188}
189static inline u32 gr_exception_en_r(void)
190{
191 return 0x00400138;
192}
193static inline u32 gr_exception_en_fe_m(void)
194{
195 return 0x1 << 0;
196}
197static inline u32 gr_exception1_en_r(void)
198{
199 return 0x00400130;
200}
201static inline u32 gr_exception2_en_r(void)
202{
203 return 0x00400134;
204}
205static inline u32 gr_gpfifo_ctl_r(void)
206{
207 return 0x00400500;
208}
209static inline u32 gr_gpfifo_ctl_access_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
214{
215 return 0x0;
216}
217static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
218{
219 return 0x1;
220}
221static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
222{
223 return (v & 0x1) << 16;
224}
225static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
226{
227 return 0x00000001;
228}
229static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
230{
231 return 0x10000;
232}
233static inline u32 gr_gpfifo_status_r(void)
234{
235 return 0x00400504;
236}
237static inline u32 gr_trapped_addr_r(void)
238{
239 return 0x00400704;
240}
241static inline u32 gr_trapped_addr_mthd_v(u32 r)
242{
243 return (r >> 2) & 0xfff;
244}
245static inline u32 gr_trapped_addr_subch_v(u32 r)
246{
247 return (r >> 16) & 0x7;
248}
249static inline u32 gr_trapped_data_lo_r(void)
250{
251 return 0x00400708;
252}
253static inline u32 gr_trapped_data_hi_r(void)
254{
255 return 0x0040070c;
256}
257static inline u32 gr_status_r(void)
258{
259 return 0x00400700;
260}
261static inline u32 gr_status_fe_method_upper_v(u32 r)
262{
263 return (r >> 1) & 0x1;
264}
265static inline u32 gr_status_fe_method_lower_v(u32 r)
266{
267 return (r >> 2) & 0x1;
268}
269static inline u32 gr_status_fe_method_lower_idle_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 gr_status_fe_gi_v(u32 r)
274{
275 return (r >> 21) & 0x1;
276}
277static inline u32 gr_status_mask_r(void)
278{
279 return 0x00400610;
280}
281static inline u32 gr_status_1_r(void)
282{
283 return 0x00400604;
284}
285static inline u32 gr_status_2_r(void)
286{
287 return 0x00400608;
288}
289static inline u32 gr_engine_status_r(void)
290{
291 return 0x0040060c;
292}
293static inline u32 gr_engine_status_value_busy_f(void)
294{
295 return 0x1;
296}
297static inline u32 gr_pri_be0_becs_be_exception_r(void)
298{
299 return 0x00410204;
300}
301static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
302{
303 return 0x00410208;
304}
305static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
306{
307 return 0x00502c90;
308}
309static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
310{
311 return 0x00502c94;
312}
313static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
314{
315 return 0x00504508;
316}
317static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
318{
319 return 0x0050450c;
320}
321static inline u32 gr_activity_0_r(void)
322{
323 return 0x00400380;
324}
325static inline u32 gr_activity_1_r(void)
326{
327 return 0x00400384;
328}
329static inline u32 gr_activity_2_r(void)
330{
331 return 0x00400388;
332}
333static inline u32 gr_activity_4_r(void)
334{
335 return 0x00400390;
336}
337static inline u32 gr_activity_4_gpc0_s(void)
338{
339 return 3;
340}
341static inline u32 gr_activity_4_gpc0_f(u32 v)
342{
343 return (v & 0x7) << 0;
344}
345static inline u32 gr_activity_4_gpc0_m(void)
346{
347 return 0x7 << 0;
348}
349static inline u32 gr_activity_4_gpc0_v(u32 r)
350{
351 return (r >> 0) & 0x7;
352}
353static inline u32 gr_activity_4_gpc0_empty_v(void)
354{
355 return 0x00000000;
356}
357static inline u32 gr_activity_4_gpc0_preempted_v(void)
358{
359 return 0x00000004;
360}
361static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
362{
363 return 0x00501000;
364}
365static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
366{
367 return 0x00419000;
368}
369static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
370{
371 return 0x1 << 1;
372}
373static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
374{
375 return 0x005046a4;
376}
377static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
378{
379 return 0x00419ea4;
380}
381static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
382{
383 return 0x1 << 0;
384}
385static inline u32 gr_pri_sked_activity_r(void)
386{
387 return 0x00407054;
388}
389static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
390{
391 return 0x00502c80;
392}
393static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
394{
395 return 0x00502c84;
396}
397static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
398{
399 return 0x00502c88;
400}
401static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
402{
403 return 0x00502c8c;
404}
405static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
406{
407 return 0x00504500;
408}
409static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
410{
411 return 0x00504d00;
412}
413static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
414{
415 return 0x00501d00;
416}
417static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
418{
419 return 0x0041ac80;
420}
421static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
422{
423 return 0x0041ac84;
424}
425static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
426{
427 return 0x0041ac88;
428}
429static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
430{
431 return 0x0041ac8c;
432}
433static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
434{
435 return 0x0041c500;
436}
437static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
438{
439 return 0x0041cd00;
440}
441static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
442{
443 return 0x00419d00;
444}
445static inline u32 gr_pri_be0_becs_be_activity0_r(void)
446{
447 return 0x00410200;
448}
449static inline u32 gr_pri_be1_becs_be_activity0_r(void)
450{
451 return 0x00410600;
452}
453static inline u32 gr_pri_bes_becs_be_activity0_r(void)
454{
455 return 0x00408a00;
456}
457static inline u32 gr_pri_ds_mpipe_status_r(void)
458{
459 return 0x00405858;
460}
461static inline u32 gr_pri_fe_go_idle_info_r(void)
462{
463 return 0x00404194;
464}
465static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
466{
467 return 0x00504238;
468}
469static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
470{
471 return 0x005046b8;
472}
473static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
474{
475 return 0x10;
476}
477static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
478{
479 return 0x20;
480}
481static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
482{
483 return 0x40;
484}
485static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
486{
487 return 0x80;
488}
489static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
490{
491 return 0x100;
492}
493static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
494{
495 return 0x200;
496}
497static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
498{
499 return 0x400;
500}
501static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
502{
503 return 0x800;
504}
505static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
506{
507 return 0x005044a0;
508}
509static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
510{
511 return 0x1;
512}
513static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
514{
515 return 0x2;
516}
517static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
518{
519 return 0x10;
520}
521static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
522{
523 return 0x20;
524}
525static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
526{
527 return 0x100;
528}
529static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
530{
531 return 0x200;
532}
533static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
534{
535 return 0x005046bc;
536}
537static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
538{
539 return 0x005046c0;
540}
541static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
542{
543 return 0x005044a4;
544}
545static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
546{
547 return 0xff << 0;
548}
549static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
550{
551 return (r >> 0) & 0xff;
552}
553static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
554{
555 return 0xff << 8;
556}
557static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
558{
559 return (r >> 8) & 0xff;
560}
561static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
562{
563 return 0xff << 16;
564}
565static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
566{
567 return (r >> 16) & 0xff;
568}
569static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
570{
571 return 0x005042c4;
572}
573static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
574{
575 return 0x0;
576}
577static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
578{
579 return 0x1;
580}
581static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
582{
583 return 0x2;
584}
585static inline u32 gr_pri_be0_crop_status1_r(void)
586{
587 return 0x00410134;
588}
589static inline u32 gr_pri_bes_crop_status1_r(void)
590{
591 return 0x00408934;
592}
593static inline u32 gr_pri_be0_zrop_status_r(void)
594{
595 return 0x00410048;
596}
597static inline u32 gr_pri_be0_zrop_status2_r(void)
598{
599 return 0x0041004c;
600}
601static inline u32 gr_pri_bes_zrop_status_r(void)
602{
603 return 0x00408848;
604}
605static inline u32 gr_pri_bes_zrop_status2_r(void)
606{
607 return 0x0040884c;
608}
609static inline u32 gr_pipe_bundle_address_r(void)
610{
611 return 0x00400200;
612}
613static inline u32 gr_pipe_bundle_address_value_v(u32 r)
614{
615 return (r >> 0) & 0xffff;
616}
617static inline u32 gr_pipe_bundle_data_r(void)
618{
619 return 0x00400204;
620}
621static inline u32 gr_pipe_bundle_config_r(void)
622{
623 return 0x00400208;
624}
625static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
626{
627 return 0x0;
628}
629static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
630{
631 return 0x80000000;
632}
633static inline u32 gr_fe_hww_esr_r(void)
634{
635 return 0x00404000;
636}
637static inline u32 gr_fe_hww_esr_reset_active_f(void)
638{
639 return 0x40000000;
640}
641static inline u32 gr_fe_hww_esr_en_enable_f(void)
642{
643 return 0x80000000;
644}
645static inline u32 gr_fe_go_idle_timeout_r(void)
646{
647 return 0x00404154;
648}
649static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
650{
651 return (v & 0xffffffff) << 0;
652}
653static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
654{
655 return 0x0;
656}
657static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
658{
659 return 0x1800;
660}
661static inline u32 gr_fe_object_table_r(u32 i)
662{
663 return 0x00404200 + i*4;
664}
665static inline u32 gr_fe_object_table_nvclass_v(u32 r)
666{
667 return (r >> 0) & 0xffff;
668}
669static inline u32 gr_fe_tpc_fs_r(void)
670{
671 return 0x004041c4;
672}
673static inline u32 gr_pri_mme_shadow_raw_index_r(void)
674{
675 return 0x00404488;
676}
677static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
678{
679 return 0x80000000;
680}
681static inline u32 gr_pri_mme_shadow_raw_data_r(void)
682{
683 return 0x0040448c;
684}
685static inline u32 gr_mme_hww_esr_r(void)
686{
687 return 0x00404490;
688}
689static inline u32 gr_mme_hww_esr_reset_active_f(void)
690{
691 return 0x40000000;
692}
693static inline u32 gr_mme_hww_esr_en_enable_f(void)
694{
695 return 0x80000000;
696}
697static inline u32 gr_memfmt_hww_esr_r(void)
698{
699 return 0x00404600;
700}
701static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
702{
703 return 0x40000000;
704}
705static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
706{
707 return 0x80000000;
708}
709static inline u32 gr_fecs_cpuctl_r(void)
710{
711 return 0x00409100;
712}
713static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
714{
715 return (v & 0x1) << 1;
716}
717static inline u32 gr_fecs_cpuctl_alias_r(void)
718{
719 return 0x00409130;
720}
721static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
722{
723 return (v & 0x1) << 1;
724}
725static inline u32 gr_fecs_dmactl_r(void)
726{
727 return 0x0040910c;
728}
729static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
730{
731 return (v & 0x1) << 0;
732}
733static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
734{
735 return 0x1 << 1;
736}
737static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
738{
739 return 0x1 << 2;
740}
741static inline u32 gr_fecs_os_r(void)
742{
743 return 0x00409080;
744}
745static inline u32 gr_fecs_idlestate_r(void)
746{
747 return 0x0040904c;
748}
749static inline u32 gr_fecs_mailbox0_r(void)
750{
751 return 0x00409040;
752}
753static inline u32 gr_fecs_mailbox1_r(void)
754{
755 return 0x00409044;
756}
757static inline u32 gr_fecs_irqstat_r(void)
758{
759 return 0x00409008;
760}
761static inline u32 gr_fecs_irqmode_r(void)
762{
763 return 0x0040900c;
764}
765static inline u32 gr_fecs_irqmask_r(void)
766{
767 return 0x00409018;
768}
769static inline u32 gr_fecs_irqdest_r(void)
770{
771 return 0x0040901c;
772}
773static inline u32 gr_fecs_curctx_r(void)
774{
775 return 0x00409050;
776}
777static inline u32 gr_fecs_nxtctx_r(void)
778{
779 return 0x00409054;
780}
781static inline u32 gr_fecs_engctl_r(void)
782{
783 return 0x004090a4;
784}
785static inline u32 gr_fecs_debug1_r(void)
786{
787 return 0x00409090;
788}
789static inline u32 gr_fecs_debuginfo_r(void)
790{
791 return 0x00409094;
792}
793static inline u32 gr_fecs_icd_cmd_r(void)
794{
795 return 0x00409200;
796}
797static inline u32 gr_fecs_icd_cmd_opc_s(void)
798{
799 return 4;
800}
801static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
802{
803 return (v & 0xf) << 0;
804}
805static inline u32 gr_fecs_icd_cmd_opc_m(void)
806{
807 return 0xf << 0;
808}
809static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
810{
811 return (r >> 0) & 0xf;
812}
813static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
814{
815 return 0x8;
816}
817static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
818{
819 return 0xe;
820}
821static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
822{
823 return (v & 0x1f) << 8;
824}
825static inline u32 gr_fecs_icd_rdata_r(void)
826{
827 return 0x0040920c;
828}
829static inline u32 gr_fecs_imemc_r(u32 i)
830{
831 return 0x00409180 + i*16;
832}
833static inline u32 gr_fecs_imemc_offs_f(u32 v)
834{
835 return (v & 0x3f) << 2;
836}
837static inline u32 gr_fecs_imemc_blk_f(u32 v)
838{
839 return (v & 0xff) << 8;
840}
841static inline u32 gr_fecs_imemc_aincw_f(u32 v)
842{
843 return (v & 0x1) << 24;
844}
845static inline u32 gr_fecs_imemd_r(u32 i)
846{
847 return 0x00409184 + i*16;
848}
849static inline u32 gr_fecs_imemt_r(u32 i)
850{
851 return 0x00409188 + i*16;
852}
853static inline u32 gr_fecs_imemt_tag_f(u32 v)
854{
855 return (v & 0xffff) << 0;
856}
857static inline u32 gr_fecs_dmemc_r(u32 i)
858{
859 return 0x004091c0 + i*8;
860}
861static inline u32 gr_fecs_dmemc_offs_s(void)
862{
863 return 6;
864}
865static inline u32 gr_fecs_dmemc_offs_f(u32 v)
866{
867 return (v & 0x3f) << 2;
868}
869static inline u32 gr_fecs_dmemc_offs_m(void)
870{
871 return 0x3f << 2;
872}
873static inline u32 gr_fecs_dmemc_offs_v(u32 r)
874{
875 return (r >> 2) & 0x3f;
876}
877static inline u32 gr_fecs_dmemc_blk_f(u32 v)
878{
879 return (v & 0xff) << 8;
880}
881static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
882{
883 return (v & 0x1) << 24;
884}
885static inline u32 gr_fecs_dmemd_r(u32 i)
886{
887 return 0x004091c4 + i*8;
888}
889static inline u32 gr_fecs_dmatrfbase_r(void)
890{
891 return 0x00409110;
892}
893static inline u32 gr_fecs_dmatrfmoffs_r(void)
894{
895 return 0x00409114;
896}
897static inline u32 gr_fecs_dmatrffboffs_r(void)
898{
899 return 0x0040911c;
900}
901static inline u32 gr_fecs_dmatrfcmd_r(void)
902{
903 return 0x00409118;
904}
905static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
906{
907 return (v & 0x1) << 4;
908}
909static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
910{
911 return (v & 0x1) << 5;
912}
913static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
914{
915 return (v & 0x7) << 8;
916}
917static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
918{
919 return (v & 0x7) << 12;
920}
921static inline u32 gr_fecs_bootvec_r(void)
922{
923 return 0x00409104;
924}
925static inline u32 gr_fecs_bootvec_vec_f(u32 v)
926{
927 return (v & 0xffffffff) << 0;
928}
929static inline u32 gr_fecs_falcon_hwcfg_r(void)
930{
931 return 0x00409108;
932}
933static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
934{
935 return 0x0041a108;
936}
937static inline u32 gr_fecs_falcon_rm_r(void)
938{
939 return 0x00409084;
940}
941static inline u32 gr_fecs_current_ctx_r(void)
942{
943 return 0x00409b00;
944}
945static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
946{
947 return (v & 0xfffffff) << 0;
948}
949static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
950{
951 return (r >> 0) & 0xfffffff;
952}
953static inline u32 gr_fecs_current_ctx_target_s(void)
954{
955 return 2;
956}
957static inline u32 gr_fecs_current_ctx_target_f(u32 v)
958{
959 return (v & 0x3) << 28;
960}
961static inline u32 gr_fecs_current_ctx_target_m(void)
962{
963 return 0x3 << 28;
964}
965static inline u32 gr_fecs_current_ctx_target_v(u32 r)
966{
967 return (r >> 28) & 0x3;
968}
969static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
970{
971 return 0x0;
972}
973static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
974{
975 return 0x20000000;
976}
977static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
978{
979 return 0x30000000;
980}
981static inline u32 gr_fecs_current_ctx_valid_s(void)
982{
983 return 1;
984}
985static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
986{
987 return (v & 0x1) << 31;
988}
989static inline u32 gr_fecs_current_ctx_valid_m(void)
990{
991 return 0x1 << 31;
992}
993static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
994{
995 return (r >> 31) & 0x1;
996}
997static inline u32 gr_fecs_current_ctx_valid_false_f(void)
998{
999 return 0x0;
1000}
1001static inline u32 gr_fecs_method_data_r(void)
1002{
1003 return 0x00409500;
1004}
1005static inline u32 gr_fecs_method_push_r(void)
1006{
1007 return 0x00409504;
1008}
1009static inline u32 gr_fecs_method_push_adr_f(u32 v)
1010{
1011 return (v & 0xfff) << 0;
1012}
1013static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
1014{
1015 return 0x00000003;
1016}
1017static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
1018{
1019 return 0x3;
1020}
1021static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
1022{
1023 return 0x00000010;
1024}
1025static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
1026{
1027 return 0x00000009;
1028}
1029static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
1030{
1031 return 0x00000015;
1032}
1033static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
1034{
1035 return 0x00000016;
1036}
1037static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
1038{
1039 return 0x00000025;
1040}
1041static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
1042{
1043 return 0x00000030;
1044}
1045static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
1046{
1047 return 0x00000031;
1048}
1049static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
1050{
1051 return 0x00000032;
1052}
1053static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
1054{
1055 return 0x00000038;
1056}
1057static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
1058{
1059 return 0x00000039;
1060}
1061static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
1062{
1063 return 0x21;
1064}
1065static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
1066{
1067 return 0x0000001a;
1068}
1069static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
1070{
1071 return 0x00000004;
1072}
1073static inline u32 gr_fecs_host_int_status_r(void)
1074{
1075 return 0x00409c18;
1076}
1077static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
1078{
1079 return (v & 0x1) << 16;
1080}
1081static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
1082{
1083 return (v & 0x1) << 17;
1084}
1085static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
1086{
1087 return (v & 0x1) << 18;
1088}
1089static inline u32 gr_fecs_host_int_clear_r(void)
1090{
1091 return 0x00409c20;
1092}
1093static inline u32 gr_fecs_host_int_enable_r(void)
1094{
1095 return 0x00409c24;
1096}
1097static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1098{
1099 return 0x10000;
1100}
1101static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1102{
1103 return 0x20000;
1104}
1105static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1106{
1107 return 0x40000;
1108}
1109static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1110{
1111 return 0x80000;
1112}
1113static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1114{
1115 return 0x00409614;
1116}
1117static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1118{
1119 return 0x0;
1120}
1121static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1122{
1123 return 0x0;
1124}
1125static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1126{
1127 return 0x0;
1128}
1129static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1130{
1131 return 0x10;
1132}
1133static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1134{
1135 return 0x20;
1136}
1137static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1138{
1139 return 0x40;
1140}
1141static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1142{
1143 return 0x0;
1144}
1145static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1146{
1147 return 0x100;
1148}
1149static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1150{
1151 return 0x0;
1152}
1153static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1154{
1155 return 0x200;
1156}
1157static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1158{
1159 return 1;
1160}
1161static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1162{
1163 return (v & 0x1) << 10;
1164}
1165static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1166{
1167 return 0x1 << 10;
1168}
1169static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1170{
1171 return (r >> 10) & 0x1;
1172}
1173static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1174{
1175 return 0x0;
1176}
1177static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1178{
1179 return 0x400;
1180}
1181static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1182{
1183 return 0x0040960c;
1184}
1185static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1186{
1187 return 0x00409800 + i*4;
1188}
1189static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1190{
1191 return 0x00000010;
1192}
1193static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1194{
1195 return (v & 0xffffffff) << 0;
1196}
1197static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1198{
1199 return 0x00000001;
1200}
1201static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1202{
1203 return 0x00000002;
1204}
1205static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1206{
1207 return 0x004098c0 + i*4;
1208}
1209static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1210{
1211 return (v & 0xffffffff) << 0;
1212}
1213static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1214{
1215 return 0x00409840 + i*4;
1216}
1217static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1218{
1219 return (v & 0xffffffff) << 0;
1220}
1221static inline u32 gr_fecs_fs_r(void)
1222{
1223 return 0x00409604;
1224}
1225static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1226{
1227 return 5;
1228}
1229static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1230{
1231 return (v & 0x1f) << 0;
1232}
1233static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1234{
1235 return 0x1f << 0;
1236}
1237static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1238{
1239 return (r >> 0) & 0x1f;
1240}
1241static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1242{
1243 return 5;
1244}
1245static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1246{
1247 return (v & 0x1f) << 16;
1248}
1249static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1250{
1251 return 0x1f << 16;
1252}
1253static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1254{
1255 return (r >> 16) & 0x1f;
1256}
1257static inline u32 gr_fecs_cfg_r(void)
1258{
1259 return 0x00409620;
1260}
1261static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1262{
1263 return (r >> 0) & 0xff;
1264}
1265static inline u32 gr_fecs_rc_lanes_r(void)
1266{
1267 return 0x00409880;
1268}
1269static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1270{
1271 return 6;
1272}
1273static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1274{
1275 return (v & 0x3f) << 0;
1276}
1277static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1278{
1279 return 0x3f << 0;
1280}
1281static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1282{
1283 return (r >> 0) & 0x3f;
1284}
1285static inline u32 gr_fecs_ctxsw_status_1_r(void)
1286{
1287 return 0x00409400;
1288}
1289static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1290{
1291 return 1;
1292}
1293static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1294{
1295 return (v & 0x1) << 12;
1296}
1297static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1298{
1299 return 0x1 << 12;
1300}
1301static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1302{
1303 return (r >> 12) & 0x1;
1304}
1305static inline u32 gr_fecs_arb_ctx_adr_r(void)
1306{
1307 return 0x00409a24;
1308}
1309static inline u32 gr_fecs_new_ctx_r(void)
1310{
1311 return 0x00409b04;
1312}
1313static inline u32 gr_fecs_new_ctx_ptr_s(void)
1314{
1315 return 28;
1316}
1317static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1318{
1319 return (v & 0xfffffff) << 0;
1320}
1321static inline u32 gr_fecs_new_ctx_ptr_m(void)
1322{
1323 return 0xfffffff << 0;
1324}
1325static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1326{
1327 return (r >> 0) & 0xfffffff;
1328}
1329static inline u32 gr_fecs_new_ctx_target_s(void)
1330{
1331 return 2;
1332}
1333static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1334{
1335 return (v & 0x3) << 28;
1336}
1337static inline u32 gr_fecs_new_ctx_target_m(void)
1338{
1339 return 0x3 << 28;
1340}
1341static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1342{
1343 return (r >> 28) & 0x3;
1344}
1345static inline u32 gr_fecs_new_ctx_valid_s(void)
1346{
1347 return 1;
1348}
1349static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1350{
1351 return (v & 0x1) << 31;
1352}
1353static inline u32 gr_fecs_new_ctx_valid_m(void)
1354{
1355 return 0x1 << 31;
1356}
1357static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1358{
1359 return (r >> 31) & 0x1;
1360}
1361static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1362{
1363 return 0x00409a0c;
1364}
1365static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1366{
1367 return 28;
1368}
1369static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1370{
1371 return (v & 0xfffffff) << 0;
1372}
1373static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1374{
1375 return 0xfffffff << 0;
1376}
1377static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1378{
1379 return (r >> 0) & 0xfffffff;
1380}
1381static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1382{
1383 return 2;
1384}
1385static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1386{
1387 return (v & 0x3) << 28;
1388}
1389static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1390{
1391 return 0x3 << 28;
1392}
1393static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1394{
1395 return (r >> 28) & 0x3;
1396}
1397static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1398{
1399 return 0x00409a10;
1400}
1401static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1402{
1403 return 5;
1404}
1405static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1406{
1407 return (v & 0x1f) << 0;
1408}
1409static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1410{
1411 return 0x1f << 0;
1412}
1413static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1414{
1415 return (r >> 0) & 0x1f;
1416}
1417static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1418{
1419 return 0x00409c00;
1420}
1421static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1422{
1423 return 0x00502c04;
1424}
1425static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1426{
1427 return 0x00502400;
1428}
1429static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1430{
1431 return 0x00409420;
1432}
1433static inline u32 gr_fecs_feature_override_ecc_r(void)
1434{
1435 return 0x00409658;
1436}
1437static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1438{
1439 return 0x00502420;
1440}
1441static inline u32 gr_rstr2d_gpc_map0_r(void)
1442{
1443 return 0x0040780c;
1444}
1445static inline u32 gr_rstr2d_gpc_map1_r(void)
1446{
1447 return 0x00407810;
1448}
1449static inline u32 gr_rstr2d_gpc_map2_r(void)
1450{
1451 return 0x00407814;
1452}
1453static inline u32 gr_rstr2d_gpc_map3_r(void)
1454{
1455 return 0x00407818;
1456}
1457static inline u32 gr_rstr2d_gpc_map4_r(void)
1458{
1459 return 0x0040781c;
1460}
1461static inline u32 gr_rstr2d_gpc_map5_r(void)
1462{
1463 return 0x00407820;
1464}
1465static inline u32 gr_rstr2d_map_table_cfg_r(void)
1466{
1467 return 0x004078bc;
1468}
1469static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1470{
1471 return (v & 0xff) << 0;
1472}
1473static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1474{
1475 return (v & 0xff) << 8;
1476}
1477static inline u32 gr_pd_hww_esr_r(void)
1478{
1479 return 0x00406018;
1480}
1481static inline u32 gr_pd_hww_esr_reset_active_f(void)
1482{
1483 return 0x40000000;
1484}
1485static inline u32 gr_pd_hww_esr_en_enable_f(void)
1486{
1487 return 0x80000000;
1488}
1489static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1490{
1491 return 0x00406028 + i*4;
1492}
1493static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1494{
1495 return 0x00000004;
1496}
1497static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1498{
1499 return (v & 0xf) << 0;
1500}
1501static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1502{
1503 return (v & 0xf) << 4;
1504}
1505static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1506{
1507 return (v & 0xf) << 8;
1508}
1509static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1510{
1511 return (v & 0xf) << 12;
1512}
1513static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1514{
1515 return (v & 0xf) << 16;
1516}
1517static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1518{
1519 return (v & 0xf) << 20;
1520}
1521static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1522{
1523 return (v & 0xf) << 24;
1524}
1525static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1526{
1527 return (v & 0xf) << 28;
1528}
1529static inline u32 gr_pd_ab_dist_cfg0_r(void)
1530{
1531 return 0x004064c0;
1532}
1533static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1534{
1535 return 0x80000000;
1536}
1537static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1538{
1539 return 0x0;
1540}
1541static inline u32 gr_pd_ab_dist_cfg1_r(void)
1542{
1543 return 0x004064c4;
1544}
1545static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1546{
1547 return 0xffff;
1548}
1549static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1550{
1551 return (v & 0xffff) << 16;
1552}
1553static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1554{
1555 return 0x00000080;
1556}
1557static inline u32 gr_pd_ab_dist_cfg2_r(void)
1558{
1559 return 0x004064c8;
1560}
1561static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1562{
1563 return (v & 0x1fff) << 0;
1564}
1565static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1566{
1567 return 0x00000900;
1568}
1569static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1570{
1571 return (v & 0x1fff) << 16;
1572}
1573static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1574{
1575 return 0x00000020;
1576}
1577static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1578{
1579 return 0x00000900;
1580}
1581static inline u32 gr_pd_dist_skip_table_r(u32 i)
1582{
1583 return 0x004064d0 + i*4;
1584}
1585static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1586{
1587 return 0x00000008;
1588}
1589static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1590{
1591 return (v & 0xff) << 0;
1592}
1593static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1594{
1595 return (v & 0xff) << 8;
1596}
1597static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1598{
1599 return (v & 0xff) << 16;
1600}
1601static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1602{
1603 return (v & 0xff) << 24;
1604}
1605static inline u32 gr_ds_debug_r(void)
1606{
1607 return 0x00405800;
1608}
1609static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1610{
1611 return 0x0;
1612}
1613static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1614{
1615 return 0x8000000;
1616}
1617static inline u32 gr_ds_zbc_color_r_r(void)
1618{
1619 return 0x00405804;
1620}
1621static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1622{
1623 return (v & 0xffffffff) << 0;
1624}
1625static inline u32 gr_ds_zbc_color_g_r(void)
1626{
1627 return 0x00405808;
1628}
1629static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1630{
1631 return (v & 0xffffffff) << 0;
1632}
1633static inline u32 gr_ds_zbc_color_b_r(void)
1634{
1635 return 0x0040580c;
1636}
1637static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1638{
1639 return (v & 0xffffffff) << 0;
1640}
1641static inline u32 gr_ds_zbc_color_a_r(void)
1642{
1643 return 0x00405810;
1644}
1645static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1646{
1647 return (v & 0xffffffff) << 0;
1648}
1649static inline u32 gr_ds_zbc_color_fmt_r(void)
1650{
1651 return 0x00405814;
1652}
1653static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1654{
1655 return (v & 0x7f) << 0;
1656}
1657static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1658{
1659 return 0x0;
1660}
1661static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1662{
1663 return 0x00000001;
1664}
1665static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1666{
1667 return 0x00000002;
1668}
1669static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1670{
1671 return 0x00000004;
1672}
1673static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1674{
1675 return 0x00000028;
1676}
1677static inline u32 gr_ds_zbc_z_r(void)
1678{
1679 return 0x00405818;
1680}
1681static inline u32 gr_ds_zbc_z_val_s(void)
1682{
1683 return 32;
1684}
1685static inline u32 gr_ds_zbc_z_val_f(u32 v)
1686{
1687 return (v & 0xffffffff) << 0;
1688}
1689static inline u32 gr_ds_zbc_z_val_m(void)
1690{
1691 return 0xffffffff << 0;
1692}
1693static inline u32 gr_ds_zbc_z_val_v(u32 r)
1694{
1695 return (r >> 0) & 0xffffffff;
1696}
1697static inline u32 gr_ds_zbc_z_val__init_v(void)
1698{
1699 return 0x00000000;
1700}
1701static inline u32 gr_ds_zbc_z_val__init_f(void)
1702{
1703 return 0x0;
1704}
1705static inline u32 gr_ds_zbc_z_fmt_r(void)
1706{
1707 return 0x0040581c;
1708}
1709static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1710{
1711 return (v & 0x1) << 0;
1712}
1713static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1714{
1715 return 0x0;
1716}
1717static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1718{
1719 return 0x00000001;
1720}
1721static inline u32 gr_ds_zbc_tbl_index_r(void)
1722{
1723 return 0x00405820;
1724}
1725static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1726{
1727 return (v & 0xf) << 0;
1728}
1729static inline u32 gr_ds_zbc_tbl_ld_r(void)
1730{
1731 return 0x00405824;
1732}
1733static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1734{
1735 return 0x0;
1736}
1737static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1738{
1739 return 0x1;
1740}
1741static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1742{
1743 return 0x0;
1744}
1745static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1746{
1747 return 0x4;
1748}
1749static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
1750{
1751 return 0x00405830;
1752}
1753static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1754{
1755 return (v & 0x3fffff) << 0;
1756}
1757static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
1758{
1759 return 0x0040585c;
1760}
1761static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1762{
1763 return (v & 0xffff) << 0;
1764}
1765static inline u32 gr_ds_hww_esr_r(void)
1766{
1767 return 0x00405840;
1768}
1769static inline u32 gr_ds_hww_esr_reset_s(void)
1770{
1771 return 1;
1772}
1773static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1774{
1775 return (v & 0x1) << 30;
1776}
1777static inline u32 gr_ds_hww_esr_reset_m(void)
1778{
1779 return 0x1 << 30;
1780}
1781static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1782{
1783 return (r >> 30) & 0x1;
1784}
1785static inline u32 gr_ds_hww_esr_reset_task_v(void)
1786{
1787 return 0x00000001;
1788}
1789static inline u32 gr_ds_hww_esr_reset_task_f(void)
1790{
1791 return 0x40000000;
1792}
1793static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1794{
1795 return 0x80000000;
1796}
1797static inline u32 gr_ds_hww_esr_2_r(void)
1798{
1799 return 0x00405848;
1800}
1801static inline u32 gr_ds_hww_esr_2_reset_s(void)
1802{
1803 return 1;
1804}
1805static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
1806{
1807 return (v & 0x1) << 30;
1808}
1809static inline u32 gr_ds_hww_esr_2_reset_m(void)
1810{
1811 return 0x1 << 30;
1812}
1813static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
1814{
1815 return (r >> 30) & 0x1;
1816}
1817static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
1818{
1819 return 0x00000001;
1820}
1821static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
1822{
1823 return 0x40000000;
1824}
1825static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
1826{
1827 return 0x80000000;
1828}
1829static inline u32 gr_ds_hww_report_mask_r(void)
1830{
1831 return 0x00405844;
1832}
1833static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1834{
1835 return 0x1;
1836}
1837static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1838{
1839 return 0x2;
1840}
1841static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1842{
1843 return 0x4;
1844}
1845static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1846{
1847 return 0x8;
1848}
1849static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1850{
1851 return 0x10;
1852}
1853static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1854{
1855 return 0x20;
1856}
1857static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1858{
1859 return 0x40;
1860}
1861static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1862{
1863 return 0x80;
1864}
1865static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1866{
1867 return 0x100;
1868}
1869static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1870{
1871 return 0x200;
1872}
1873static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1874{
1875 return 0x400;
1876}
1877static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1878{
1879 return 0x800;
1880}
1881static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1882{
1883 return 0x1000;
1884}
1885static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1886{
1887 return 0x2000;
1888}
1889static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1890{
1891 return 0x4000;
1892}
1893static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1894{
1895 return 0x8000;
1896}
1897static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1898{
1899 return 0x10000;
1900}
1901static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1902{
1903 return 0x20000;
1904}
1905static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1906{
1907 return 0x40000;
1908}
1909static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1910{
1911 return 0x80000;
1912}
1913static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1914{
1915 return 0x100000;
1916}
1917static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
1918{
1919 return 0x200000;
1920}
1921static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
1922{
1923 return 0x400000;
1924}
1925static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
1926{
1927 return 0x800000;
1928}
1929static inline u32 gr_ds_hww_report_mask_2_r(void)
1930{
1931 return 0x0040584c;
1932}
1933static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
1934{
1935 return 0x1;
1936}
1937static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
1938{
1939 return 0x00405870 + i*4;
1940}
1941static inline u32 gr_scc_bundle_cb_base_r(void)
1942{
1943 return 0x00408004;
1944}
1945static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
1946{
1947 return (v & 0xffffffff) << 0;
1948}
1949static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
1950{
1951 return 0x00000008;
1952}
1953static inline u32 gr_scc_bundle_cb_size_r(void)
1954{
1955 return 0x00408008;
1956}
1957static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
1958{
1959 return (v & 0x7ff) << 0;
1960}
1961static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
1962{
1963 return 0x00000030;
1964}
1965static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
1966{
1967 return 0x00000100;
1968}
1969static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
1970{
1971 return 0x00000000;
1972}
1973static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
1974{
1975 return 0x0;
1976}
1977static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
1978{
1979 return 0x80000000;
1980}
1981static inline u32 gr_scc_pagepool_base_r(void)
1982{
1983 return 0x0040800c;
1984}
1985static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
1986{
1987 return (v & 0xffffffff) << 0;
1988}
1989static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
1990{
1991 return 0x00000008;
1992}
1993static inline u32 gr_scc_pagepool_r(void)
1994{
1995 return 0x00408010;
1996}
1997static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
1998{
1999 return (v & 0x3ff) << 0;
2000}
2001static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
2002{
2003 return 0x00000000;
2004}
2005static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
2006{
2007 return 0x00000200;
2008}
2009static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
2010{
2011 return 0x00000100;
2012}
2013static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
2014{
2015 return 10;
2016}
2017static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
2018{
2019 return (v & 0x3ff) << 10;
2020}
2021static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
2022{
2023 return 0x3ff << 10;
2024}
2025static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
2026{
2027 return (r >> 10) & 0x3ff;
2028}
2029static inline u32 gr_scc_pagepool_valid_true_f(void)
2030{
2031 return 0x80000000;
2032}
2033static inline u32 gr_scc_init_r(void)
2034{
2035 return 0x0040802c;
2036}
2037static inline u32 gr_scc_init_ram_trigger_f(void)
2038{
2039 return 0x1;
2040}
2041static inline u32 gr_scc_hww_esr_r(void)
2042{
2043 return 0x00408030;
2044}
2045static inline u32 gr_scc_hww_esr_reset_active_f(void)
2046{
2047 return 0x40000000;
2048}
2049static inline u32 gr_scc_hww_esr_en_enable_f(void)
2050{
2051 return 0x80000000;
2052}
2053static inline u32 gr_sked_hww_esr_r(void)
2054{
2055 return 0x00407020;
2056}
2057static inline u32 gr_sked_hww_esr_reset_active_f(void)
2058{
2059 return 0x40000000;
2060}
2061static inline u32 gr_cwd_fs_r(void)
2062{
2063 return 0x00405b00;
2064}
2065static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2066{
2067 return (v & 0xff) << 0;
2068}
2069static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2070{
2071 return (v & 0xff) << 8;
2072}
2073static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2074{
2075 return 0x00405b60 + i*4;
2076}
2077static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2078{
2079 return (v & 0xf) << 0;
2080}
2081static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2082{
2083 return (v & 0xf) << 8;
2084}
2085static inline u32 gr_cwd_sm_id_r(u32 i)
2086{
2087 return 0x00405ba0 + i*4;
2088}
2089static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2090{
2091 return (v & 0xff) << 0;
2092}
2093static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2094{
2095 return (v & 0xff) << 8;
2096}
2097static inline u32 gr_gpc0_fs_gpc_r(void)
2098{
2099 return 0x00502608;
2100}
2101static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2102{
2103 return (r >> 0) & 0x1f;
2104}
2105static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2106{
2107 return (r >> 16) & 0x1f;
2108}
2109static inline u32 gr_gpc0_cfg_r(void)
2110{
2111 return 0x00502620;
2112}
2113static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2114{
2115 return (r >> 0) & 0xff;
2116}
2117static inline u32 gr_gpccs_rc_lanes_r(void)
2118{
2119 return 0x00502880;
2120}
2121static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2122{
2123 return 6;
2124}
2125static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2126{
2127 return (v & 0x3f) << 0;
2128}
2129static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2130{
2131 return 0x3f << 0;
2132}
2133static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2134{
2135 return (r >> 0) & 0x3f;
2136}
2137static inline u32 gr_gpccs_rc_lane_size_r(void)
2138{
2139 return 0x00502910;
2140}
2141static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2142{
2143 return 24;
2144}
2145static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2146{
2147 return (v & 0xffffff) << 0;
2148}
2149static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2150{
2151 return 0xffffff << 0;
2152}
2153static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2154{
2155 return (r >> 0) & 0xffffff;
2156}
2157static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2158{
2159 return 0x00000000;
2160}
2161static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2162{
2163 return 0x0;
2164}
2165static inline u32 gr_gpc0_zcull_fs_r(void)
2166{
2167 return 0x00500910;
2168}
2169static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2170{
2171 return (v & 0x1ff) << 0;
2172}
2173static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2174{
2175 return (v & 0xf) << 16;
2176}
2177static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2178{
2179 return 0x00500914;
2180}
2181static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2182{
2183 return (v & 0xf) << 0;
2184}
2185static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2186{
2187 return (v & 0xf) << 8;
2188}
2189static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2190{
2191 return 0x00500918;
2192}
2193static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2194{
2195 return (v & 0xffffff) << 0;
2196}
2197static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2198{
2199 return 0x00800000;
2200}
2201static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2202{
2203 return 0x00500920;
2204}
2205static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2206{
2207 return (v & 0xffff) << 0;
2208}
2209static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2210{
2211 return 0x00500a04 + i*32;
2212}
2213static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2214{
2215 return 0x00000040;
2216}
2217static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2218{
2219 return 0x00000010;
2220}
2221static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2222{
2223 return 0x00500c10 + i*4;
2224}
2225static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2226{
2227 return (v & 0xff) << 0;
2228}
2229static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2230{
2231 return 0x00500c30 + i*4;
2232}
2233static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2234{
2235 return (r >> 0) & 0xff;
2236}
2237static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2238{
2239 return 0x00504088;
2240}
2241static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2242{
2243 return (v & 0xffff) << 0;
2244}
2245static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2246{
2247 return 0x00504698;
2248}
2249static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2250{
2251 return (v & 0xffff) << 0;
2252}
2253static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2254{
2255 return 0x0050469c;
2256}
2257static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2258{
2259 return (r >> 0) & 0xff;
2260}
2261static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2262{
2263 return (r >> 8) & 0xfff;
2264}
2265static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2266{
2267 return (r >> 20) & 0xfff;
2268}
2269static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2270{
2271 return 0x00503018;
2272}
2273static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2274{
2275 return 0x1 << 0;
2276}
2277static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2278{
2279 return 0x1;
2280}
2281static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2282{
2283 return 0x005030c0;
2284}
2285static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2286{
2287 return (v & 0x3fffff) << 0;
2288}
2289static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2290{
2291 return 0x3fffff << 0;
2292}
2293static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2294{
2295 return 0x00000320;
2296}
2297static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
2298{
2299 return 0x00000ba8;
2300}
2301static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2302{
2303 return 0x00000020;
2304}
2305static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2306{
2307 return 0x005030f4;
2308}
2309static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2310{
2311 return 0x005030e4;
2312}
2313static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2314{
2315 return (v & 0xffff) << 0;
2316}
2317static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2318{
2319 return 0xffff << 0;
2320}
2321static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2322{
2323 return 0x00000800;
2324}
2325static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2326{
2327 return 0x00000020;
2328}
2329static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2330{
2331 return 0x005030f8;
2332}
2333static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2334{
2335 return 0x005030f0;
2336}
2337static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2338{
2339 return (v & 0x3fffff) << 0;
2340}
2341static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2342{
2343 return 0x00000320;
2344}
2345static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
2346{
2347 return 0x00419b00;
2348}
2349static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
2350{
2351 return (v & 0xffffffff) << 0;
2352}
2353static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
2354{
2355 return 0x00419b04;
2356}
2357static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
2358{
2359 return 21;
2360}
2361static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
2362{
2363 return (v & 0x1fffff) << 0;
2364}
2365static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
2366{
2367 return 0x1fffff << 0;
2368}
2369static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
2370{
2371 return (r >> 0) & 0x1fffff;
2372}
2373static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
2374{
2375 return 0x80;
2376}
2377static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
2378{
2379 return 1;
2380}
2381static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
2382{
2383 return (v & 0x1) << 31;
2384}
2385static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
2386{
2387 return 0x1 << 31;
2388}
2389static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
2390{
2391 return (r >> 31) & 0x1;
2392}
2393static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
2394{
2395 return 0x80000000;
2396}
2397static inline u32 gr_gpccs_falcon_addr_r(void)
2398{
2399 return 0x0041a0ac;
2400}
2401static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2402{
2403 return 6;
2404}
2405static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2406{
2407 return (v & 0x3f) << 0;
2408}
2409static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2410{
2411 return 0x3f << 0;
2412}
2413static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2414{
2415 return (r >> 0) & 0x3f;
2416}
2417static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2418{
2419 return 0x00000000;
2420}
2421static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2422{
2423 return 0x0;
2424}
2425static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2426{
2427 return 6;
2428}
2429static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2430{
2431 return (v & 0x3f) << 6;
2432}
2433static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2434{
2435 return 0x3f << 6;
2436}
2437static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2438{
2439 return (r >> 6) & 0x3f;
2440}
2441static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2442{
2443 return 0x00000000;
2444}
2445static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2446{
2447 return 0x0;
2448}
2449static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2450{
2451 return 12;
2452}
2453static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2454{
2455 return (v & 0xfff) << 0;
2456}
2457static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2458{
2459 return 0xfff << 0;
2460}
2461static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2462{
2463 return (r >> 0) & 0xfff;
2464}
2465static inline u32 gr_gpccs_cpuctl_r(void)
2466{
2467 return 0x0041a100;
2468}
2469static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2470{
2471 return (v & 0x1) << 1;
2472}
2473static inline u32 gr_gpccs_dmactl_r(void)
2474{
2475 return 0x0041a10c;
2476}
2477static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2478{
2479 return (v & 0x1) << 0;
2480}
2481static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2482{
2483 return 0x1 << 1;
2484}
2485static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2486{
2487 return 0x1 << 2;
2488}
2489static inline u32 gr_gpccs_imemc_r(u32 i)
2490{
2491 return 0x0041a180 + i*16;
2492}
2493static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2494{
2495 return (v & 0x3f) << 2;
2496}
2497static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2498{
2499 return (v & 0xff) << 8;
2500}
2501static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2502{
2503 return (v & 0x1) << 24;
2504}
2505static inline u32 gr_gpccs_imemd_r(u32 i)
2506{
2507 return 0x0041a184 + i*16;
2508}
2509static inline u32 gr_gpccs_imemt_r(u32 i)
2510{
2511 return 0x0041a188 + i*16;
2512}
2513static inline u32 gr_gpccs_imemt__size_1_v(void)
2514{
2515 return 0x00000004;
2516}
2517static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2518{
2519 return (v & 0xffff) << 0;
2520}
2521static inline u32 gr_gpccs_dmemc_r(u32 i)
2522{
2523 return 0x0041a1c0 + i*8;
2524}
2525static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2526{
2527 return (v & 0x3f) << 2;
2528}
2529static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2530{
2531 return (v & 0xff) << 8;
2532}
2533static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2534{
2535 return (v & 0x1) << 24;
2536}
2537static inline u32 gr_gpccs_dmemd_r(u32 i)
2538{
2539 return 0x0041a1c4 + i*8;
2540}
2541static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2542{
2543 return 0x0041a800 + i*4;
2544}
2545static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2546{
2547 return (v & 0xffffffff) << 0;
2548}
2549static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2550{
2551 return 0x00418e24;
2552}
2553static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2554{
2555 return 32;
2556}
2557static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2558{
2559 return (v & 0xffffffff) << 0;
2560}
2561static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2562{
2563 return 0xffffffff << 0;
2564}
2565static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2566{
2567 return (r >> 0) & 0xffffffff;
2568}
2569static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2570{
2571 return 0x00000000;
2572}
2573static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2574{
2575 return 0x0;
2576}
2577static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2578{
2579 return 0x00418e28;
2580}
2581static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2582{
2583 return 11;
2584}
2585static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2586{
2587 return (v & 0x7ff) << 0;
2588}
2589static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2590{
2591 return 0x7ff << 0;
2592}
2593static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2594{
2595 return (r >> 0) & 0x7ff;
2596}
2597static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2598{
2599 return 0x00000030;
2600}
2601static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2602{
2603 return 0x30;
2604}
2605static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2606{
2607 return 1;
2608}
2609static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2610{
2611 return (v & 0x1) << 31;
2612}
2613static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2614{
2615 return 0x1 << 31;
2616}
2617static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2618{
2619 return (r >> 31) & 0x1;
2620}
2621static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2622{
2623 return 0x00000000;
2624}
2625static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2626{
2627 return 0x0;
2628}
2629static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2630{
2631 return 0x00000001;
2632}
2633static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2634{
2635 return 0x80000000;
2636}
2637static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
2638{
2639 return 0x005001dc;
2640}
2641static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
2642{
2643 return (v & 0xffff) << 0;
2644}
2645static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
2646{
2647 return 0x00000de0;
2648}
2649static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
2650{
2651 return 0x00000100;
2652}
2653static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
2654{
2655 return 0x005001d8;
2656}
2657static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
2658{
2659 return (v & 0xffffffff) << 0;
2660}
2661static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
2662{
2663 return 0x00000008;
2664}
2665static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
2666{
2667 return 0x004181e4;
2668}
2669static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
2670{
2671 return (v & 0xfff) << 0;
2672}
2673static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
2674{
2675 return 0x00000100;
2676}
2677static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
2678{
2679 return 0x0041befc;
2680}
2681static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
2682{
2683 return (v & 0xfff) << 0;
2684}
2685static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
2686{
2687 return 0x00418ea0 + i*4;
2688}
2689static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
2690{
2691 return (v & 0x3fffff) << 0;
2692}
2693static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
2694{
2695 return 0x3fffff << 0;
2696}
2697static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
2698{
2699 return 0x00418010 + i*4;
2700}
2701static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
2702{
2703 return (v & 0xffffffff) << 0;
2704}
2705static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
2706{
2707 return 0x0041804c + i*4;
2708}
2709static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
2710{
2711 return (v & 0xffffffff) << 0;
2712}
2713static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
2714{
2715 return 0x00418088 + i*4;
2716}
2717static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
2718{
2719 return (v & 0xffffffff) << 0;
2720}
2721static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
2722{
2723 return 0x004180c4 + i*4;
2724}
2725static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
2726{
2727 return (v & 0xffffffff) << 0;
2728}
2729static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
2730{
2731 return 0x00500100;
2732}
2733static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
2734{
2735 return 0x00418110 + i*4;
2736}
2737static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
2738{
2739 return (v & 0xffffffff) << 0;
2740}
2741static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
2742{
2743 return 0x0050014c;
2744}
2745static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2746{
2747 return 0x00418810;
2748}
2749static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2750{
2751 return (v & 0xfffffff) << 0;
2752}
2753static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2754{
2755 return 0x0000000c;
2756}
2757static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2758{
2759 return 0x80000000;
2760}
2761static inline u32 gr_crstr_gpc_map0_r(void)
2762{
2763 return 0x00418b08;
2764}
2765static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2766{
2767 return (v & 0x7) << 0;
2768}
2769static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2770{
2771 return (v & 0x7) << 5;
2772}
2773static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2774{
2775 return (v & 0x7) << 10;
2776}
2777static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2778{
2779 return (v & 0x7) << 15;
2780}
2781static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2782{
2783 return (v & 0x7) << 20;
2784}
2785static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2786{
2787 return (v & 0x7) << 25;
2788}
2789static inline u32 gr_crstr_gpc_map1_r(void)
2790{
2791 return 0x00418b0c;
2792}
2793static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2794{
2795 return (v & 0x7) << 0;
2796}
2797static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2798{
2799 return (v & 0x7) << 5;
2800}
2801static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2802{
2803 return (v & 0x7) << 10;
2804}
2805static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2806{
2807 return (v & 0x7) << 15;
2808}
2809static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2810{
2811 return (v & 0x7) << 20;
2812}
2813static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2814{
2815 return (v & 0x7) << 25;
2816}
2817static inline u32 gr_crstr_gpc_map2_r(void)
2818{
2819 return 0x00418b10;
2820}
2821static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2822{
2823 return (v & 0x7) << 0;
2824}
2825static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2826{
2827 return (v & 0x7) << 5;
2828}
2829static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2830{
2831 return (v & 0x7) << 10;
2832}
2833static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2834{
2835 return (v & 0x7) << 15;
2836}
2837static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2838{
2839 return (v & 0x7) << 20;
2840}
2841static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2842{
2843 return (v & 0x7) << 25;
2844}
2845static inline u32 gr_crstr_gpc_map3_r(void)
2846{
2847 return 0x00418b14;
2848}
2849static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2850{
2851 return (v & 0x7) << 0;
2852}
2853static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2854{
2855 return (v & 0x7) << 5;
2856}
2857static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2858{
2859 return (v & 0x7) << 10;
2860}
2861static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2862{
2863 return (v & 0x7) << 15;
2864}
2865static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2866{
2867 return (v & 0x7) << 20;
2868}
2869static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2870{
2871 return (v & 0x7) << 25;
2872}
2873static inline u32 gr_crstr_gpc_map4_r(void)
2874{
2875 return 0x00418b18;
2876}
2877static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2878{
2879 return (v & 0x7) << 0;
2880}
2881static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2882{
2883 return (v & 0x7) << 5;
2884}
2885static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2886{
2887 return (v & 0x7) << 10;
2888}
2889static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2890{
2891 return (v & 0x7) << 15;
2892}
2893static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2894{
2895 return (v & 0x7) << 20;
2896}
2897static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2898{
2899 return (v & 0x7) << 25;
2900}
2901static inline u32 gr_crstr_gpc_map5_r(void)
2902{
2903 return 0x00418b1c;
2904}
2905static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2906{
2907 return (v & 0x7) << 0;
2908}
2909static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2910{
2911 return (v & 0x7) << 5;
2912}
2913static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
2914{
2915 return (v & 0x7) << 10;
2916}
2917static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
2918{
2919 return (v & 0x7) << 15;
2920}
2921static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
2922{
2923 return (v & 0x7) << 20;
2924}
2925static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
2926{
2927 return (v & 0x7) << 25;
2928}
2929static inline u32 gr_crstr_map_table_cfg_r(void)
2930{
2931 return 0x00418bb8;
2932}
2933static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
2934{
2935 return (v & 0xff) << 0;
2936}
2937static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
2938{
2939 return (v & 0xff) << 8;
2940}
2941static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
2942{
2943 return 0x00418980;
2944}
2945static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
2946{
2947 return (v & 0x7) << 0;
2948}
2949static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
2950{
2951 return (v & 0x7) << 4;
2952}
2953static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
2954{
2955 return (v & 0x7) << 8;
2956}
2957static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
2958{
2959 return (v & 0x7) << 12;
2960}
2961static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
2962{
2963 return (v & 0x7) << 16;
2964}
2965static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
2966{
2967 return (v & 0x7) << 20;
2968}
2969static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
2970{
2971 return (v & 0x7) << 24;
2972}
2973static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
2974{
2975 return (v & 0x7) << 28;
2976}
2977static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
2978{
2979 return 0x00418984;
2980}
2981static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
2982{
2983 return (v & 0x7) << 0;
2984}
2985static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
2986{
2987 return (v & 0x7) << 4;
2988}
2989static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
2990{
2991 return (v & 0x7) << 8;
2992}
2993static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
2994{
2995 return (v & 0x7) << 12;
2996}
2997static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
2998{
2999 return (v & 0x7) << 16;
3000}
3001static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
3002{
3003 return (v & 0x7) << 20;
3004}
3005static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
3006{
3007 return (v & 0x7) << 24;
3008}
3009static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
3010{
3011 return (v & 0x7) << 28;
3012}
3013static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
3014{
3015 return 0x00418988;
3016}
3017static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
3018{
3019 return (v & 0x7) << 0;
3020}
3021static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
3022{
3023 return (v & 0x7) << 4;
3024}
3025static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
3026{
3027 return (v & 0x7) << 8;
3028}
3029static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
3030{
3031 return (v & 0x7) << 12;
3032}
3033static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
3034{
3035 return (v & 0x7) << 16;
3036}
3037static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
3038{
3039 return (v & 0x7) << 20;
3040}
3041static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
3042{
3043 return (v & 0x7) << 24;
3044}
3045static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
3046{
3047 return 3;
3048}
3049static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
3050{
3051 return (v & 0x7) << 28;
3052}
3053static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
3054{
3055 return 0x7 << 28;
3056}
3057static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
3058{
3059 return (r >> 28) & 0x7;
3060}
3061static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
3062{
3063 return 0x0041898c;
3064}
3065static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
3066{
3067 return (v & 0x7) << 0;
3068}
3069static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
3070{
3071 return (v & 0x7) << 4;
3072}
3073static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
3074{
3075 return (v & 0x7) << 8;
3076}
3077static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
3078{
3079 return (v & 0x7) << 12;
3080}
3081static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
3082{
3083 return (v & 0x7) << 16;
3084}
3085static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
3086{
3087 return (v & 0x7) << 20;
3088}
3089static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
3090{
3091 return (v & 0x7) << 24;
3092}
3093static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
3094{
3095 return (v & 0x7) << 28;
3096}
3097static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
3098{
3099 return 0x00418c6c;
3100}
3101static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
3102{
3103 return 0x0;
3104}
3105static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
3106{
3107 return 0x1;
3108}
3109static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
3110{
3111 return 0x00419004;
3112}
3113static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
3114{
3115 return (v & 0xffffffff) << 0;
3116}
3117static inline u32 gr_gpcs_gcc_pagepool_r(void)
3118{
3119 return 0x00419008;
3120}
3121static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
3122{
3123 return (v & 0x3ff) << 0;
3124}
3125static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
3126{
3127 return 0x0041980c;
3128}
3129static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
3130{
3131 return 0x10;
3132}
3133static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
3134{
3135 return 0x00419848;
3136}
3137static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
3138{
3139 return (v & 0xfffffff) << 0;
3140}
3141static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
3142{
3143 return (v & 0x1) << 28;
3144}
3145static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
3146{
3147 return 0x10000000;
3148}
3149static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
3150{
3151 return 0x00419c00;
3152}
3153static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
3154{
3155 return 0x0;
3156}
3157static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
3158{
3159 return 0x8;
3160}
3161static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
3162{
3163 return 0x00419c2c;
3164}
3165static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
3166{
3167 return (v & 0xfffffff) << 0;
3168}
3169static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
3170{
3171 return (v & 0x1) << 28;
3172}
3173static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
3174{
3175 return 0x10000000;
3176}
3177static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
3178{
3179 return 0x00419e44;
3180}
3181static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
3182{
3183 return 0x2;
3184}
3185static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3186{
3187 return 0x4;
3188}
3189static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3190{
3191 return 0x8;
3192}
3193static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3194{
3195 return 0x10;
3196}
3197static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3198{
3199 return 0x20;
3200}
3201static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3202{
3203 return 0x40;
3204}
3205static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3206{
3207 return 0x80;
3208}
3209static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3210{
3211 return 0x100;
3212}
3213static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3214{
3215 return 0x200;
3216}
3217static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3218{
3219 return 0x400;
3220}
3221static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3222{
3223 return 0x800;
3224}
3225static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3226{
3227 return 0x1000;
3228}
3229static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3230{
3231 return 0x2000;
3232}
3233static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3234{
3235 return 0x4000;
3236}
3237static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3238{
3239 return 0x8000;
3240}
3241static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3242{
3243 return 0x10000;
3244}
3245static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3246{
3247 return 0x20000;
3248}
3249static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3250{
3251 return 0x40000;
3252}
3253static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3254{
3255 return 0x800000;
3256}
3257static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3258{
3259 return 0x400000;
3260}
3261static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3262{
3263 return 0x80000;
3264}
3265static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3266{
3267 return 0x100000;
3268}
3269static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3270{
3271 return 0x00419e4c;
3272}
3273static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3274{
3275 return 0x1;
3276}
3277static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3278{
3279 return 0x2;
3280}
3281static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3282{
3283 return 0x4;
3284}
3285static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3286{
3287 return 0x8;
3288}
3289static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3290{
3291 return 0x10;
3292}
3293static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
3294{
3295 return 0x20000000;
3296}
3297static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
3298{
3299 return 0x40000000;
3300}
3301static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3302{
3303 return 0x20;
3304}
3305static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3306{
3307 return 0x40;
3308}
3309static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3310{
3311 return 0x00419d0c;
3312}
3313static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3314{
3315 return 0x2;
3316}
3317static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3318{
3319 return 0x1;
3320}
3321static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3322{
3323 return 0x0050450c;
3324}
3325static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3326{
3327 return (r >> 1) & 0x1;
3328}
3329static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3330{
3331 return 0x2;
3332}
3333static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3334{
3335 return 0x0041ac94;
3336}
3337static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3338{
3339 return (v & 0xff) << 16;
3340}
3341static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3342{
3343 return 0x00502c90;
3344}
3345static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3346{
3347 return (r >> 16) & 0xff;
3348}
3349static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3350{
3351 return 0x00000001;
3352}
3353static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3354{
3355 return 0x00504508;
3356}
3357static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3358{
3359 return (r >> 0) & 0x1;
3360}
3361static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3362{
3363 return 0x00000001;
3364}
3365static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3366{
3367 return (r >> 1) & 0x1;
3368}
3369static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3370{
3371 return 0x00000001;
3372}
3373static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3374{
3375 return 0x00504610;
3376}
3377static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3378{
3379 return 0x1 << 0;
3380}
3381static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3382{
3383 return (r >> 0) & 0x1;
3384}
3385static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3386{
3387 return 0x00000001;
3388}
3389static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
3390{
3391 return 0x1;
3392}
3393static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3394{
3395 return 0x00000000;
3396}
3397static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
3398{
3399 return 0x0;
3400}
3401static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3402{
3403 return 0x80000000;
3404}
3405static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3406{
3407 return 0x0;
3408}
3409static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3410{
3411 return 0x40000000;
3412}
3413static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3414{
3415 return 0x1 << 1;
3416}
3417static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3418{
3419 return (r >> 1) & 0x1;
3420}
3421static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3422{
3423 return 0x0;
3424}
3425static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3426{
3427 return 0x1 << 2;
3428}
3429static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3430{
3431 return (r >> 2) & 0x1;
3432}
3433static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3434{
3435 return 0x0;
3436}
3437static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3438{
3439 return 0x00504614;
3440}
3441static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3442{
3443 return 0x00504624;
3444}
3445static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3446{
3447 return 0x00504634;
3448}
3449static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3450{
3451 return 0x00419e24;
3452}
3453static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void)
3454{
3455 return 0x00000000;
3456}
3457static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void)
3458{
3459 return 0x00000000;
3460}
3461static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3462{
3463 return 0x0050460c;
3464}
3465static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3466{
3467 return (r >> 0) & 0x1;
3468}
3469static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3470{
3471 return (r >> 4) & 0x1;
3472}
3473static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3474{
3475 return 0x00000001;
3476}
3477static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3478{
3479 return 0x00419e50;
3480}
3481static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3482{
3483 return 0x10;
3484}
3485static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3486{
3487 return 0x20;
3488}
3489static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3490{
3491 return 0x40;
3492}
3493static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3494{
3495 return 0x00504650;
3496}
3497static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3498{
3499 return 0x10;
3500}
3501static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
3502{
3503 return 0x20000000;
3504}
3505static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
3506{
3507 return 0x40000000;
3508}
3509static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3510{
3511 return 0x20;
3512}
3513static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3514{
3515 return 0x40;
3516}
3517static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3518{
3519 return 0x00504224;
3520}
3521static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3522{
3523 return 0x1;
3524}
3525static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3526{
3527 return 0x00504648;
3528}
3529static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3530{
3531 return (r >> 0) & 0xffff;
3532}
3533static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3534{
3535 return 0x00000000;
3536}
3537static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3538{
3539 return 0x0;
3540}
3541static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3542{
3543 return 0x00504770;
3544}
3545static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3546{
3547 return 0x00419f70;
3548}
3549static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3550{
3551 return 0x1 << 4;
3552}
3553static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3554{
3555 return (v & 0x1) << 4;
3556}
3557static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3558{
3559 return 0x0050477c;
3560}
3561static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3562{
3563 return 0x00419f7c;
3564}
3565static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3566{
3567 return 0x1 << 0;
3568}
3569static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3570{
3571 return (v & 0x1) << 0;
3572}
3573static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3574{
3575 return 0x0041be08;
3576}
3577static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3578{
3579 return 0x4;
3580}
3581static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3582{
3583 return 0x0041bf00;
3584}
3585static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3586{
3587 return 0x0041bf04;
3588}
3589static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3590{
3591 return 0x0041bf08;
3592}
3593static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3594{
3595 return 0x0041bf0c;
3596}
3597static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3598{
3599 return 0x0041bf10;
3600}
3601static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3602{
3603 return 0x0041bf14;
3604}
3605static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3606{
3607 return 0x0041bfd0;
3608}
3609static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3610{
3611 return (v & 0xff) << 0;
3612}
3613static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3614{
3615 return (v & 0xff) << 8;
3616}
3617static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3618{
3619 return (v & 0x1f) << 16;
3620}
3621static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3622{
3623 return (v & 0x7) << 21;
3624}
3625static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3626{
3627 return (v & 0x1f) << 24;
3628}
3629static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3630{
3631 return 0x0041bfd4;
3632}
3633static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3634{
3635 return (v & 0xffffff) << 0;
3636}
3637static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3638{
3639 return 0x0041bfe4;
3640}
3641static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3642{
3643 return (v & 0x1f) << 0;
3644}
3645static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3646{
3647 return (v & 0x1f) << 5;
3648}
3649static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3650{
3651 return (v & 0x1f) << 10;
3652}
3653static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3654{
3655 return (v & 0x1f) << 15;
3656}
3657static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3658{
3659 return (v & 0x1f) << 20;
3660}
3661static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3662{
3663 return (v & 0x1f) << 25;
3664}
3665static inline u32 gr_bes_zrop_settings_r(void)
3666{
3667 return 0x00408850;
3668}
3669static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3670{
3671 return (v & 0xf) << 0;
3672}
3673static inline u32 gr_be0_crop_debug3_r(void)
3674{
3675 return 0x00410108;
3676}
3677static inline u32 gr_bes_crop_debug3_r(void)
3678{
3679 return 0x00408908;
3680}
3681static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3682{
3683 return 0x1 << 31;
3684}
3685static inline u32 gr_bes_crop_settings_r(void)
3686{
3687 return 0x00408958;
3688}
3689static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3690{
3691 return (v & 0xf) << 0;
3692}
3693static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3694{
3695 return 0x00000020;
3696}
3697static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3698{
3699 return 0x00000020;
3700}
3701static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3702{
3703 return 0x000000c0;
3704}
3705static inline u32 gr_zcull_subregion_qty_v(void)
3706{
3707 return 0x00000010;
3708}
3709static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3710{
3711 return 0x00504604;
3712}
3713static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3714{
3715 return 0x00504608;
3716}
3717static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3718{
3719 return 0x0050465c;
3720}
3721static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3722{
3723 return 0x00504660;
3724}
3725static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3726{
3727 return 0x00504664;
3728}
3729static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3730{
3731 return 0x00504668;
3732}
3733static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3734{
3735 return 0x0050466c;
3736}
3737static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3738{
3739 return 0x00504658;
3740}
3741static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3742{
3743 return 0x00504730;
3744}
3745static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3746{
3747 return 0x00504734;
3748}
3749static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3750{
3751 return 0x00504738;
3752}
3753static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3754{
3755 return 0x0050473c;
3756}
3757static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3758{
3759 return 0x00504740;
3760}
3761static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3762{
3763 return 0x00504744;
3764}
3765static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3766{
3767 return 0x00504748;
3768}
3769static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3770{
3771 return 0x0050474c;
3772}
3773static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
3774{
3775 return 0x00504678;
3776}
3777static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3778{
3779 return 0x00504694;
3780}
3781static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
3782{
3783 return 0x005046f0;
3784}
3785static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
3786{
3787 return 0x00504700;
3788}
3789static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
3790{
3791 return 0x005046f4;
3792}
3793static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
3794{
3795 return 0x00504704;
3796}
3797static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
3798{
3799 return 0x005046f8;
3800}
3801static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
3802{
3803 return 0x00504708;
3804}
3805static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
3806{
3807 return 0x005046fc;
3808}
3809static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
3810{
3811 return 0x0050470c;
3812}
3813static inline u32 gr_fe_pwr_mode_r(void)
3814{
3815 return 0x00404170;
3816}
3817static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3818{
3819 return 0x0;
3820}
3821static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3822{
3823 return 0x2;
3824}
3825static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3826{
3827 return (r >> 4) & 0x1;
3828}
3829static inline u32 gr_fe_pwr_mode_req_send_f(void)
3830{
3831 return 0x10;
3832}
3833static inline u32 gr_fe_pwr_mode_req_done_v(void)
3834{
3835 return 0x00000000;
3836}
3837static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
3838{
3839 return 0x00418880;
3840}
3841static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
3842{
3843 return 0x1 << 0;
3844}
3845static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
3846{
3847 return 0x1 << 11;
3848}
3849static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
3850{
3851 return 0x1 << 1;
3852}
3853static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
3854{
3855 return 0x1 << 2;
3856}
3857static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
3858{
3859 return 0x3 << 3;
3860}
3861static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
3862{
3863 return 0x3 << 5;
3864}
3865static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
3866{
3867 return 0x3 << 28;
3868}
3869static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
3870{
3871 return 0x1 << 30;
3872}
3873static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
3874{
3875 return 0x1 << 31;
3876}
3877static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
3878{
3879 return 0x00418890;
3880}
3881static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
3882{
3883 return 0x00418894;
3884}
3885static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
3886{
3887 return 0x004188b0;
3888}
3889static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
3890{
3891 return (r >> 16) & 0x1;
3892}
3893static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
3894{
3895 return 0x00000001;
3896}
3897static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
3898{
3899 return 0x004188b4;
3900}
3901static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
3902{
3903 return 0x004188b8;
3904}
3905static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
3906{
3907 return 0x004188ac;
3908}
3909static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
3910{
3911 return 0x00419e10;
3912}
3913static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
3914{
3915 return (v & 0x1) << 0;
3916}
3917static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
3918{
3919 return 0x00000001;
3920}
3921static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
3922{
3923 return 0x1 << 31;
3924}
3925static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
3926{
3927 return (r >> 31) & 0x1;
3928}
3929static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
3930{
3931 return 0x80000000;
3932}
3933static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3934{
3935 return 0x0;
3936}
3937static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3938{
3939 return 0x1 << 30;
3940}
3941static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
3942{
3943 return (r >> 30) & 0x1;
3944}
3945static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3946{
3947 return 0x40000000;
3948}
3949static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
3950{
3951 return 0x004041c0;
3952}
3953static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
3954{
3955 return (v & 0xffffffff) << 0;
3956}
3957static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
3958{
3959 return 0x0;
3960}
3961static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
3962{
3963 return 0x00419c84;
3964}
3965static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
3966{
3967 return (v & 0x7) << 8;
3968}
3969static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
3970{
3971 return 0x7 << 8;
3972}
3973static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
3974{
3975 return 0x100;
3976}
3977static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
3978{
3979 return 0x00419f78;
3980}
3981static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
3982{
3983 return 0x3 << 11;
3984}
3985static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
3986{
3987 return 0x1000;
3988}
3989static inline u32 gr_gpcs_tc_debug0_r(void)
3990{
3991 return 0x00418708;
3992}
3993static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
3994{
3995 return (v & 0x1ff) << 0;
3996}
3997static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
3998{
3999 return 0x1ff << 0;
4000}
4001#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h
new file mode 100644
index 00000000..d760b588
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h
@@ -0,0 +1,553 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ltc_gp106_h_
51#define _hw_ltc_gp106_h_
52
53static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
54{
55 return 0x0014046c;
56}
57static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
58{
59 return 0x00140518;
60}
61static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
62{
63 return 0x0017e318;
64}
65static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
66{
67 return 0x1 << 15;
68}
69static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
70{
71 return 0x00140494;
72}
73static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
74{
75 return (r >> 0) & 0xffff;
76}
77static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
78{
79 return (r >> 16) & 0x3;
80}
81static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
86{
87 return 0x00000001;
88}
89static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
90{
91 return 0x00000002;
92}
93static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
94{
95 return 0x0017e26c;
96}
97static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
98{
99 return 0x1;
100}
101static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
102{
103 return 0x2;
104}
105static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
106{
107 return (r >> 2) & 0x1;
108}
109static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
114{
115 return 0x4;
116}
117static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
118{
119 return 0x0014046c;
120}
121static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
122{
123 return 0x0017e270;
124}
125static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
126{
127 return (v & 0x3ffff) << 0;
128}
129static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
130{
131 return 0x0017e274;
132}
133static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
134{
135 return (v & 0x3ffff) << 0;
136}
137static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
138{
139 return 0x0003ffff;
140}
141static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
142{
143 return 0x0017e278;
144}
145static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
146{
147 return 0x0000000b;
148}
149static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
150{
151 return (r >> 0) & 0x3ffffff;
152}
153static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
154{
155 return 0x0017e27c;
156}
157static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
158{
159 return 0x0017e000;
160}
161static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
162{
163 return 0x0017e280;
164}
165static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
166{
167 return (r >> 0) & 0xffff;
168}
169static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
170{
171 return (r >> 24) & 0xf;
172}
173static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
174{
175 return (r >> 28) & 0xf;
176}
177static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
178{
179 return 0x0017e3f4;
180}
181static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
182{
183 return (r >> 0) & 0xffff;
184}
185static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
186{
187 return 0x0017e2ac;
188}
189static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
190{
191 return (v & 0x1f) << 16;
192}
193static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
194{
195 return 0x0017e338;
196}
197static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
198{
199 return (v & 0xf) << 0;
200}
201static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
202{
203 return 0x0017e33c + i*4;
204}
205static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
210{
211 return 0x0017e34c;
212}
213static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
214{
215 return 32;
216}
217static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
218{
219 return (v & 0xffffffff) << 0;
220}
221static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
222{
223 return 0xffffffff << 0;
224}
225static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
226{
227 return (r >> 0) & 0xffffffff;
228}
229static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
230{
231 return 0x0017e2b0;
232}
233static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
234{
235 return 0x10000000;
236}
237static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
238{
239 return 0x0017e214;
240}
241static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
242{
243 return (r >> 0) & 0x1;
244}
245static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
246{
247 return 0x00000001;
248}
249static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
250{
251 return 0x1;
252}
253static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
254{
255 return 0x00140214;
256}
257static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
258{
259 return (r >> 0) & 0x1;
260}
261static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
262{
263 return 0x00000001;
264}
265static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
266{
267 return 0x1;
268}
269static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
270{
271 return 0x00142214;
272}
273static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
274{
275 return (r >> 0) & 0x1;
276}
277static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
278{
279 return 0x00000001;
280}
281static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
282{
283 return 0x1;
284}
285static inline u32 ltc_ltcs_ltss_intr_r(void)
286{
287 return 0x0017e20c;
288}
289static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
290{
291 return 0x100;
292}
293static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
294{
295 return 0x200;
296}
297static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
298{
299 return 0x1 << 20;
300}
301static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
302{
303 return 0x1 << 30;
304}
305static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
306{
307 return 0x1000000;
308}
309static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
310{
311 return 0x2000000;
312}
313static inline u32 ltc_ltc0_lts0_intr_r(void)
314{
315 return 0x0014040c;
316}
317static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
318{
319 return 0x0014051c;
320}
321static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
322{
323 return 0xff << 0;
324}
325static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
326{
327 return (r >> 0) & 0xff;
328}
329static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
330{
331 return 0xff << 16;
332}
333static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
334{
335 return (r >> 16) & 0xff;
336}
337static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
338{
339 return 0x0017e2a0;
340}
341static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
342{
343 return (r >> 0) & 0x1;
344}
345static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
346{
347 return 0x00000001;
348}
349static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
350{
351 return 0x1;
352}
353static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
354{
355 return (r >> 8) & 0xf;
356}
357static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
358{
359 return 0x00000003;
360}
361static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
362{
363 return 0x300;
364}
365static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
366{
367 return (r >> 28) & 0x1;
368}
369static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
370{
371 return 0x00000001;
372}
373static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
374{
375 return 0x10000000;
376}
377static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
378{
379 return (r >> 29) & 0x1;
380}
381static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
382{
383 return 0x00000001;
384}
385static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
386{
387 return 0x20000000;
388}
389static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
390{
391 return (r >> 30) & 0x1;
392}
393static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
394{
395 return 0x00000001;
396}
397static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
398{
399 return 0x40000000;
400}
401static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
402{
403 return 0x0017e2a4;
404}
405static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
406{
407 return (r >> 0) & 0x1;
408}
409static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
410{
411 return 0x00000001;
412}
413static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
414{
415 return 0x1;
416}
417static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
418{
419 return (r >> 8) & 0xf;
420}
421static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
422{
423 return 0x00000003;
424}
425static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
426{
427 return 0x300;
428}
429static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
430{
431 return (r >> 16) & 0x1;
432}
433static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
434{
435 return 0x00000001;
436}
437static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
438{
439 return 0x10000;
440}
441static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
442{
443 return (r >> 28) & 0x1;
444}
445static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
446{
447 return 0x00000001;
448}
449static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
450{
451 return 0x10000000;
452}
453static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
454{
455 return (r >> 29) & 0x1;
456}
457static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
462{
463 return 0x20000000;
464}
465static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
466{
467 return (r >> 30) & 0x1;
468}
469static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
470{
471 return 0x00000001;
472}
473static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
474{
475 return 0x40000000;
476}
477static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
478{
479 return 0x001402a0;
480}
481static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
482{
483 return (r >> 0) & 0x1;
484}
485static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
486{
487 return 0x00000001;
488}
489static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
490{
491 return 0x1;
492}
493static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
494{
495 return 0x001402a4;
496}
497static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
498{
499 return (r >> 0) & 0x1;
500}
501static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
502{
503 return 0x00000001;
504}
505static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
506{
507 return 0x1;
508}
509static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
510{
511 return 0x001422a0;
512}
513static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
514{
515 return (r >> 0) & 0x1;
516}
517static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
518{
519 return 0x00000001;
520}
521static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
522{
523 return 0x1;
524}
525static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
526{
527 return 0x001422a4;
528}
529static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
530{
531 return (r >> 0) & 0x1;
532}
533static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
534{
535 return 0x00000001;
536}
537static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
538{
539 return 0x1;
540}
541static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
542{
543 return 0x0014058c;
544}
545static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
546{
547 return (r >> 0) & 0xffff;
548}
549static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
550{
551 return (r >> 16) & 0x1f;
552}
553#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h b/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h
new file mode 100644
index 00000000..99ad8bc0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h
@@ -0,0 +1,245 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_mc_gp106_h_
51#define _hw_mc_gp106_h_
52
53static inline u32 mc_boot_0_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 mc_boot_0_architecture_v(u32 r)
58{
59 return (r >> 24) & 0x1f;
60}
61static inline u32 mc_boot_0_implementation_v(u32 r)
62{
63 return (r >> 20) & 0xf;
64}
65static inline u32 mc_boot_0_major_revision_v(u32 r)
66{
67 return (r >> 4) & 0xf;
68}
69static inline u32 mc_boot_0_minor_revision_v(u32 r)
70{
71 return (r >> 0) & 0xf;
72}
73static inline u32 mc_intr_r(u32 i)
74{
75 return 0x00000100 + i*4;
76}
77static inline u32 mc_intr_pfifo_pending_f(void)
78{
79 return 0x100;
80}
81static inline u32 mc_intr_replayable_fault_pending_f(void)
82{
83 return 0x200;
84}
85static inline u32 mc_intr_pgraph_pending_f(void)
86{
87 return 0x1000;
88}
89static inline u32 mc_intr_pmu_pending_f(void)
90{
91 return 0x1000000;
92}
93static inline u32 mc_intr_ltc_pending_f(void)
94{
95 return 0x2000000;
96}
97static inline u32 mc_intr_priv_ring_pending_f(void)
98{
99 return 0x40000000;
100}
101static inline u32 mc_intr_pbus_pending_f(void)
102{
103 return 0x10000000;
104}
105static inline u32 mc_intr_en_r(u32 i)
106{
107 return 0x00000140 + i*4;
108}
109static inline u32 mc_intr_en_set_r(u32 i)
110{
111 return 0x00000160 + i*4;
112}
113static inline u32 mc_intr_en_clear_r(u32 i)
114{
115 return 0x00000180 + i*4;
116}
117static inline u32 mc_enable_r(void)
118{
119 return 0x00000200;
120}
121static inline u32 mc_enable_xbar_enabled_f(void)
122{
123 return 0x4;
124}
125static inline u32 mc_enable_l2_enabled_f(void)
126{
127 return 0x8;
128}
129static inline u32 mc_enable_pmedia_s(void)
130{
131 return 1;
132}
133static inline u32 mc_enable_pmedia_f(u32 v)
134{
135 return (v & 0x1) << 4;
136}
137static inline u32 mc_enable_pmedia_m(void)
138{
139 return 0x1 << 4;
140}
141static inline u32 mc_enable_pmedia_v(u32 r)
142{
143 return (r >> 4) & 0x1;
144}
145static inline u32 mc_enable_priv_ring_enabled_f(void)
146{
147 return 0x20;
148}
149static inline u32 mc_enable_ce0_m(void)
150{
151 return 0x1 << 6;
152}
153static inline u32 mc_enable_pfifo_enabled_f(void)
154{
155 return 0x100;
156}
157static inline u32 mc_enable_pgraph_enabled_f(void)
158{
159 return 0x1000;
160}
161static inline u32 mc_enable_pwr_v(u32 r)
162{
163 return (r >> 13) & 0x1;
164}
165static inline u32 mc_enable_pwr_disabled_v(void)
166{
167 return 0x00000000;
168}
169static inline u32 mc_enable_pwr_enabled_f(void)
170{
171 return 0x2000;
172}
173static inline u32 mc_enable_pfb_enabled_f(void)
174{
175 return 0x100000;
176}
177static inline u32 mc_enable_ce2_m(void)
178{
179 return 0x1 << 21;
180}
181static inline u32 mc_enable_ce2_enabled_f(void)
182{
183 return 0x200000;
184}
185static inline u32 mc_enable_blg_enabled_f(void)
186{
187 return 0x8000000;
188}
189static inline u32 mc_enable_perfmon_enabled_f(void)
190{
191 return 0x10000000;
192}
193static inline u32 mc_enable_hub_enabled_f(void)
194{
195 return 0x20000000;
196}
197static inline u32 mc_intr_ltc_r(void)
198{
199 return 0x000001c0;
200}
201static inline u32 mc_enable_pb_r(void)
202{
203 return 0x00000204;
204}
205static inline u32 mc_enable_pb_0_s(void)
206{
207 return 1;
208}
209static inline u32 mc_enable_pb_0_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 mc_enable_pb_0_m(void)
214{
215 return 0x1 << 0;
216}
217static inline u32 mc_enable_pb_0_v(u32 r)
218{
219 return (r >> 0) & 0x1;
220}
221static inline u32 mc_enable_pb_0_enabled_v(void)
222{
223 return 0x00000001;
224}
225static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
226{
227 return (v & 0x1) << (0 + i*1);
228}
229static inline u32 mc_elpg_enable_r(void)
230{
231 return 0x0000020c;
232}
233static inline u32 mc_elpg_enable_xbar_enabled_f(void)
234{
235 return 0x4;
236}
237static inline u32 mc_elpg_enable_pfb_enabled_f(void)
238{
239 return 0x100000;
240}
241static inline u32 mc_elpg_enable_hub_enabled_f(void)
242{
243 return 0x20000000;
244}
245#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h
new file mode 100644
index 00000000..a5406672
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h
@@ -0,0 +1,505 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pbdma_gp106_h_
51#define _hw_pbdma_gp106_h_
52
53static inline u32 pbdma_gp_entry1_r(void)
54{
55 return 0x10000004;
56}
57static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
58{
59 return (r >> 0) & 0xff;
60}
61static inline u32 pbdma_gp_entry1_length_f(u32 v)
62{
63 return (v & 0x1fffff) << 10;
64}
65static inline u32 pbdma_gp_entry1_length_v(u32 r)
66{
67 return (r >> 10) & 0x1fffff;
68}
69static inline u32 pbdma_gp_base_r(u32 i)
70{
71 return 0x00040048 + i*8192;
72}
73static inline u32 pbdma_gp_base__size_1_v(void)
74{
75 return 0x00000004;
76}
77static inline u32 pbdma_gp_base_offset_f(u32 v)
78{
79 return (v & 0x1fffffff) << 3;
80}
81static inline u32 pbdma_gp_base_rsvd_s(void)
82{
83 return 3;
84}
85static inline u32 pbdma_gp_base_hi_r(u32 i)
86{
87 return 0x0004004c + i*8192;
88}
89static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
90{
91 return (v & 0xff) << 0;
92}
93static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
94{
95 return (v & 0x1f) << 16;
96}
97static inline u32 pbdma_gp_fetch_r(u32 i)
98{
99 return 0x00040050 + i*8192;
100}
101static inline u32 pbdma_gp_get_r(u32 i)
102{
103 return 0x00040014 + i*8192;
104}
105static inline u32 pbdma_gp_put_r(u32 i)
106{
107 return 0x00040000 + i*8192;
108}
109static inline u32 pbdma_pb_fetch_r(u32 i)
110{
111 return 0x00040054 + i*8192;
112}
113static inline u32 pbdma_pb_fetch_hi_r(u32 i)
114{
115 return 0x00040058 + i*8192;
116}
117static inline u32 pbdma_get_r(u32 i)
118{
119 return 0x00040018 + i*8192;
120}
121static inline u32 pbdma_get_hi_r(u32 i)
122{
123 return 0x0004001c + i*8192;
124}
125static inline u32 pbdma_put_r(u32 i)
126{
127 return 0x0004005c + i*8192;
128}
129static inline u32 pbdma_put_hi_r(u32 i)
130{
131 return 0x00040060 + i*8192;
132}
133static inline u32 pbdma_formats_r(u32 i)
134{
135 return 0x0004009c + i*8192;
136}
137static inline u32 pbdma_formats_gp_fermi0_f(void)
138{
139 return 0x0;
140}
141static inline u32 pbdma_formats_pb_fermi1_f(void)
142{
143 return 0x100;
144}
145static inline u32 pbdma_formats_mp_fermi0_f(void)
146{
147 return 0x0;
148}
149static inline u32 pbdma_pb_header_r(u32 i)
150{
151 return 0x00040084 + i*8192;
152}
153static inline u32 pbdma_pb_header_priv_user_f(void)
154{
155 return 0x0;
156}
157static inline u32 pbdma_pb_header_method_zero_f(void)
158{
159 return 0x0;
160}
161static inline u32 pbdma_pb_header_subchannel_zero_f(void)
162{
163 return 0x0;
164}
165static inline u32 pbdma_pb_header_level_main_f(void)
166{
167 return 0x0;
168}
169static inline u32 pbdma_pb_header_first_true_f(void)
170{
171 return 0x400000;
172}
173static inline u32 pbdma_pb_header_type_inc_f(void)
174{
175 return 0x20000000;
176}
177static inline u32 pbdma_pb_header_type_non_inc_f(void)
178{
179 return 0x60000000;
180}
181static inline u32 pbdma_hdr_shadow_r(u32 i)
182{
183 return 0x00040118 + i*8192;
184}
185static inline u32 pbdma_subdevice_r(u32 i)
186{
187 return 0x00040094 + i*8192;
188}
189static inline u32 pbdma_subdevice_id_f(u32 v)
190{
191 return (v & 0xfff) << 0;
192}
193static inline u32 pbdma_subdevice_status_active_f(void)
194{
195 return 0x10000000;
196}
197static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
198{
199 return 0x20000000;
200}
201static inline u32 pbdma_method0_r(u32 i)
202{
203 return 0x000400c0 + i*8192;
204}
205static inline u32 pbdma_method0_fifo_size_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 pbdma_method0_addr_f(u32 v)
210{
211 return (v & 0xfff) << 2;
212}
213static inline u32 pbdma_method0_addr_v(u32 r)
214{
215 return (r >> 2) & 0xfff;
216}
217static inline u32 pbdma_method0_subch_v(u32 r)
218{
219 return (r >> 16) & 0x7;
220}
221static inline u32 pbdma_method0_first_true_f(void)
222{
223 return 0x400000;
224}
225static inline u32 pbdma_method0_valid_true_f(void)
226{
227 return 0x80000000;
228}
229static inline u32 pbdma_method1_r(u32 i)
230{
231 return 0x000400c8 + i*8192;
232}
233static inline u32 pbdma_method2_r(u32 i)
234{
235 return 0x000400d0 + i*8192;
236}
237static inline u32 pbdma_method3_r(u32 i)
238{
239 return 0x000400d8 + i*8192;
240}
241static inline u32 pbdma_data0_r(u32 i)
242{
243 return 0x000400c4 + i*8192;
244}
245static inline u32 pbdma_target_r(u32 i)
246{
247 return 0x000400ac + i*8192;
248}
249static inline u32 pbdma_target_engine_sw_f(void)
250{
251 return 0x1f;
252}
253static inline u32 pbdma_acquire_r(u32 i)
254{
255 return 0x00040030 + i*8192;
256}
257static inline u32 pbdma_acquire_retry_man_2_f(void)
258{
259 return 0x2;
260}
261static inline u32 pbdma_acquire_retry_exp_2_f(void)
262{
263 return 0x100;
264}
265static inline u32 pbdma_acquire_timeout_exp_max_f(void)
266{
267 return 0x7800;
268}
269static inline u32 pbdma_acquire_timeout_man_max_f(void)
270{
271 return 0x7fff8000;
272}
273static inline u32 pbdma_acquire_timeout_en_disable_f(void)
274{
275 return 0x0;
276}
277static inline u32 pbdma_status_r(u32 i)
278{
279 return 0x00040100 + i*8192;
280}
281static inline u32 pbdma_channel_r(u32 i)
282{
283 return 0x00040120 + i*8192;
284}
285static inline u32 pbdma_signature_r(u32 i)
286{
287 return 0x00040010 + i*8192;
288}
289static inline u32 pbdma_signature_hw_valid_f(void)
290{
291 return 0xface;
292}
293static inline u32 pbdma_signature_sw_zero_f(void)
294{
295 return 0x0;
296}
297static inline u32 pbdma_userd_r(u32 i)
298{
299 return 0x00040008 + i*8192;
300}
301static inline u32 pbdma_userd_target_vid_mem_f(void)
302{
303 return 0x0;
304}
305static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
306{
307 return 0x2;
308}
309static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
310{
311 return 0x3;
312}
313static inline u32 pbdma_userd_addr_f(u32 v)
314{
315 return (v & 0x7fffff) << 9;
316}
317static inline u32 pbdma_userd_hi_r(u32 i)
318{
319 return 0x0004000c + i*8192;
320}
321static inline u32 pbdma_userd_hi_addr_f(u32 v)
322{
323 return (v & 0xff) << 0;
324}
325static inline u32 pbdma_hce_ctrl_r(u32 i)
326{
327 return 0x000400e4 + i*8192;
328}
329static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
330{
331 return 0x20;
332}
333static inline u32 pbdma_intr_0_r(u32 i)
334{
335 return 0x00040108 + i*8192;
336}
337static inline u32 pbdma_intr_0_memreq_v(u32 r)
338{
339 return (r >> 0) & 0x1;
340}
341static inline u32 pbdma_intr_0_memreq_pending_f(void)
342{
343 return 0x1;
344}
345static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
346{
347 return 0x2;
348}
349static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
350{
351 return 0x4;
352}
353static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
354{
355 return 0x8;
356}
357static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
358{
359 return 0x10;
360}
361static inline u32 pbdma_intr_0_memflush_pending_f(void)
362{
363 return 0x20;
364}
365static inline u32 pbdma_intr_0_memop_pending_f(void)
366{
367 return 0x40;
368}
369static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
370{
371 return 0x80;
372}
373static inline u32 pbdma_intr_0_lbreq_pending_f(void)
374{
375 return 0x100;
376}
377static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
378{
379 return 0x200;
380}
381static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
382{
383 return 0x400;
384}
385static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
386{
387 return 0x800;
388}
389static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
390{
391 return 0x1000;
392}
393static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
394{
395 return 0x2000;
396}
397static inline u32 pbdma_intr_0_gpptr_pending_f(void)
398{
399 return 0x4000;
400}
401static inline u32 pbdma_intr_0_gpentry_pending_f(void)
402{
403 return 0x8000;
404}
405static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
406{
407 return 0x10000;
408}
409static inline u32 pbdma_intr_0_pbptr_pending_f(void)
410{
411 return 0x20000;
412}
413static inline u32 pbdma_intr_0_pbentry_pending_f(void)
414{
415 return 0x40000;
416}
417static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
418{
419 return 0x80000;
420}
421static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
422{
423 return 0x100000;
424}
425static inline u32 pbdma_intr_0_method_pending_f(void)
426{
427 return 0x200000;
428}
429static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
430{
431 return 0x400000;
432}
433static inline u32 pbdma_intr_0_device_pending_f(void)
434{
435 return 0x800000;
436}
437static inline u32 pbdma_intr_0_semaphore_pending_f(void)
438{
439 return 0x2000000;
440}
441static inline u32 pbdma_intr_0_acquire_pending_f(void)
442{
443 return 0x4000000;
444}
445static inline u32 pbdma_intr_0_pri_pending_f(void)
446{
447 return 0x8000000;
448}
449static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
450{
451 return 0x20000000;
452}
453static inline u32 pbdma_intr_0_pbseg_pending_f(void)
454{
455 return 0x40000000;
456}
457static inline u32 pbdma_intr_0_signature_pending_f(void)
458{
459 return 0x80000000;
460}
461static inline u32 pbdma_intr_1_r(u32 i)
462{
463 return 0x00040148 + i*8192;
464}
465static inline u32 pbdma_intr_en_0_r(u32 i)
466{
467 return 0x0004010c + i*8192;
468}
469static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
470{
471 return 0x100;
472}
473static inline u32 pbdma_intr_en_1_r(u32 i)
474{
475 return 0x0004014c + i*8192;
476}
477static inline u32 pbdma_intr_stall_r(u32 i)
478{
479 return 0x0004013c + i*8192;
480}
481static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
482{
483 return 0x100;
484}
485static inline u32 pbdma_udma_nop_r(void)
486{
487 return 0x00000008;
488}
489static inline u32 pbdma_runlist_timeslice_r(u32 i)
490{
491 return 0x000400f8 + i*8192;
492}
493static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
494{
495 return 0x80;
496}
497static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
498{
499 return 0x3000;
500}
501static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
502{
503 return 0x10000000;
504}
505#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h b/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h
new file mode 100644
index 00000000..cd3501a8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_perf_gp106_h_
51#define _hw_perf_gp106_h_
52
53static inline u32 perf_pmasys_control_r(void)
54{
55 return 0x001b4000;
56}
57static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
58{
59 return (r >> 4) & 0x1;
60}
61static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
66{
67 return 0x10;
68}
69static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
70{
71 return (v & 0x1) << 5;
72}
73static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
74{
75 return (r >> 5) & 0x1;
76}
77static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
82{
83 return 0x20;
84}
85static inline u32 perf_pmasys_mem_block_r(void)
86{
87 return 0x001b4070;
88}
89static inline u32 perf_pmasys_mem_block_base_f(u32 v)
90{
91 return (v & 0xfffffff) << 0;
92}
93static inline u32 perf_pmasys_mem_block_target_f(u32 v)
94{
95 return (v & 0x3) << 28;
96}
97static inline u32 perf_pmasys_mem_block_target_v(u32 r)
98{
99 return (r >> 28) & 0x3;
100}
101static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
106{
107 return 0x0;
108}
109static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
118{
119 return 0x00000003;
120}
121static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
122{
123 return 0x30000000;
124}
125static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
130{
131 return (r >> 31) & 0x1;
132}
133static inline u32 perf_pmasys_mem_block_valid_true_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 perf_pmasys_mem_block_valid_true_f(void)
138{
139 return 0x80000000;
140}
141static inline u32 perf_pmasys_mem_block_valid_false_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 perf_pmasys_mem_block_valid_false_f(void)
146{
147 return 0x0;
148}
149static inline u32 perf_pmasys_outbase_r(void)
150{
151 return 0x001b4074;
152}
153static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
154{
155 return (v & 0x7ffffff) << 5;
156}
157static inline u32 perf_pmasys_outbaseupper_r(void)
158{
159 return 0x001b4078;
160}
161static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
162{
163 return (v & 0xff) << 0;
164}
165static inline u32 perf_pmasys_outsize_r(void)
166{
167 return 0x001b407c;
168}
169static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
170{
171 return (v & 0x7ffffff) << 5;
172}
173static inline u32 perf_pmasys_mem_bytes_r(void)
174{
175 return 0x001b4084;
176}
177static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 perf_pmasys_mem_bump_r(void)
182{
183 return 0x001b4088;
184}
185static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
186{
187 return (v & 0xfffffff) << 4;
188}
189static inline u32 perf_pmasys_enginestatus_r(void)
190{
191 return 0x001b40a4;
192}
193static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
194{
195 return (v & 0x1) << 4;
196}
197static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
198{
199 return 0x00000001;
200}
201static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
202{
203 return 0x10;
204}
205#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h
new file mode 100644
index 00000000..0eb2187a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringmaster_gp106_h_
51#define _hw_pri_ringmaster_gp106_h_
52
53static inline u32 pri_ringmaster_command_r(void)
54{
55 return 0x0012004c;
56}
57static inline u32 pri_ringmaster_command_cmd_m(void)
58{
59 return 0x3f << 0;
60}
61static inline u32 pri_ringmaster_command_cmd_v(u32 r)
62{
63 return (r >> 0) & 0x3f;
64}
65static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
66{
67 return 0x00000000;
68}
69static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
70{
71 return 0x1;
72}
73static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
74{
75 return 0x2;
76}
77static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
78{
79 return 0x3;
80}
81static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
82{
83 return 0x0;
84}
85static inline u32 pri_ringmaster_command_data_r(void)
86{
87 return 0x00120048;
88}
89static inline u32 pri_ringmaster_start_results_r(void)
90{
91 return 0x00120050;
92}
93static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 pri_ringmaster_intr_status0_r(void)
102{
103 return 0x00120058;
104}
105static inline u32 pri_ringmaster_intr_status1_r(void)
106{
107 return 0x0012005c;
108}
109static inline u32 pri_ringmaster_global_ctl_r(void)
110{
111 return 0x00120060;
112}
113static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
114{
115 return 0x1;
116}
117static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
118{
119 return 0x0;
120}
121static inline u32 pri_ringmaster_enum_fbp_r(void)
122{
123 return 0x00120074;
124}
125static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
126{
127 return (r >> 0) & 0x1f;
128}
129static inline u32 pri_ringmaster_enum_gpc_r(void)
130{
131 return 0x00120078;
132}
133static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
134{
135 return (r >> 0) & 0x1f;
136}
137static inline u32 pri_ringmaster_enum_ltc_r(void)
138{
139 return 0x0012006c;
140}
141static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
142{
143 return (r >> 0) & 0x1f;
144}
145#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h
new file mode 100644
index 00000000..a22d6a05
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_sys_gp106_h_
51#define _hw_pri_ringstation_sys_gp106_h_
52
53static inline u32 pri_ringstation_sys_master_config_r(u32 i)
54{
55 return 0x00122300 + i*4;
56}
57static inline u32 pri_ringstation_sys_decode_config_r(void)
58{
59 return 0x00122204;
60}
61static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
62{
63 return 0x7 << 0;
64}
65static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
66{
67 return 0x1;
68}
69#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
new file mode 100644
index 00000000..0b4b86b1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_proj_gp106_h_
51#define _hw_proj_gp106_h_
52
53static inline u32 proj_gpc_base_v(void)
54{
55 return 0x00500000;
56}
57static inline u32 proj_gpc_shared_base_v(void)
58{
59 return 0x00418000;
60}
61static inline u32 proj_gpc_stride_v(void)
62{
63 return 0x00008000;
64}
65static inline u32 proj_ltc_stride_v(void)
66{
67 return 0x00002000;
68}
69static inline u32 proj_lts_stride_v(void)
70{
71 return 0x00000200;
72}
73static inline u32 proj_fbpa_stride_v(void)
74{
75 return 0x00004000;
76}
77static inline u32 proj_ppc_in_gpc_base_v(void)
78{
79 return 0x00003000;
80}
81static inline u32 proj_ppc_in_gpc_stride_v(void)
82{
83 return 0x00000200;
84}
85static inline u32 proj_rop_base_v(void)
86{
87 return 0x00410000;
88}
89static inline u32 proj_rop_shared_base_v(void)
90{
91 return 0x00408800;
92}
93static inline u32 proj_rop_stride_v(void)
94{
95 return 0x00000400;
96}
97static inline u32 proj_tpc_in_gpc_base_v(void)
98{
99 return 0x00004000;
100}
101static inline u32 proj_tpc_in_gpc_stride_v(void)
102{
103 return 0x00000800;
104}
105static inline u32 proj_tpc_in_gpc_shared_base_v(void)
106{
107 return 0x00001800;
108}
109static inline u32 proj_host_num_pbdma_v(void)
110{
111 return 0x00000004;
112}
113static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
114{
115 return 0x00000005;
116}
117static inline u32 proj_scal_litter_num_fbps_v(void)
118{
119 return 0x00000006;
120}
121static inline u32 proj_scal_litter_num_fbpas_v(void)
122{
123 return 0x00000006;
124}
125static inline u32 proj_scal_litter_num_gpcs_v(void)
126{
127 return 0x00000006;
128}
129static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
130{
131 return 0x00000003;
132}
133static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
134{
135 return 0x00000002;
136}
137static inline u32 proj_scal_litter_num_zcull_banks_v(void)
138{
139 return 0x00000004;
140}
141static inline u32 proj_scal_max_gpcs_v(void)
142{
143 return 0x00000020;
144}
145static inline u32 proj_scal_max_tpc_per_gpc_v(void)
146{
147 return 0x00000008;
148}
149#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h
new file mode 100644
index 00000000..b4dfea0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h
@@ -0,0 +1,841 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pwr_gp106_h_
51#define _hw_pwr_gp106_h_
52
53static inline u32 pwr_falcon_irqsset_r(void)
54{
55 return 0x0010a000;
56}
57static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 pwr_falcon_irqsclr_r(void)
62{
63 return 0x0010a004;
64}
65static inline u32 pwr_falcon_irqstat_r(void)
66{
67 return 0x0010a008;
68}
69static inline u32 pwr_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 pwr_falcon_irqmode_r(void)
82{
83 return 0x0010a00c;
84}
85static inline u32 pwr_falcon_irqmset_r(void)
86{
87 return 0x0010a010;
88}
89static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
90{
91 return (v & 0x1) << 0;
92}
93static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
94{
95 return (v & 0x1) << 1;
96}
97static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
98{
99 return (v & 0x1) << 2;
100}
101static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
102{
103 return (v & 0x1) << 3;
104}
105static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
106{
107 return (v & 0x1) << 4;
108}
109static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
114{
115 return (v & 0x1) << 6;
116}
117static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
118{
119 return (v & 0x1) << 7;
120}
121static inline u32 pwr_falcon_irqmclr_r(void)
122{
123 return 0x0010a014;
124}
125static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
126{
127 return (v & 0x1) << 0;
128}
129static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
130{
131 return (v & 0x1) << 1;
132}
133static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
138{
139 return (v & 0x1) << 3;
140}
141static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
142{
143 return (v & 0x1) << 4;
144}
145static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
146{
147 return (v & 0x1) << 5;
148}
149static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
150{
151 return (v & 0x1) << 6;
152}
153static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
154{
155 return (v & 0x1) << 7;
156}
157static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
158{
159 return (v & 0xff) << 8;
160}
161static inline u32 pwr_falcon_irqmask_r(void)
162{
163 return 0x0010a018;
164}
165static inline u32 pwr_falcon_irqdest_r(void)
166{
167 return 0x0010a01c;
168}
169static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
170{
171 return (v & 0x1) << 0;
172}
173static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
174{
175 return (v & 0x1) << 1;
176}
177static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
178{
179 return (v & 0x1) << 2;
180}
181static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
182{
183 return (v & 0x1) << 3;
184}
185static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
186{
187 return (v & 0x1) << 4;
188}
189static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
190{
191 return (v & 0x1) << 5;
192}
193static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
198{
199 return (v & 0x1) << 7;
200}
201static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
202{
203 return (v & 0xff) << 8;
204}
205static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
206{
207 return (v & 0x1) << 16;
208}
209static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
210{
211 return (v & 0x1) << 17;
212}
213static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
214{
215 return (v & 0x1) << 18;
216}
217static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
218{
219 return (v & 0x1) << 19;
220}
221static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
222{
223 return (v & 0x1) << 20;
224}
225static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
226{
227 return (v & 0x1) << 21;
228}
229static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
230{
231 return (v & 0x1) << 22;
232}
233static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
234{
235 return (v & 0x1) << 23;
236}
237static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
238{
239 return (v & 0xff) << 24;
240}
241static inline u32 pwr_falcon_curctx_r(void)
242{
243 return 0x0010a050;
244}
245static inline u32 pwr_falcon_nxtctx_r(void)
246{
247 return 0x0010a054;
248}
249static inline u32 pwr_falcon_mailbox0_r(void)
250{
251 return 0x0010a040;
252}
253static inline u32 pwr_falcon_mailbox1_r(void)
254{
255 return 0x0010a044;
256}
257static inline u32 pwr_falcon_itfen_r(void)
258{
259 return 0x0010a048;
260}
261static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
262{
263 return 0x1;
264}
265static inline u32 pwr_falcon_idlestate_r(void)
266{
267 return 0x0010a04c;
268}
269static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
270{
271 return (r >> 0) & 0x1;
272}
273static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
274{
275 return (r >> 1) & 0x7fff;
276}
277static inline u32 pwr_falcon_os_r(void)
278{
279 return 0x0010a080;
280}
281static inline u32 pwr_falcon_engctl_r(void)
282{
283 return 0x0010a0a4;
284}
285static inline u32 pwr_falcon_cpuctl_r(void)
286{
287 return 0x0010a100;
288}
289static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
290{
291 return (v & 0x1) << 1;
292}
293static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
294{
295 return (v & 0x1) << 4;
296}
297static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
298{
299 return 0x1 << 4;
300}
301static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
302{
303 return (r >> 4) & 0x1;
304}
305static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
306{
307 return (v & 0x1) << 6;
308}
309static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
310{
311 return 0x1 << 6;
312}
313static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
314{
315 return (r >> 6) & 0x1;
316}
317static inline u32 pwr_falcon_cpuctl_alias_r(void)
318{
319 return 0x0010a130;
320}
321static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
322{
323 return (v & 0x1) << 1;
324}
325static inline u32 pwr_pmu_scpctl_stat_r(void)
326{
327 return 0x0010ac08;
328}
329static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
330{
331 return (v & 0x1) << 20;
332}
333static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
334{
335 return 0x1 << 20;
336}
337static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
338{
339 return (r >> 20) & 0x1;
340}
341static inline u32 pwr_falcon_imemc_r(u32 i)
342{
343 return 0x0010a180 + i*16;
344}
345static inline u32 pwr_falcon_imemc_offs_f(u32 v)
346{
347 return (v & 0x3f) << 2;
348}
349static inline u32 pwr_falcon_imemc_blk_f(u32 v)
350{
351 return (v & 0xff) << 8;
352}
353static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
354{
355 return (v & 0x1) << 24;
356}
357static inline u32 pwr_falcon_imemd_r(u32 i)
358{
359 return 0x0010a184 + i*16;
360}
361static inline u32 pwr_falcon_imemt_r(u32 i)
362{
363 return 0x0010a188 + i*16;
364}
365static inline u32 pwr_falcon_sctl_r(void)
366{
367 return 0x0010a240;
368}
369static inline u32 pwr_falcon_mmu_phys_sec_r(void)
370{
371 return 0x00100ce4;
372}
373static inline u32 pwr_falcon_bootvec_r(void)
374{
375 return 0x0010a104;
376}
377static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
378{
379 return (v & 0xffffffff) << 0;
380}
381static inline u32 pwr_falcon_dmactl_r(void)
382{
383 return 0x0010a10c;
384}
385static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
386{
387 return 0x1 << 1;
388}
389static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
390{
391 return 0x1 << 2;
392}
393static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
394{
395 return (v & 0x1) << 0;
396}
397static inline u32 pwr_falcon_hwcfg_r(void)
398{
399 return 0x0010a108;
400}
401static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
402{
403 return (r >> 0) & 0x1ff;
404}
405static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
406{
407 return (r >> 9) & 0x1ff;
408}
409static inline u32 pwr_falcon_dmatrfbase_r(void)
410{
411 return 0x0010a110;
412}
413static inline u32 pwr_falcon_dmatrfbase1_r(void)
414{
415 return 0x0010a128;
416}
417static inline u32 pwr_falcon_dmatrfmoffs_r(void)
418{
419 return 0x0010a114;
420}
421static inline u32 pwr_falcon_dmatrfcmd_r(void)
422{
423 return 0x0010a118;
424}
425static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
426{
427 return (v & 0x1) << 4;
428}
429static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
430{
431 return (v & 0x1) << 5;
432}
433static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
434{
435 return (v & 0x7) << 8;
436}
437static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
438{
439 return (v & 0x7) << 12;
440}
441static inline u32 pwr_falcon_dmatrffboffs_r(void)
442{
443 return 0x0010a11c;
444}
445static inline u32 pwr_falcon_exterraddr_r(void)
446{
447 return 0x0010a168;
448}
449static inline u32 pwr_falcon_exterrstat_r(void)
450{
451 return 0x0010a16c;
452}
453static inline u32 pwr_falcon_exterrstat_valid_m(void)
454{
455 return 0x1 << 31;
456}
457static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
458{
459 return (r >> 31) & 0x1;
460}
461static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
462{
463 return 0x00000001;
464}
465static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
466{
467 return 0x0010a200;
468}
469static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
470{
471 return 4;
472}
473static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
474{
475 return (v & 0xf) << 0;
476}
477static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
478{
479 return 0xf << 0;
480}
481static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
482{
483 return (r >> 0) & 0xf;
484}
485static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
486{
487 return 0x8;
488}
489static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
490{
491 return 0xe;
492}
493static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
494{
495 return (v & 0x1f) << 8;
496}
497static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
498{
499 return 0x0010a20c;
500}
501static inline u32 pwr_falcon_dmemc_r(u32 i)
502{
503 return 0x0010a1c0 + i*8;
504}
505static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
506{
507 return (v & 0x3f) << 2;
508}
509static inline u32 pwr_falcon_dmemc_offs_m(void)
510{
511 return 0x3f << 2;
512}
513static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
514{
515 return (v & 0xff) << 8;
516}
517static inline u32 pwr_falcon_dmemc_blk_m(void)
518{
519 return 0xff << 8;
520}
521static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
522{
523 return (v & 0x1) << 24;
524}
525static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
526{
527 return (v & 0x1) << 25;
528}
529static inline u32 pwr_falcon_dmemd_r(u32 i)
530{
531 return 0x0010a1c4 + i*8;
532}
533static inline u32 pwr_pmu_new_instblk_r(void)
534{
535 return 0x0010a480;
536}
537static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
538{
539 return (v & 0xfffffff) << 0;
540}
541static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
542{
543 return 0x0;
544}
545static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
546{
547 return 0x20000000;
548}
549static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
550{
551 return 0x30000000;
552}
553static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
554{
555 return (v & 0x1) << 30;
556}
557static inline u32 pwr_pmu_mutex_id_r(void)
558{
559 return 0x0010a488;
560}
561static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
562{
563 return (r >> 0) & 0xff;
564}
565static inline u32 pwr_pmu_mutex_id_value_init_v(void)
566{
567 return 0x00000000;
568}
569static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
570{
571 return 0x000000ff;
572}
573static inline u32 pwr_pmu_mutex_id_release_r(void)
574{
575 return 0x0010a48c;
576}
577static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
578{
579 return (v & 0xff) << 0;
580}
581static inline u32 pwr_pmu_mutex_id_release_value_m(void)
582{
583 return 0xff << 0;
584}
585static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
586{
587 return 0x00000000;
588}
589static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
590{
591 return 0x0;
592}
593static inline u32 pwr_pmu_mutex_r(u32 i)
594{
595 return 0x0010a580 + i*4;
596}
597static inline u32 pwr_pmu_mutex__size_1_v(void)
598{
599 return 0x00000010;
600}
601static inline u32 pwr_pmu_mutex_value_f(u32 v)
602{
603 return (v & 0xff) << 0;
604}
605static inline u32 pwr_pmu_mutex_value_v(u32 r)
606{
607 return (r >> 0) & 0xff;
608}
609static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
610{
611 return 0x0;
612}
613static inline u32 pwr_pmu_queue_head_r(u32 i)
614{
615 return 0x0010a4a0 + i*4;
616}
617static inline u32 pwr_pmu_queue_head__size_1_v(void)
618{
619 return 0x00000004;
620}
621static inline u32 pwr_pmu_queue_head_address_f(u32 v)
622{
623 return (v & 0xffffffff) << 0;
624}
625static inline u32 pwr_pmu_queue_head_address_v(u32 r)
626{
627 return (r >> 0) & 0xffffffff;
628}
629static inline u32 pwr_pmu_queue_tail_r(u32 i)
630{
631 return 0x0010a4b0 + i*4;
632}
633static inline u32 pwr_pmu_queue_tail__size_1_v(void)
634{
635 return 0x00000004;
636}
637static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
638{
639 return (v & 0xffffffff) << 0;
640}
641static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
642{
643 return (r >> 0) & 0xffffffff;
644}
645static inline u32 pwr_pmu_msgq_head_r(void)
646{
647 return 0x0010a4c8;
648}
649static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
650{
651 return (v & 0xffffffff) << 0;
652}
653static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
654{
655 return (r >> 0) & 0xffffffff;
656}
657static inline u32 pwr_pmu_msgq_tail_r(void)
658{
659 return 0x0010a4cc;
660}
661static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
662{
663 return (v & 0xffffffff) << 0;
664}
665static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
666{
667 return (r >> 0) & 0xffffffff;
668}
669static inline u32 pwr_pmu_idle_mask_r(u32 i)
670{
671 return 0x0010a504 + i*16;
672}
673static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
674{
675 return 0x1;
676}
677static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
678{
679 return 0x200000;
680}
681static inline u32 pwr_pmu_idle_count_r(u32 i)
682{
683 return 0x0010a508 + i*16;
684}
685static inline u32 pwr_pmu_idle_count_value_f(u32 v)
686{
687 return (v & 0x7fffffff) << 0;
688}
689static inline u32 pwr_pmu_idle_count_value_v(u32 r)
690{
691 return (r >> 0) & 0x7fffffff;
692}
693static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
694{
695 return (v & 0x1) << 31;
696}
697static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
698{
699 return 0x0010a50c + i*16;
700}
701static inline u32 pwr_pmu_idle_ctrl_value_m(void)
702{
703 return 0x3 << 0;
704}
705static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
706{
707 return 0x2;
708}
709static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
710{
711 return 0x3;
712}
713static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
714{
715 return 0x1 << 2;
716}
717static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
718{
719 return 0x0;
720}
721static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
722{
723 return 0x0010a9f0 + i*8;
724}
725static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
726{
727 return 0x0010a9f4 + i*8;
728}
729static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
730{
731 return 0x0010aa30 + i*8;
732}
733static inline u32 pwr_pmu_debug_r(u32 i)
734{
735 return 0x0010a5c0 + i*4;
736}
737static inline u32 pwr_pmu_debug__size_1_v(void)
738{
739 return 0x00000004;
740}
741static inline u32 pwr_pmu_mailbox_r(u32 i)
742{
743 return 0x0010a450 + i*4;
744}
745static inline u32 pwr_pmu_mailbox__size_1_v(void)
746{
747 return 0x0000000c;
748}
749static inline u32 pwr_pmu_bar0_addr_r(void)
750{
751 return 0x0010a7a0;
752}
753static inline u32 pwr_pmu_bar0_data_r(void)
754{
755 return 0x0010a7a4;
756}
757static inline u32 pwr_pmu_bar0_ctl_r(void)
758{
759 return 0x0010a7ac;
760}
761static inline u32 pwr_pmu_bar0_timeout_r(void)
762{
763 return 0x0010a7a8;
764}
765static inline u32 pwr_pmu_bar0_fecs_error_r(void)
766{
767 return 0x0010a988;
768}
769static inline u32 pwr_pmu_bar0_error_status_r(void)
770{
771 return 0x0010a7b0;
772}
773static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
774{
775 return 0x0010a6c0 + i*4;
776}
777static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
778{
779 return 0x0010a6e8 + i*4;
780}
781static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
782{
783 return 0x0010a710 + i*4;
784}
785static inline u32 pwr_pmu_pg_intren_r(u32 i)
786{
787 return 0x0010a760 + i*4;
788}
789static inline u32 pwr_fbif_transcfg_r(u32 i)
790{
791 return 0x0010ae00 + i*4;
792}
793static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
794{
795 return 0x0;
796}
797static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
798{
799 return 0x1;
800}
801static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
802{
803 return 0x2;
804}
805static inline u32 pwr_fbif_transcfg_mem_type_s(void)
806{
807 return 1;
808}
809static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
810{
811 return (v & 0x1) << 2;
812}
813static inline u32 pwr_fbif_transcfg_mem_type_m(void)
814{
815 return 0x1 << 2;
816}
817static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
818{
819 return (r >> 2) & 0x1;
820}
821static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
822{
823 return 0x0;
824}
825static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
826{
827 return 0x4;
828}
829static inline u32 pwr_falcon_engine_r(void)
830{
831 return 0x0010a3c0;
832}
833static inline u32 pwr_falcon_engine_reset_true_f(void)
834{
835 return 0x1;
836}
837static inline u32 pwr_falcon_engine_reset_false_f(void)
838{
839 return 0x0;
840}
841#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h
new file mode 100644
index 00000000..b325affc
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h
@@ -0,0 +1,477 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ram_gp106_h_
51#define _hw_ram_gp106_h_
52
53static inline u32 ram_in_ramfc_s(void)
54{
55 return 4096;
56}
57static inline u32 ram_in_ramfc_w(void)
58{
59 return 0;
60}
61static inline u32 ram_in_page_dir_base_target_f(u32 v)
62{
63 return (v & 0x3) << 0;
64}
65static inline u32 ram_in_page_dir_base_target_w(void)
66{
67 return 128;
68}
69static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
70{
71 return 0x0;
72}
73static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
74{
75 return 0x2;
76}
77static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
78{
79 return 0x3;
80}
81static inline u32 ram_in_page_dir_base_vol_w(void)
82{
83 return 128;
84}
85static inline u32 ram_in_page_dir_base_vol_true_f(void)
86{
87 return 0x4;
88}
89static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
90{
91 return (v & 0x1) << 4;
92}
93static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
94{
95 return 0x1 << 4;
96}
97static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
98{
99 return 128;
100}
101static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
102{
103 return 0x10;
104}
105static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
106{
107 return (v & 0x1) << 5;
108}
109static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
110{
111 return 0x1 << 5;
112}
113static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
114{
115 return 128;
116}
117static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
118{
119 return 0x20;
120}
121static inline u32 ram_in_big_page_size_f(u32 v)
122{
123 return (v & 0x1) << 11;
124}
125static inline u32 ram_in_big_page_size_m(void)
126{
127 return 0x1 << 11;
128}
129static inline u32 ram_in_big_page_size_w(void)
130{
131 return 128;
132}
133static inline u32 ram_in_big_page_size_128kb_f(void)
134{
135 return 0x0;
136}
137static inline u32 ram_in_big_page_size_64kb_f(void)
138{
139 return 0x800;
140}
141static inline u32 ram_in_page_dir_base_lo_f(u32 v)
142{
143 return (v & 0xfffff) << 12;
144}
145static inline u32 ram_in_page_dir_base_lo_w(void)
146{
147 return 128;
148}
149static inline u32 ram_in_page_dir_base_hi_f(u32 v)
150{
151 return (v & 0xffffffff) << 0;
152}
153static inline u32 ram_in_page_dir_base_hi_w(void)
154{
155 return 129;
156}
157static inline u32 ram_in_adr_limit_lo_f(u32 v)
158{
159 return (v & 0xfffff) << 12;
160}
161static inline u32 ram_in_adr_limit_lo_w(void)
162{
163 return 130;
164}
165static inline u32 ram_in_adr_limit_hi_f(u32 v)
166{
167 return (v & 0xffffffff) << 0;
168}
169static inline u32 ram_in_adr_limit_hi_w(void)
170{
171 return 131;
172}
173static inline u32 ram_in_engine_cs_w(void)
174{
175 return 132;
176}
177static inline u32 ram_in_engine_cs_wfi_v(void)
178{
179 return 0x00000000;
180}
181static inline u32 ram_in_engine_cs_wfi_f(void)
182{
183 return 0x0;
184}
185static inline u32 ram_in_engine_cs_fg_v(void)
186{
187 return 0x00000001;
188}
189static inline u32 ram_in_engine_cs_fg_f(void)
190{
191 return 0x8;
192}
193static inline u32 ram_in_gr_cs_w(void)
194{
195 return 132;
196}
197static inline u32 ram_in_gr_cs_wfi_f(void)
198{
199 return 0x0;
200}
201static inline u32 ram_in_gr_wfi_target_w(void)
202{
203 return 132;
204}
205static inline u32 ram_in_gr_wfi_mode_w(void)
206{
207 return 132;
208}
209static inline u32 ram_in_gr_wfi_mode_physical_v(void)
210{
211 return 0x00000000;
212}
213static inline u32 ram_in_gr_wfi_mode_physical_f(void)
214{
215 return 0x0;
216}
217static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
218{
219 return 0x00000001;
220}
221static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
222{
223 return 0x4;
224}
225static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
226{
227 return (v & 0xfffff) << 12;
228}
229static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
230{
231 return 132;
232}
233static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
234{
235 return (v & 0xff) << 0;
236}
237static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
238{
239 return 133;
240}
241static inline u32 ram_in_base_shift_v(void)
242{
243 return 0x0000000c;
244}
245static inline u32 ram_in_alloc_size_v(void)
246{
247 return 0x00001000;
248}
249static inline u32 ram_fc_size_val_v(void)
250{
251 return 0x00000200;
252}
253static inline u32 ram_fc_gp_put_w(void)
254{
255 return 0;
256}
257static inline u32 ram_fc_userd_w(void)
258{
259 return 2;
260}
261static inline u32 ram_fc_userd_hi_w(void)
262{
263 return 3;
264}
265static inline u32 ram_fc_signature_w(void)
266{
267 return 4;
268}
269static inline u32 ram_fc_gp_get_w(void)
270{
271 return 5;
272}
273static inline u32 ram_fc_pb_get_w(void)
274{
275 return 6;
276}
277static inline u32 ram_fc_pb_get_hi_w(void)
278{
279 return 7;
280}
281static inline u32 ram_fc_pb_top_level_get_w(void)
282{
283 return 8;
284}
285static inline u32 ram_fc_pb_top_level_get_hi_w(void)
286{
287 return 9;
288}
289static inline u32 ram_fc_acquire_w(void)
290{
291 return 12;
292}
293static inline u32 ram_fc_semaphorea_w(void)
294{
295 return 14;
296}
297static inline u32 ram_fc_semaphoreb_w(void)
298{
299 return 15;
300}
301static inline u32 ram_fc_semaphorec_w(void)
302{
303 return 16;
304}
305static inline u32 ram_fc_semaphored_w(void)
306{
307 return 17;
308}
309static inline u32 ram_fc_gp_base_w(void)
310{
311 return 18;
312}
313static inline u32 ram_fc_gp_base_hi_w(void)
314{
315 return 19;
316}
317static inline u32 ram_fc_gp_fetch_w(void)
318{
319 return 20;
320}
321static inline u32 ram_fc_pb_fetch_w(void)
322{
323 return 21;
324}
325static inline u32 ram_fc_pb_fetch_hi_w(void)
326{
327 return 22;
328}
329static inline u32 ram_fc_pb_put_w(void)
330{
331 return 23;
332}
333static inline u32 ram_fc_pb_put_hi_w(void)
334{
335 return 24;
336}
337static inline u32 ram_fc_pb_header_w(void)
338{
339 return 33;
340}
341static inline u32 ram_fc_pb_count_w(void)
342{
343 return 34;
344}
345static inline u32 ram_fc_subdevice_w(void)
346{
347 return 37;
348}
349static inline u32 ram_fc_formats_w(void)
350{
351 return 39;
352}
353static inline u32 ram_fc_target_w(void)
354{
355 return 43;
356}
357static inline u32 ram_fc_hce_ctrl_w(void)
358{
359 return 57;
360}
361static inline u32 ram_fc_chid_w(void)
362{
363 return 58;
364}
365static inline u32 ram_fc_chid_id_f(u32 v)
366{
367 return (v & 0xfff) << 0;
368}
369static inline u32 ram_fc_chid_id_w(void)
370{
371 return 0;
372}
373static inline u32 ram_fc_runlist_timeslice_w(void)
374{
375 return 62;
376}
377static inline u32 ram_userd_base_shift_v(void)
378{
379 return 0x00000009;
380}
381static inline u32 ram_userd_chan_size_v(void)
382{
383 return 0x00000200;
384}
385static inline u32 ram_userd_put_w(void)
386{
387 return 16;
388}
389static inline u32 ram_userd_get_w(void)
390{
391 return 17;
392}
393static inline u32 ram_userd_ref_w(void)
394{
395 return 18;
396}
397static inline u32 ram_userd_put_hi_w(void)
398{
399 return 19;
400}
401static inline u32 ram_userd_ref_threshold_w(void)
402{
403 return 20;
404}
405static inline u32 ram_userd_top_level_get_w(void)
406{
407 return 22;
408}
409static inline u32 ram_userd_top_level_get_hi_w(void)
410{
411 return 23;
412}
413static inline u32 ram_userd_get_hi_w(void)
414{
415 return 24;
416}
417static inline u32 ram_userd_gp_get_w(void)
418{
419 return 34;
420}
421static inline u32 ram_userd_gp_put_w(void)
422{
423 return 35;
424}
425static inline u32 ram_userd_gp_top_level_get_w(void)
426{
427 return 22;
428}
429static inline u32 ram_userd_gp_top_level_get_hi_w(void)
430{
431 return 23;
432}
433static inline u32 ram_rl_entry_size_v(void)
434{
435 return 0x00000008;
436}
437static inline u32 ram_rl_entry_chid_f(u32 v)
438{
439 return (v & 0xfff) << 0;
440}
441static inline u32 ram_rl_entry_id_f(u32 v)
442{
443 return (v & 0xfff) << 0;
444}
445static inline u32 ram_rl_entry_type_f(u32 v)
446{
447 return (v & 0x1) << 13;
448}
449static inline u32 ram_rl_entry_type_chid_f(void)
450{
451 return 0x0;
452}
453static inline u32 ram_rl_entry_type_tsg_f(void)
454{
455 return 0x2000;
456}
457static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
458{
459 return (v & 0xf) << 14;
460}
461static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
462{
463 return 0xc000;
464}
465static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
466{
467 return (v & 0xff) << 18;
468}
469static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
470{
471 return 0x2000000;
472}
473static inline u32 ram_rl_entry_tsg_length_f(u32 v)
474{
475 return (v & 0x3f) << 26;
476}
477#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h b/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h
new file mode 100644
index 00000000..62771628
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_timer_gp106_h_
51#define _hw_timer_gp106_h_
52
53static inline u32 timer_pri_timeout_r(void)
54{
55 return 0x00009080;
56}
57static inline u32 timer_pri_timeout_period_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 timer_pri_timeout_period_m(void)
62{
63 return 0xffffff << 0;
64}
65static inline u32 timer_pri_timeout_period_v(u32 r)
66{
67 return (r >> 0) & 0xffffff;
68}
69static inline u32 timer_pri_timeout_en_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 timer_pri_timeout_en_m(void)
74{
75 return 0x1 << 31;
76}
77static inline u32 timer_pri_timeout_en_v(u32 r)
78{
79 return (r >> 31) & 0x1;
80}
81static inline u32 timer_pri_timeout_en_en_enabled_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 timer_pri_timeout_en_en_disabled_f(void)
86{
87 return 0x0;
88}
89static inline u32 timer_pri_timeout_save_0_r(void)
90{
91 return 0x00009084;
92}
93static inline u32 timer_pri_timeout_save_1_r(void)
94{
95 return 0x00009088;
96}
97static inline u32 timer_pri_timeout_fecs_errcode_r(void)
98{
99 return 0x0000908c;
100}
101static inline u32 timer_time_0_r(void)
102{
103 return 0x00009400;
104}
105static inline u32 timer_time_1_r(void)
106{
107 return 0x00009410;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
new file mode 100644
index 00000000..ed8e0888
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
@@ -0,0 +1,169 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_top_gp106_h_
51#define _hw_top_gp106_h_
52
53static inline u32 top_num_gpcs_r(void)
54{
55 return 0x00022430;
56}
57static inline u32 top_num_gpcs_value_v(u32 r)
58{
59 return (r >> 0) & 0x1f;
60}
61static inline u32 top_tpc_per_gpc_r(void)
62{
63 return 0x00022434;
64}
65static inline u32 top_tpc_per_gpc_value_v(u32 r)
66{
67 return (r >> 0) & 0x1f;
68}
69static inline u32 top_num_fbps_r(void)
70{
71 return 0x00022438;
72}
73static inline u32 top_num_fbps_value_v(u32 r)
74{
75 return (r >> 0) & 0x1f;
76}
77static inline u32 top_ltc_per_fbp_r(void)
78{
79 return 0x00022450;
80}
81static inline u32 top_ltc_per_fbp_value_v(u32 r)
82{
83 return (r >> 0) & 0x1f;
84}
85static inline u32 top_slices_per_ltc_r(void)
86{
87 return 0x0002245c;
88}
89static inline u32 top_slices_per_ltc_value_v(u32 r)
90{
91 return (r >> 0) & 0x1f;
92}
93static inline u32 top_num_ltcs_r(void)
94{
95 return 0x00022454;
96}
97static inline u32 top_device_info_r(u32 i)
98{
99 return 0x00022700 + i*4;
100}
101static inline u32 top_device_info__size_1_v(void)
102{
103 return 0x00000040;
104}
105static inline u32 top_device_info_chain_v(u32 r)
106{
107 return (r >> 31) & 0x1;
108}
109static inline u32 top_device_info_chain_enable_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 top_device_info_engine_enum_v(u32 r)
114{
115 return (r >> 26) & 0xf;
116}
117static inline u32 top_device_info_runlist_enum_v(u32 r)
118{
119 return (r >> 21) & 0xf;
120}
121static inline u32 top_device_info_intr_enum_v(u32 r)
122{
123 return (r >> 15) & 0x1f;
124}
125static inline u32 top_device_info_reset_enum_v(u32 r)
126{
127 return (r >> 9) & 0x1f;
128}
129static inline u32 top_device_info_type_enum_v(u32 r)
130{
131 return (r >> 2) & 0x1fffffff;
132}
133static inline u32 top_device_info_type_enum_graphics_v(void)
134{
135 return 0x00000000;
136}
137static inline u32 top_device_info_type_enum_graphics_f(void)
138{
139 return 0x0;
140}
141static inline u32 top_device_info_type_enum_copy0_v(void)
142{
143 return 0x00000001;
144}
145static inline u32 top_device_info_type_enum_copy0_f(void)
146{
147 return 0x4;
148}
149static inline u32 top_device_info_entry_v(u32 r)
150{
151 return (r >> 0) & 0x3;
152}
153static inline u32 top_device_info_entry_not_valid_v(void)
154{
155 return 0x00000000;
156}
157static inline u32 top_device_info_entry_enum_v(void)
158{
159 return 0x00000002;
160}
161static inline u32 top_scratch1_r(void)
162{
163 return 0x0002240c;
164}
165static inline u32 top_scratch1_devinit_completed_v(u32 r)
166{
167 return (r >> 1) & 0x1;
168}
169#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h
new file mode 100644
index 00000000..74b6cf7c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_xve_gp106_h_
51#define _hw_xve_gp106_h_
52
53static inline u32 xve_rom_ctrl_r(void)
54{
55 return 0x00000050;
56}
57static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
58{
59 return (v & 0x1) << 0;
60}
61static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
62{
63 return 0x0;
64}
65static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
66{
67 return 0x1;
68}
69#endif
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
new file mode 100644
index 00000000..a9d05730
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h> /* for udelay */
15#include "gk20a/gk20a.h"
16#include "gk20a/pmu_gk20a.h"
17
18#include "gp10b/pmu_gp10b.h"
19#include "hw_mc_gp106.h"
20#include "hw_pwr_gp106.h"
21
22int gp106_pmu_reset(struct gk20a *g)
23{
24 gk20a_dbg_fn("");
25
26 gk20a_reset(g, mc_enable_pwr_enabled_f());
27
28 gk20a_writel(g, pwr_falcon_engine_r(),
29 pwr_falcon_engine_reset_true_f());
30 udelay(10);
31 gk20a_writel(g, pwr_falcon_engine_r(),
32 pwr_falcon_engine_reset_false_f());
33
34 gk20a_dbg_fn("done");
35 return 0;
36}
37
38void gp106_init_pmu_ops(struct gpu_ops *gops)
39{
40 gk20a_dbg_fn("");
41
42 gp10b_init_pmu_ops(gops);
43 gops->pmu.reset = gp106_pmu_reset;
44
45 gk20a_dbg_fn("done");
46}
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
new file mode 100644
index 00000000..8fb4c736
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __PMU_GP106_H_
15#define __PMU_GP106_H_
16
17void gp106_init_pmu_ops(struct gpu_ops *gops);
18
19#endif /*__PMU_GP106_H_*/
diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h
index 96f02125..84da4b96 100644
--- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h
+++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * NVIDIA GPU ID functions, definitions. 2 * NVIDIA GPU ID functions, definitions.
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -17,6 +17,10 @@
17 17
18#define NVGPU_GPUID_GP10B \ 18#define NVGPU_GPUID_GP10B \
19 GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP10B) 19 GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP10B)
20#define NVGPU_GPUID_GP104 \
21 GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP104)
22#define NVGPU_GPUID_GP106 \
23 GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP106)
20 24
21#define NVGPU_COMPAT_TEGRA_GP10B "nvidia,tegra186-gp10b" 25#define NVGPU_COMPAT_TEGRA_GP10B "nvidia,tegra186-gp10b"
22#define NVGPU_COMPAT_GENERIC_GP10B "nvidia,generic-gp10b" 26#define NVGPU_COMPAT_GENERIC_GP10B "nvidia,generic-gp10b"
@@ -25,8 +29,13 @@
25#define TEGRA_18x_GPUID_HAL gp10b_init_hal 29#define TEGRA_18x_GPUID_HAL gp10b_init_hal
26#define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B 30#define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B
27#define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B 31#define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B
32#define TEGRA_18x_GPUID2 NVGPU_GPUID_GP104
33#define TEGRA_18x_GPUID2_HAL gp106_init_hal
34#define TEGRA_18x_GPUID3 NVGPU_GPUID_GP106
35#define TEGRA_18x_GPUID3_HAL gp106_init_hal
28struct gpu_ops; 36struct gpu_ops;
29extern int gp10b_init_hal(struct gk20a *); 37extern int gp10b_init_hal(struct gk20a *);
38extern int gp106_init_hal(struct gk20a *);
30extern struct gk20a_platform t18x_gpu_tegra_platform; 39extern struct gk20a_platform t18x_gpu_tegra_platform;
31 40
32#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 41#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h
index 1dce0c21..24c38f80 100644
--- a/include/uapi/linux/nvgpu-t18x.h
+++ b/include/uapi/linux/nvgpu-t18x.h
@@ -25,6 +25,8 @@
25#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ 25#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
26 26
27#define NVGPU_GPU_ARCH_GP100 0x00000130 27#define NVGPU_GPU_ARCH_GP100 0x00000130
28#define NVGPU_GPU_IMPL_GP104 0x00000004
29#define NVGPU_GPU_IMPL_GP106 0x00000006
28#define NVGPU_GPU_IMPL_GP10B 0x0000000B 30#define NVGPU_GPU_IMPL_GP10B 0x0000000B
29 31
30/* 32/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:07:14 -0400