gpu: nvgpu: gv11b: Reorg ce2 HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ce2
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509633
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
index 9716c6d6..8bf636b1 100644
--- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
@@ -28,7 +28,7 @@
 #include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 
-static u32 gv11b_ce_get_num_pce(struct gk20a *g)
+u32 gv11b_ce_get_num_pce(struct gk20a *g)
 {
         /* register contains a bitmask indicating which physical copy
          * engines are present (and not floorswept).
@@ -41,7 +41,7 @@ static u32 gv11b_ce_get_num_pce(struct gk20a *g)
         return num_pce;
 }
 
-static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 {
         u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
         u32 clear_intr = 0;
@@ -102,10 +102,3 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g)
                 }
         }
 }
-
-void gv11b_init_ce(struct gpu_ops *gops)
-{
-        gp10b_init_ce(gops);
-        gops->ce2.isr_stall = gv11b_ce_isr;
-        gops->ce2.get_num_pce = gv11b_ce_get_num_pce;
-}
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h
index 23053199..ce60ad3e 100644
--- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h
@@ -19,10 +19,11 @@
 #ifndef __CE_GV11B_H__
 #define __CE_GV11B_H__
 
-struct gpu_ops;
+struct gk20a;
 
-void gv11b_init_ce(struct gpu_ops *gops);
 void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g);
 u32 gv11b_ce_get_num_lce(struct gk20a *g);
+u32 gv11b_ce_get_num_pce(struct gk20a *g);
+void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 
 #endif /*__CE2_GV11B_H__*/
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 3ebeb205..e585e9b1 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -34,6 +34,7 @@
 
 #include "gp10b/ltc_gp10b.h"
 #include "gp10b/mc_gp10b.h"
+#include "gp10b/ce_gp10b.h"
 #include "gp10b/priv_ring_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 
@@ -160,6 +161,11 @@ static const struct gpu_ops gv11b_ops = {
                 .sync_debugfs = gp10b_ltc_sync_debugfs,
 #endif
         },
+        .ce2 = {
+                .isr_stall = gv11b_ce_isr,
+                .isr_nonstall = gp10b_ce_nonstall_isr,
+                .get_num_pce = gv11b_ce_get_num_pce,
+        },
         .clock_gating = {
                 .slcg_bus_load_gating_prod =
                         gv11b_slcg_bus_load_gating_prod,
@@ -340,6 +346,7 @@ int gv11b_init_hal(struct gk20a *g)
         struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
 
         gops->ltc = gv11b_ops.ltc;
+        gops->ce2 = gv11b_ops.ce2;
         gops->clock_gating = gv11b_ops.clock_gating;
         gops->fifo = gv11b_ops.fifo;
         gops->mc = gv11b_ops.mc;
@@ -364,7 +371,6 @@ int gv11b_init_hal(struct gk20a *g)
         gv11b_init_gr(g);
         gv11b_init_fecs_trace_ops(gops);
         gv11b_init_fb(gops);
-        gv11b_init_ce(gops);
         gv11b_init_gr_ctx(gops);
         gv11b_init_mm(gops);
         gv11b_init_pmu_ops(g);