gpu: nvgpu: gv11b: move cbc init to mmu from ltc

Added cbc_init in fb and removed cbc_init from ltc.

Also avoid writing into read only registers in ltc.

GPUT19X-70
GPUT19X-116

Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1484525
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>

3 files changed, 149 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 9a4ea36b..3b3d775e 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -28,6 +28,7 @@
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 
 #include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
 
 static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
 {
@@ -62,6 +63,71 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
 
 }
 
+static void gv11b_fb_init_fs_state(struct gk20a *g)
+{
+        nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb");
+
+        nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %u",
+                        gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
+
+        gk20a_writel(g, fb_mmu_num_active_ltcs_r(),
+                        fb_mmu_num_active_ltcs_count_f(g->ltc_count));
+
+        nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u",
+                        fb_mmu_num_active_ltcs_count_v(
+                        gk20a_readl(g, fb_mmu_num_active_ltcs_r())));
+}
+
+static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
+{
+        u32 max_size = gr->max_comptag_mem;
+        /* one tag line covers 64KB */
+        u32 max_comptag_lines = max_size << 4;
+        u32 compbit_base_post_divide;
+        u64 compbit_base_post_multiply64;
+        u64 compbit_store_iova;
+        u64 compbit_base_post_divide64;
+
+        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
+                compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
+        else
+                compbit_store_iova = g->ops.mm.get_iova_addr(g,
+                                gr->compbit_store.mem.priv.sgt->sgl, 0);
+
+        compbit_base_post_divide64 = compbit_store_iova >>
+                fb_mmu_cbc_base_address_alignment_shift_v();
+
+        do_div(compbit_base_post_divide64, g->ltc_count);
+        compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
+
+        compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
+                g->ltc_count) << fb_mmu_cbc_base_address_alignment_shift_v();
+
+        if (compbit_base_post_multiply64 < compbit_store_iova)
+                compbit_base_post_divide++;
+
+        if (g->ops.ltc.cbc_fix_config)
+                compbit_base_post_divide =
+                        g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide);
+
+        gk20a_writel(g, fb_mmu_cbc_base_r(),
+                fb_mmu_cbc_base_address_f(compbit_base_post_divide));
+
+        nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
+                "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
+                (u32)(compbit_store_iova >> 32),
+                (u32)(compbit_store_iova & 0xffffffff),
+                compbit_base_post_divide);
+        nvgpu_log(g, gpu_dbg_fn, "cbc base %x",
+                gk20a_readl(g, fb_mmu_cbc_base_r()));
+
+        gr->compbit_store.base_hw = compbit_base_post_divide;
+
+        g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
+                        0, max_comptag_lines - 1);
+
+}
+
 static void gv11b_fb_reset(struct gk20a *g)
 {
         u32 val;
@@ -450,6 +516,8 @@ void gv11b_init_fb(struct gpu_ops *gops)
         gp10b_init_fb(gops);
         gops->fb.hub_isr = gv11b_fb_hub_isr;
         gops->fb.reset = gv11b_fb_reset;
+        gops->fb.init_fs_state = gv11b_fb_init_fs_state;
+        gops->fb.init_cbc = gv11b_fb_init_cbc;
 
         gv11b_init_uncompressed_kind_map();
         gv11b_init_kind_attr();
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
index b8a97ce3..5b98b0aa 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
@@ -53,10 +53,6 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g)
         g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r());
         gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count);
 
-        reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r());
-        reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true);
-        gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg);
-
         gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(),
                 gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) |
                 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m());
@@ -200,4 +196,5 @@ void gv11b_init_ltc(struct gpu_ops *gops)
         gops->ltc.init_fs_state = gv11b_ltc_init_fs_state;
         gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config;
         gops->ltc.isr = gv11b_ltc_isr;
+        gops->ltc.init_cbc = NULL;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index 0ddccd45..e261ef14 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -1814,4 +1814,84 @@ static inline u32 fb_mmu_fault_status_valid_clear_f(void)
 {
         return 0x80000000;
 }
+static inline u32 fb_mmu_num_active_ltcs_r(void)
+{
+        return 0x00100ec0;
+}
+static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 fb_mmu_cbc_base_r(void)
+{
+        return 0x00100ec4;
+}
+static inline u32 fb_mmu_cbc_base_address_f(u32 v)
+{
+        return (v & 0x3ffffff) << 0;
+}
+static inline u32 fb_mmu_cbc_base_address_v(u32 r)
+{
+        return (r >> 0) & 0x3ffffff;
+}
+static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 fb_mmu_cbc_top_r(void)
+{
+        return 0x00100ec8;
+}
+static inline u32 fb_mmu_cbc_top_size_f(u32 v)
+{
+        return (v & 0x7fff) << 0;
+}
+static inline u32 fb_mmu_cbc_top_size_v(u32 r)
+{
+        return (r >> 0) & 0x7fff;
+}
+static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 fb_mmu_cbc_max_r(void)
+{
+        return 0x00100ecc;
+}
+static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v)
+{
+        return (v & 0xffffff) << 0;
+}
+static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r)
+{
+        return (r >> 0) & 0xffffff;
+}
+static inline u32 fb_mmu_cbc_max_safe_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 fb_mmu_cbc_max_safe_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_mmu_cbc_max_safe_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void)
+{
+        return 0x00000001;
+}
 #endif