diff options
author | Alex Frid <afrid@nvidia.com> | 2014-09-12 00:05:29 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:18 -0400 |
commit | 375ab4bea0f4fc5d202eed651e0d74bd786152ef (patch) | |
tree | 81dcb2fff00e8436a30d805e5d8a21da30ea0586 | |
parent | d70948ebe804395ff6e75f5aba0fa29d2bfefbf6 (diff) |
gpu: nvgpu: Add GM20B GPCPLL h/w definitions
Expanded GM20B GPCPLL definitions of DVFS registers.
Bug 1450787
Change-Id: I51d049be70badfedd8c451019b10770b4fb31e80
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499487
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h index bab9242c..e923e451 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h | |||
@@ -318,6 +318,10 @@ static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) | |||
318 | { | 318 | { |
319 | return 0xff << 16; | 319 | return 0xff << 16; |
320 | } | 320 | } |
321 | static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r) | ||
322 | { | ||
323 | return (r >> 24) & 0x7f; | ||
324 | } | ||
321 | static inline u32 trim_sys_gpcpll_dvfs0_r(void) | 325 | static inline u32 trim_sys_gpcpll_dvfs0_r(void) |
322 | { | 326 | { |
323 | return 0x00137010; | 327 | return 0x00137010; |
@@ -470,6 +474,10 @@ static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_syn | |||
470 | { | 474 | { |
471 | return (r >> 24) & 0x1; | 475 | return (r >> 24) & 0x1; |
472 | } | 476 | } |
477 | static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void) | ||
478 | { | ||
479 | return 0x00132820; | ||
480 | } | ||
473 | static inline u32 trim_sys_bypassctrl_r(void) | 481 | static inline u32 trim_sys_bypassctrl_r(void) |
474 | { | 482 | { |
475 | return 0x00137340; | 483 | return 0x00137340; |