gpu: nvgpu: dump falcon stats for fecs watchdog

After fecs watchdog gets triggered, system will not
do anything useful as it cannot context switch. Dumping
falcon stats will help debug the issue since s/w is
not triggering recovery.

Bug 2113657

Change-Id: I03ccd5ad7c03daac0581775dc615174cc0e77328
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 24 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index b94eade1..a9a87a54 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5288,10 +5288,16 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                           gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)),
                           isr_data->data_lo);
                 ret = -1;
+        } else if ((gr_fecs_intr &
+                        gr_fecs_host_int_status_watchdog_active_f()) != 0U) {
+                /* currently, recovery is not initiated */
+                nvgpu_err(g, "fecs watchdog triggered for channel %u, "
+                                "cannot ctxsw anymore !!", isr_data->chid);
+                gk20a_fecs_dump_falcon_stats(g);
         } else {
                 nvgpu_err(g,
-                   "fecs error interrupt 0x%08x for channel %u",
-                   gr_fecs_intr, isr_data->chid);
+                        "fecs error interrupt 0x%08x for channel %u",
+                        gr_fecs_intr, isr_data->chid);
         }
 
         gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 8655a0d3..826108f1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -996,6 +996,10 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
         return (v & 0x1U) << 18U;
 }
+static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
+{
+        return 0x80000U;
+}
 static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
 {
         return (v & 0xffffU) << 0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index be05d031..5bbb3b9f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -1012,6 +1012,10 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
         return (v & 0x1U) << 18U;
 }
+static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
+{
+        return 0x80000U;
+}
 static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
 {
         return (v & 0xffffU) << 0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index efd8b555..f7bc4c23 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1200,6 +1200,10 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
         return (v & 0x1U) << 18U;
 }
+static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
+{
+        return 0x80000U;
+}
 static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
 {
         return (v & 0xffffU) << 0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 588452cd..36a7ebf5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -2032,6 +2032,10 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
         return (v & 0x1U) << 18U;
 }
+static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
+{
+        return 0x80000U;
+}
 static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
 {
         return (v & 0xffffU) << 0U;