gpu: nvgpu: gv11b: Correct PMU PG enabled masks.

PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.

It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.

Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.

Bug 200392620.
Bug 200296076.

Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

8 files changed, 41 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/debug_pmu.c b/drivers/gpu/nvgpu/common/linux/debug_pmu.c
index a8a8870e..f4ed992d 100644
--- a/drivers/gpu/nvgpu/common/linux/debug_pmu.c
+++ b/drivers/gpu/nvgpu/common/linux/debug_pmu.c
@@ -27,7 +27,7 @@ static int lpwr_debug_show(struct seq_file *s, void *data)
         if (g->ops.pmu.pmu_pg_engines_feature_list &&
                 g->ops.pmu.pmu_pg_engines_feature_list(g,
                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                 seq_printf(s, "PSTATE: %u\n"
                         "RPPG Enabled: %u\n"
                         "RPPG ref count: %u\n"
diff --git a/drivers/gpu/nvgpu/common/linux/sysfs.c b/drivers/gpu/nvgpu/common/linux/sysfs.c
index 86f1877d..afa08fc4 100644
--- a/drivers/gpu/nvgpu/common/linux/sysfs.c
+++ b/drivers/gpu/nvgpu/common/linux/sysfs.c
@@ -477,7 +477,7 @@ static ssize_t elpg_enable_store(struct device *dev,
                         if (g->ops.pmu.pmu_pg_engines_feature_list &&
                                 g->ops.pmu.pmu_pg_engines_feature_list(g,
                                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                                 nvgpu_pmu_pg_global_enable(g, false);
                                 g->elpg_enabled = false;
                         } else {
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index bf39ce19..2d0fc499 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -89,7 +89,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
                         if (g->ops.pmu.pmu_pg_engines_feature_list &&
                                 g->ops.pmu.pmu_pg_engines_feature_list(g,
                                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                                 pmu->initialized = true;
                                 nvgpu_pmu_state_change(g, PMU_STATE_STARTED,
                                         true);
@@ -116,7 +116,7 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
                 if (g->ops.pmu.pmu_pg_engines_feature_list &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
                         PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                        PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                        NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_enable_pg)
                                 status = g->ops.pmu.pmu_lpwr_enable_pg(g,
                                                 true);
@@ -126,7 +126,7 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
                 if (g->ops.pmu.pmu_pg_engines_feature_list &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
                         PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                        PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                        NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_disable_pg)
                                 status = g->ops.pmu.pmu_lpwr_disable_pg(g,
                                                 true);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 603d25fe..0531b387 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -545,7 +545,7 @@ u32 gk20a_pmu_pg_engines_list(struct gk20a *g)
 u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id)
 {
         if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS)
-                return PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
+                return NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING;
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index de26ecf2..d4041905 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -81,7 +81,7 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
 u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id)
 {
         if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS)
-                return PMU_PG_FEATURE_GR_RPPG_ENABLED;
+                return NVGPU_PMU_GR_FEATURE_MASK_RPPG;
 
         if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS)
                 return NVGPU_PMU_MS_FEATURE_MASK_ALL;
@@ -133,7 +133,7 @@ int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
                 cmd.cmd.pg.gr_init_param.sub_cmd_id =
                                 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
                 cmd.cmd.pg.gr_init_param.featuremask =
-                                PMU_PG_FEATURE_GR_RPPG_ENABLED;
+                                NVGPU_PMU_GR_FEATURE_MASK_RPPG;
 
                 gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
                 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index d368bad7..49ad3920 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -239,7 +239,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
                 cmd.cmd.pg.gr_init_param.sub_cmd_id =
                                 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
                 cmd.cmd.pg.gr_init_param.featuremask =
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
+                                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING;
 
                 gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM ");
                 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index 7dd4f8f4..32e751d9 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -446,7 +446,7 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
                 cmd.cmd.pg.gr_init_param_v1.sub_cmd_id =
                                 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
                 cmd.cmd.pg.gr_init_param_v1.featuremask =
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
+                                NVGPU_PMU_GR_FEATURE_MASK_ALL;
 
                 gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n");
                 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
@@ -476,7 +476,15 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
                 cmd.cmd.pg.sf_mask_update.ctrl_id =
                                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS;
                 cmd.cmd.pg.sf_mask_update.enabled_mask =
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
+                                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |
+                                NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |
+                                NVGPU_PMU_GR_FEATURE_MASK_UNBIND |
+                                NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |
+                                NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |
+                                NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |
+                                NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |
+                                NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |
+                                NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG;
 
                 gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n");
                 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
index b1077821..91656156 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -128,14 +128,31 @@ enum {
 #define PMU_PG_PARAM_CMD_POST_INIT  0x06
 #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE  0x07
 
-#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
-#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED  (1 << 2)
-#define PMU_PG_FEATURE_GR_RPPG_ENABLED          (1 << 3)
+#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     (1 << 0)
+#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      (1 << 2)
+#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              (1 << 3)
+#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         (1 << 5)
+#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            (1 << 6)
+#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7)
+#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       (1 << 8)
+#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       (1 << 9)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         (1 << 10)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        (1 << 11)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       (1 << 12)
 
-#define NVGPU_PMU_GR_FEATURE_MASK_RPPG  (1 << 3)
 #define NVGPU_PMU_GR_FEATURE_MASK_ALL   \
         (       \
-                NVGPU_PMU_GR_FEATURE_MASK_RPPG   \
+                NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN         |\
+                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING          |\
+                NVGPU_PMU_GR_FEATURE_MASK_RPPG                  |\
+                NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING             |\
+                NVGPU_PMU_GR_FEATURE_MASK_UNBIND                |\
+                NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE     |\
+                NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY           |\
+                NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE           |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM             |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC            |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG           \
         )
 
 #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  (1 << 0)