gpu: nvgpu: gv11b: PMU parity HWW ECC support

Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path

JIRA: GPUT19X-83

Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

13 files changed, 397 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
index 3c6eac77..a2a60aaa 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
@@ -243,6 +243,9 @@ static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_ar
 static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array;
 static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array;
 
+static struct device_attribute *dev_attr_pmu_ecc_corrected_err_count_array;
+static struct device_attribute *dev_attr_pmu_ecc_uncorrected_err_count_array;
+
 void gr_gv11b_create_sysfs(struct gk20a *g)
 {
         struct device *dev = dev_from_gk20a(g);
@@ -414,6 +417,21 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
                                 &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
                                 &dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
 
+        error |= gp10b_ecc_stat_create(dev,
+                                1,
+                                "eng",
+                                "pmu_ecc_uncorrected_err_count",
+                                &g->ecc.eng.t19x.pmu_uncorrected_err_count,
+                                &dev_attr_pmu_ecc_uncorrected_err_count_array);
+
+        error |= gp10b_ecc_stat_create(dev,
+                                1,
+                                "eng",
+                                "pmu_ecc_corrected_err_count",
+                                &g->ecc.eng.t19x.pmu_corrected_err_count,
+                                &dev_attr_pmu_ecc_corrected_err_count_array);
+
+
         if (error)
                 dev_err(dev, "Failed to create gv11b sysfs attributes!\n");
 }
@@ -541,4 +559,14 @@ static void gr_gv11b_remove_sysfs(struct device *dev)
                         1,
                         &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
                         dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
+
+        gp10b_ecc_stat_remove(dev,
+                        1,
+                        &g->ecc.eng.t19x.pmu_uncorrected_err_count,
+                        dev_attr_pmu_ecc_uncorrected_err_count_array);
+
+        gp10b_ecc_stat_remove(dev,
+                        1,
+                        &g->ecc.eng.t19x.pmu_corrected_err_count,
+                        dev_attr_pmu_ecc_corrected_err_count_array);
 }
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f577f93c..2ae1b758 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -888,6 +888,7 @@ struct gpu_ops {
                 void (*set_irqmask)(struct gk20a *g);
                 void (*update_lspmu_cmdline_args)(struct gk20a *g);
                 void (*setup_apertures)(struct gk20a *g);
+                u32 (*get_irqdest)(struct gk20a *g);
         } pmu;
         struct {
                 int (*init_debugfs)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index f9f85219..9c2f72fb 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -110,6 +110,33 @@ static void print_pmu_trace(struct nvgpu_pmu *pmu)
         nvgpu_kfree(g, tracebuffer);
 }
 
+u32 gk20a_pmu_get_irqdest(struct gk20a *g)
+{
+        u32 intr_dest;
+
+        /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
+        intr_dest = pwr_falcon_irqdest_host_gptmr_f(0)    |
+                pwr_falcon_irqdest_host_wdtmr_f(1)    |
+                pwr_falcon_irqdest_host_mthd_f(0)     |
+                pwr_falcon_irqdest_host_ctxsw_f(0)    |
+                pwr_falcon_irqdest_host_halt_f(1)     |
+                pwr_falcon_irqdest_host_exterr_f(0)   |
+                pwr_falcon_irqdest_host_swgen0_f(1)   |
+                pwr_falcon_irqdest_host_swgen1_f(0)   |
+                pwr_falcon_irqdest_host_ext_f(0xff)   |
+                pwr_falcon_irqdest_target_gptmr_f(1)  |
+                pwr_falcon_irqdest_target_wdtmr_f(0)  |
+                pwr_falcon_irqdest_target_mthd_f(0)   |
+                pwr_falcon_irqdest_target_ctxsw_f(0)  |
+                pwr_falcon_irqdest_target_halt_f(0)   |
+                pwr_falcon_irqdest_target_exterr_f(0) |
+                pwr_falcon_irqdest_target_swgen0_f(0) |
+                pwr_falcon_irqdest_target_swgen1_f(0) |
+                pwr_falcon_irqdest_target_ext_f(0xff);
+
+        return intr_dest;
+}
+
 void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
@@ -126,26 +153,7 @@ void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
         nvgpu_flcn_set_irq(pmu->flcn, false, 0x0, 0x0);
 
         if (enable) {
-                /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
-                intr_dest = pwr_falcon_irqdest_host_gptmr_f(0)    |
-                        pwr_falcon_irqdest_host_wdtmr_f(1)    |
-                        pwr_falcon_irqdest_host_mthd_f(0)     |
-                        pwr_falcon_irqdest_host_ctxsw_f(0)    |
-                        pwr_falcon_irqdest_host_halt_f(1)     |
-                        pwr_falcon_irqdest_host_exterr_f(0)   |
-                        pwr_falcon_irqdest_host_swgen0_f(1)   |
-                        pwr_falcon_irqdest_host_swgen1_f(0)   |
-                        pwr_falcon_irqdest_host_ext_f(0xff)   |
-                        pwr_falcon_irqdest_target_gptmr_f(1)  |
-                        pwr_falcon_irqdest_target_wdtmr_f(0)  |
-                        pwr_falcon_irqdest_target_mthd_f(0)   |
-                        pwr_falcon_irqdest_target_ctxsw_f(0)  |
-                        pwr_falcon_irqdest_target_halt_f(0)   |
-                        pwr_falcon_irqdest_target_exterr_f(0) |
-                        pwr_falcon_irqdest_target_swgen0_f(0) |
-                        pwr_falcon_irqdest_target_swgen1_f(0) |
-                        pwr_falcon_irqdest_target_ext_f(0xff);
-
+                intr_dest = g->ops.pmu.get_irqdest(g);
                 /* 0=disable, 1=enable */
                 intr_mask = pwr_falcon_irqmset_gptmr_f(1)  |
                         pwr_falcon_irqmset_wdtmr_f(1)  |
@@ -729,6 +737,10 @@ void gk20a_pmu_isr(struct gk20a *g)
                         gk20a_readl(g, pwr_falcon_exterrstat_r()) &
                                 ~pwr_falcon_exterrstat_valid_m());
         }
+
+        if (g->ops.pmu.handle_ext_irq)
+                g->ops.pmu.handle_ext_irq(g, intr);
+
         if (intr & pwr_falcon_irqstat_swgen0_true_f()) {
                 nvgpu_pmu_process_message(pmu);
                 recheck = true;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index f1d9498c..5bd43510 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -76,5 +76,5 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
 int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
-
+u32 gk20a_pmu_get_irqdest(struct gk20a *g);
 #endif /*__PMU_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 3ef11d11..d89ff2fe 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -495,6 +495,7 @@ static const struct gpu_ops gm20b_ops = {
                 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
                 .reset_engine = gk20a_pmu_engine_reset,
                 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
+                .get_irqdest = gk20a_pmu_get_irqdest,
         },
         .clk = {
                 .init_clk_support = gm20b_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index a3a58903..2150b1ec 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -598,6 +598,7 @@ static const struct gpu_ops gp106_ops = {
                 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
                 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
                 .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg,
+                .get_irqdest = gk20a_pmu_get_irqdest,
         },
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 0186ba00..06311347 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -547,6 +547,7 @@ static const struct gpu_ops gp10b_ops = {
                 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
                 .reset_engine = gk20a_pmu_engine_reset,
                 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
+                .get_irqdest = gk20a_pmu_get_irqdest,
         },
         .regops = {
                 .get_global_whitelist_ranges =
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 36ac029b..648a3b39 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -603,6 +603,7 @@ static const struct gpu_ops gv100_ops = {
                 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
                 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
                 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
+                .get_irqdest = gk20a_pmu_get_irqdest,
         },
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
index 94b25c02..ebce46ce 100644
--- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
@@ -59,6 +59,8 @@ struct ecc_eng_t19x {
         struct gk20a_ecc_stat mmu_fillunit_corrected_err_count;
         struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count;
         /* PMU */
+        struct gk20a_ecc_stat pmu_corrected_err_count;
+        struct gk20a_ecc_stat pmu_uncorrected_err_count;
 };
 
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 6a21eb2d..f6bdf6e5 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -611,6 +611,8 @@ static const struct gpu_ops gv11b_ops = {
                 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
                 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
                 .is_pmu_supported = gv11b_is_pmu_supported,
+                .get_irqdest = gv11b_pmu_get_irqdest,
+                .handle_ext_irq = gv11b_pmu_handle_ext_irq,
         },
         .regops = {
                 .get_global_whitelist_ranges =
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index 4b244f5a..a972510f 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -287,6 +287,123 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
         return 0;
 }
 
+void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0)
+{
+        u32 intr1;
+        u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt;
+        u32 corrected_delta, uncorrected_delta;
+        u32 corrected_overflow, uncorrected_overflow;
+
+        /*
+         * handle the ECC interrupt
+         */
+        if (intr0 & pwr_falcon_irqstat_ext_ecc_parity_true_f()) {
+                intr1 = gk20a_readl(g, pwr_pmu_ecc_intr_status_r());
+                if (intr1 & (pwr_pmu_ecc_intr_status_corrected_m() |
+                             pwr_pmu_ecc_intr_status_uncorrected_m())) {
+
+                        ecc_status = gk20a_readl(g,
+                                pwr_pmu_falcon_ecc_status_r());
+                        ecc_addr = gk20a_readl(g,
+                                pwr_pmu_falcon_ecc_address_r());
+                        corrected_cnt = gk20a_readl(g,
+                                pwr_pmu_falcon_ecc_corrected_err_count_r());
+                        uncorrected_cnt = gk20a_readl(g,
+                                pwr_pmu_falcon_ecc_uncorrected_err_count_r());
+
+                        corrected_delta =
+                                pwr_pmu_falcon_ecc_corrected_err_count_total_v(corrected_cnt);
+                        uncorrected_delta =
+                                pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(uncorrected_cnt);
+                        corrected_overflow = ecc_status &
+                                pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m();
+
+                        uncorrected_overflow = ecc_status &
+                                pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m();
+                        corrected_overflow = ecc_status &
+                                pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m();
+
+                        /* clear the interrupt */
+                        if ((intr1 & pwr_pmu_ecc_intr_status_corrected_m()) ||
+                                                        corrected_overflow) {
+                                gk20a_writel(g, pwr_pmu_falcon_ecc_corrected_err_count_r(), 0);
+                        }
+                        if ((intr1 & pwr_pmu_ecc_intr_status_uncorrected_m()) ||
+                                                        uncorrected_overflow) {
+                                gk20a_writel(g,
+                                        pwr_pmu_falcon_ecc_uncorrected_err_count_r(), 0);
+                        }
+
+                        gk20a_writel(g, pwr_pmu_falcon_ecc_status_r(),
+                                pwr_pmu_falcon_ecc_status_reset_task_f());
+
+                        /* update counters per slice */
+                        if (corrected_overflow)
+                                corrected_delta += (0x1UL << pwr_pmu_falcon_ecc_corrected_err_count_total_s());
+                        if (uncorrected_overflow)
+                                uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s());
+
+                        g->ecc.eng.t19x.pmu_corrected_err_count.counters[0] += corrected_delta;
+                        g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0] += uncorrected_delta;
+
+                        nvgpu_log(g, gpu_dbg_intr,
+                                "pmu ecc interrupt intr1: 0x%x", intr1);
+
+                        if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_imem_m())
+                                nvgpu_log(g, gpu_dbg_intr,
+                                        "imem ecc error corrected");
+                        if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m())
+                                nvgpu_log(g, gpu_dbg_intr,
+                                        "imem ecc error uncorrected");
+                        if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_dmem_m())
+                                nvgpu_log(g, gpu_dbg_intr,
+                                        "dmem ecc error corrected");
+                        if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m())
+                                nvgpu_log(g, gpu_dbg_intr,
+                                        "dmem ecc error uncorrected");
+
+                        if (corrected_overflow || uncorrected_overflow)
+                                nvgpu_info(g, "ecc counter overflow!");
+
+                        nvgpu_log(g, gpu_dbg_intr,
+                                "ecc error row address: 0x%x",
+                                pwr_pmu_falcon_ecc_address_row_address_v(ecc_addr));
+
+                        nvgpu_log(g, gpu_dbg_intr,
+                                "ecc error count corrected: %d, uncorrected %d",
+                                g->ecc.eng.t19x.pmu_corrected_err_count.counters[0],
+                                g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0]);
+                }
+        }
+}
+
+u32 gv11b_pmu_get_irqdest(struct gk20a *g)
+{
+        u32 intr_dest;
+
+        /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
+        intr_dest = pwr_falcon_irqdest_host_gptmr_f(0)      |
+                pwr_falcon_irqdest_host_wdtmr_f(1)          |
+                pwr_falcon_irqdest_host_mthd_f(0)           |
+                pwr_falcon_irqdest_host_ctxsw_f(0)          |
+                pwr_falcon_irqdest_host_halt_f(1)           |
+                pwr_falcon_irqdest_host_exterr_f(0)         |
+                pwr_falcon_irqdest_host_swgen0_f(1)         |
+                pwr_falcon_irqdest_host_swgen1_f(0)         |
+                pwr_falcon_irqdest_host_ext_ecc_parity_f(1) |
+                pwr_falcon_irqdest_target_gptmr_f(1)        |
+                pwr_falcon_irqdest_target_wdtmr_f(0)        |
+                pwr_falcon_irqdest_target_mthd_f(0)         |
+                pwr_falcon_irqdest_target_ctxsw_f(0)        |
+                pwr_falcon_irqdest_target_halt_f(0)         |
+                pwr_falcon_irqdest_target_exterr_f(0)       |
+                pwr_falcon_irqdest_target_swgen0_f(0)       |
+                pwr_falcon_irqdest_target_swgen1_f(0)       |
+                pwr_falcon_irqdest_target_ext_ecc_parity_f(0);
+
+        return intr_dest;
+}
+
 static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg,
                         void *param, u32 handle, u32 status)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
index e917188d..dd6db10c 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
@@ -35,4 +35,6 @@ bool gv11b_is_lazy_bootstrap(u32 falcon_id);
 bool gv11b_is_priv_load(u32 falcon_id);
 int gv11b_pmu_setup_elpg(struct gk20a *g);
 
+u32 gv11b_pmu_get_irqdest(struct gk20a *g);
+void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
 #endif /*__PMU_GV11B_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index eba6d806..c16d44f1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -88,6 +88,30 @@ static inline u32 pwr_falcon_irqstat_ext_second_true_f(void)
 {
         return 0x800U;
 }
+static inline u32 pwr_falcon_irqstat_ext_ecc_parity_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pwr_pmu_ecc_intr_status_r(void)
+{
+        return 0x0010abfcU;
+}
+static inline u32 pwr_pmu_ecc_intr_status_corrected_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_ecc_intr_status_corrected_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_ecc_intr_status_uncorrected_m(void)
+{
+        return 0x1U << 1U;
+}
 static inline u32 pwr_falcon_irqmode_r(void)
 {
         return 0x0010a00cU;
@@ -160,6 +184,10 @@ static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v)
 {
         return (v & 0x1U) << 15U;
 }
+static inline u32 pwr_falcon_irqmset_ext_ecc_parity_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
 static inline u32 pwr_falcon_irqmclr_r(void)
 {
         return 0x0010a014U;
@@ -228,6 +256,10 @@ static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v)
 {
         return (v & 0x1U) << 15U;
 }
+static inline u32 pwr_falcon_irqmclr_ext_ecc_parity_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
 static inline u32 pwr_falcon_irqmask_r(void)
 {
         return 0x0010a018U;
@@ -300,6 +332,10 @@ static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v)
 {
         return (v & 0x1U) << 15U;
 }
+static inline u32 pwr_falcon_irqdest_host_ext_ecc_parity_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
 static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
 {
         return (v & 0x1U) << 16U;
@@ -364,6 +400,10 @@ static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v)
 {
         return (v & 0x1U) << 31U;
 }
+static inline u32 pwr_falcon_irqdest_target_ext_ecc_parity_f(u32 v)
+{
+        return (v & 0x1U) << 26U;
+}
 static inline u32 pwr_falcon_curctx_r(void)
 {
         return 0x0010a050U;
@@ -908,6 +948,174 @@ static inline u32 pwr_pmu_pg_intren_r(u32 i)
 {
         return 0x0010a760U + i*4U;
 }
+static inline u32 pwr_pmu_falcon_ecc_status_r(void)
+{
+        return 0x0010a6b0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v)
+{
+        return (v & 0x1U) << 9U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m(void)
+{
+        return 0x1U << 9U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void)
+{
+        return 0x1U << 18U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_falcon_ecc_status_reset_task_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_r(void)
+{
+        return 0x0010a6b4U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_index_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_type_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_type_imem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_type_dmem_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_row_address_s(void)
+{
+        return 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_row_address_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_row_address_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_address_row_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_r(void)
+{
+        return 0x0010a6b8U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_s(void)
+{
+        return 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_r(void)
+{
+        return 0x0010a6bcU;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_s(void)
+{
+        return 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
 static inline u32 pwr_fbif_transcfg_r(u32 i)
 {
         return 0x0010ae00U + i*4U;