gpu: nvgpu: Move fuse HAL to common

Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.

JIRA NVGPU-957

Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177

24 files changed, 409 insertions, 287 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 9da20802..c7ccefb5 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -42,7 +42,10 @@ nvgpu-y += common/bus/bus_gk20a.o \
         common/therm/therm_gm20b.o \
         common/therm/therm_gp10b.o \
         common/therm/therm_gp106.o \
-        common/therm/therm_gv11b.o
+        common/therm/therm_gv11b.o \
+        common/fuse/fuse_gm20b.o \
+        common/fuse/fuse_gp10b.o \
+        common/fuse/fuse_gp106.o
 
 # Linux specific parts of nvgpu.
 nvgpu-y += \
@@ -227,7 +230,6 @@ nvgpu-y += \
         gm20b/pmu_gm20b.o \
         gm20b/mm_gm20b.o \
         gm20b/regops_gm20b.o \
-        gm20b/fuse_gm20b.o \
         boardobj/boardobj.o \
         boardobj/boardobjgrp.o \
         boardobj/boardobjgrpmask.o \
@@ -275,7 +277,6 @@ nvgpu-y += \
         gp10b/regops_gp10b.o \
         gp10b/fecs_trace_gp10b.o \
         gp10b/gp10b.o \
-        gp10b/fuse_gp10b.o \
         gp10b/ecc_gp10b.o \
         gp106/hal_gp106.o \
         gp106/mm_gp106.o \
@@ -289,7 +290,6 @@ nvgpu-y += \
         gp106/fifo_gp106.o \
         gp106/regops_gp106.o \
         gp106/bios_gp106.o \
-        gp106/fuse_gp106.o \
         gv11b/gv11b.o  \
         gv11b/css_gr_gv11b.o  \
         gv11b/dbg_gpu_gv11b.o  \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index 7c6e7f7f..503e0f3a 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -74,6 +74,9 @@ srcs :=	os/posix/nvgpu.c \
         common/therm/therm_gp10b.c \
         common/therm/therm_gv11b.c \
         common/therm/therm_gp106.c \
+        common/fuse/fuse_gm20b.c \
+        common/fuse/fuse_gp10b.c \
+        common/fuse/fuse_gp106.c \
         common/enabled.c \
         common/pramin.c \
         common/semaphore.c \
@@ -160,7 +163,6 @@ srcs :=	os/posix/nvgpu.c \
         gm20b/pmu_gm20b.c \
         gm20b/mm_gm20b.c \
         gm20b/regops_gm20b.c \
-        gm20b/fuse_gm20b.c \
         gp10b/gr_gp10b.c  \
         gp10b/gr_ctx_gp10b.c  \
         gp10b/ce_gp10b.c \
@@ -172,7 +174,6 @@ srcs :=	os/posix/nvgpu.c \
         gp10b/regops_gp10b.c \
         gp10b/fecs_trace_gp10b.c \
         gp10b/gp10b.c \
-        gp10b/fuse_gp10b.c \
         gp10b/ecc_gp10b.c \
         gv11b/gv11b.c  \
         gv11b/dbg_gpu_gv11b.c  \
@@ -200,7 +201,6 @@ srcs :=	os/posix/nvgpu.c \
         gp106/fifo_gp106.c \
         gp106/regops_gp106.c \
         gp106/bios_gp106.c \
-        gp106/fuse_gp106.c \
         gp106/clk_gp106.c \
         gp106/clk_arb_gp106.c \
         gv100/mm_gv100.c \
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c
index 4e6fbe50..67eeffd5 100644
--- a/drivers/gpu/nvgpu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/clk/clk_vin.c
@@ -36,8 +36,6 @@
 #include "clk.h"
 #include "clk_vin.h"
 
-#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
-
 static u32 devinit_get_vin_device_table(struct gk20a *g,
                 struct avfsvinobjs *pvinobjs);
 
@@ -62,196 +60,6 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g,
                                   struct boardobj *board_obj_ptr,
                                   struct nv_pmu_boardobj *ppmudata);
 
-static u32 read_vin_cal_fuse_rev(struct gk20a *g)
-{
-        return fuse_vin_cal_fuse_rev_data_v(
-                gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
-}
-
-static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
-                                             u32 vin_id, u32 *slope,
-                                             u32 *intercept)
-{
-        u32 data = 0;
-        u32 interceptdata = 0;
-        u32 slopedata = 0;
-        u32 gpc0data;
-        u32 gpc0slopedata;
-        u32 gpc0interceptdata;
-
-        /* read gpc0 irrespective of vin id */
-        gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
-        if (gpc0data == 0xFFFFFFFF)
-                return -EINVAL;
-
-        switch (vin_id) {
-        case CTRL_CLK_VIN_ID_GPC0:
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC1:
-                data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC2:
-                data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC3:
-                data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC4:
-                data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC5:
-                data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_SYS:
-        case CTRL_CLK_VIN_ID_XBAR:
-        case CTRL_CLK_VIN_ID_LTC:
-                data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_SRAM:
-                data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
-                break;
-
-        default:
-                return -EINVAL;
-        }
-        if (data == 0xFFFFFFFF)
-                return -EINVAL;
-
-        gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
-                             fuse_vin_cal_gpc0_icpt_frac_data_s()) +
-                            fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
-        gpc0interceptdata = (gpc0interceptdata * 1000U) >>
-                            fuse_vin_cal_gpc0_icpt_frac_data_s();
-
-        switch (vin_id) {
-        case CTRL_CLK_VIN_ID_GPC0:
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC1:
-        case CTRL_CLK_VIN_ID_GPC2:
-        case CTRL_CLK_VIN_ID_GPC3:
-        case CTRL_CLK_VIN_ID_GPC4:
-        case CTRL_CLK_VIN_ID_GPC5:
-        case CTRL_CLK_VIN_ID_SYS:
-        case CTRL_CLK_VIN_ID_XBAR:
-        case CTRL_CLK_VIN_ID_LTC:
-                interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
-                                 fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
-                                fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
-                interceptdata = (interceptdata * 1000U) >>
-                                fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
-                break;
-
-        case CTRL_CLK_VIN_ID_SRAM:
-                interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
-                                 fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
-                                fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
-                interceptdata = (interceptdata * 1000U) >>
-                                fuse_vin_cal_sram_delta_icpt_frac_data_s();
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
-                *intercept = gpc0interceptdata - interceptdata;
-        else
-                *intercept = gpc0interceptdata + interceptdata;
-
-        /* slope */
-        gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
-                             fuse_vin_cal_gpc0_slope_frac_data_s()) +
-                            fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
-        gpc0slopedata = (gpc0slopedata * 1000U) >>
-                            fuse_vin_cal_gpc0_slope_frac_data_s();
-        switch (vin_id) {
-        case CTRL_CLK_VIN_ID_GPC0:
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC1:
-        case CTRL_CLK_VIN_ID_GPC2:
-        case CTRL_CLK_VIN_ID_GPC3:
-        case CTRL_CLK_VIN_ID_GPC4:
-        case CTRL_CLK_VIN_ID_GPC5:
-        case CTRL_CLK_VIN_ID_SYS:
-        case CTRL_CLK_VIN_ID_XBAR:
-        case CTRL_CLK_VIN_ID_LTC:
-        case CTRL_CLK_VIN_ID_SRAM:
-                slopedata =
-                        (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
-                *slope = gpc0slopedata - slopedata;
-        else
-                *slope = gpc0slopedata + slopedata;
-        return 0;
-}
-
-static u32 read_vin_cal_gain_offset_fuse(struct gk20a *g,
-                                             u32 vin_id, s8 *gain,
-                                             s8 *offset)
-{
-        u32 data = 0;
-
-        switch (vin_id) {
-        case CTRL_CLK_VIN_ID_GPC0:
-                data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC1:
-                data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC2:
-                data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC3:
-                data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC4:
-                data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_GPC5:
-                data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_SYS:
-        case CTRL_CLK_VIN_ID_XBAR:
-        case CTRL_CLK_VIN_ID_LTC:
-                data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
-                break;
-
-        case CTRL_CLK_VIN_ID_SRAM:
-                data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
-                break;
-
-        default:
-                return -EINVAL;
-        }
-        if (data == 0xFFFFFFFF)
-                return -EINVAL;
-        *gain = (s8) (data >> 16) & 0x1f;
-        *offset = (s8) data & 0x7f;
-
-        return 0;
-}
-
 u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
                                         struct avfsvinobjs *pvinobjs,
                                         struct vin_device_v20 *pvindev)
@@ -260,13 +68,13 @@ u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
         u32 slope, intercept;
         u8 i;
 
-        if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) {
+        if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
                 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
                                      struct vin_device_v20 *, pvindev, i) {
                         slope = 0;
                         intercept = 0;
                         pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
-                        status = read_vin_cal_slope_intercept_fuse(g,
+                        status = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,
                                         pvindev->super.id, &slope, &intercept);
                         if (status) {
                                 nvgpu_err(g,
@@ -291,13 +99,13 @@ u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
         s8 gain, offset;
         u8 i;
 
-        if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) {
+        if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
                 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
                                      struct vin_device_v20 *, pvindev, i) {
                         gain = 0;
                         offset = 0;
                         pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
-                        status = read_vin_cal_gain_offset_fuse(g,
+                        status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g,
                                         pvindev->super.id, &gain, &offset);
                         if (status) {
                                 nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index 95ac8ee3..c790e297 100644
--- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -89,3 +89,38 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
 
         return 0;
 }
+
+u32 gm20b_fuse_status_opt_fbio(struct gk20a *g)
+{
+        return nvgpu_readl(g, fuse_status_opt_fbio_r());
+}
+
+u32 gm20b_fuse_status_opt_fbp(struct gk20a *g)
+{
+        return nvgpu_readl(g, fuse_status_opt_fbp_r());
+}
+
+u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
+{
+        return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
+}
+
+u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
+{
+        return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
+}
+
+void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val)
+{
+        nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val);
+}
+
+u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g)
+{
+        return nvgpu_readl(g, fuse_opt_sec_debug_en_r());
+}
+
+u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g)
+{
+        return gk20a_readl(g, fuse_opt_priv_sec_en_r());
+}
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
index 51734b2f..5e2d194b 100644
--- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
@@ -33,5 +33,12 @@
 struct gk20a;
 
 int gm20b_fuse_check_priv_security(struct gk20a *g);
+u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
+u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
+u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
+void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
+u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
+u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c
new file mode 100644
index 00000000..17951e27
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c
@@ -0,0 +1,230 @@
+/*
+ * GP106 FUSE
+ *
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+
+#include "gk20a/gk20a.h"
+
+#include "fuse_gp106.h"
+
+#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
+
+int gp106_fuse_check_priv_security(struct gk20a *g)
+{
+        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+
+        return 0;
+}
+
+u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g)
+{
+        return fuse_vin_cal_fuse_rev_data_v(
+                gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
+}
+
+u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
+                                             u32 vin_id, u32 *slope,
+                                             u32 *intercept)
+{
+        u32 data = 0;
+        u32 interceptdata = 0;
+        u32 slopedata = 0;
+        u32 gpc0data;
+        u32 gpc0slopedata;
+        u32 gpc0interceptdata;
+
+        /* read gpc0 irrespective of vin id */
+        gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
+        if (gpc0data == 0xFFFFFFFF)
+                return -EINVAL;
+
+        switch (vin_id) {
+        case CTRL_CLK_VIN_ID_GPC0:
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC1:
+                data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC2:
+                data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC3:
+                data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC4:
+                data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC5:
+                data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_SYS:
+        case CTRL_CLK_VIN_ID_XBAR:
+        case CTRL_CLK_VIN_ID_LTC:
+                data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_SRAM:
+                data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
+                break;
+
+        default:
+                return -EINVAL;
+        }
+        if (data == 0xFFFFFFFF)
+                return -EINVAL;
+
+        gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
+                             fuse_vin_cal_gpc0_icpt_frac_data_s()) +
+                            fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
+        gpc0interceptdata = (gpc0interceptdata * 1000U) >>
+                            fuse_vin_cal_gpc0_icpt_frac_data_s();
+
+        switch (vin_id) {
+        case CTRL_CLK_VIN_ID_GPC0:
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC1:
+        case CTRL_CLK_VIN_ID_GPC2:
+        case CTRL_CLK_VIN_ID_GPC3:
+        case CTRL_CLK_VIN_ID_GPC4:
+        case CTRL_CLK_VIN_ID_GPC5:
+        case CTRL_CLK_VIN_ID_SYS:
+        case CTRL_CLK_VIN_ID_XBAR:
+        case CTRL_CLK_VIN_ID_LTC:
+                interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
+                                 fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
+                                fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
+                interceptdata = (interceptdata * 1000U) >>
+                                fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
+                break;
+
+        case CTRL_CLK_VIN_ID_SRAM:
+                interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
+                                 fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
+                                fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
+                interceptdata = (interceptdata * 1000U) >>
+                                fuse_vin_cal_sram_delta_icpt_frac_data_s();
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
+                *intercept = gpc0interceptdata - interceptdata;
+        else
+                *intercept = gpc0interceptdata + interceptdata;
+
+        /* slope */
+        gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
+                             fuse_vin_cal_gpc0_slope_frac_data_s()) +
+                            fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
+        gpc0slopedata = (gpc0slopedata * 1000U) >>
+                            fuse_vin_cal_gpc0_slope_frac_data_s();
+        switch (vin_id) {
+        case CTRL_CLK_VIN_ID_GPC0:
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC1:
+        case CTRL_CLK_VIN_ID_GPC2:
+        case CTRL_CLK_VIN_ID_GPC3:
+        case CTRL_CLK_VIN_ID_GPC4:
+        case CTRL_CLK_VIN_ID_GPC5:
+        case CTRL_CLK_VIN_ID_SYS:
+        case CTRL_CLK_VIN_ID_XBAR:
+        case CTRL_CLK_VIN_ID_LTC:
+        case CTRL_CLK_VIN_ID_SRAM:
+                slopedata =
+                        (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
+                *slope = gpc0slopedata - slopedata;
+        else
+                *slope = gpc0slopedata + slopedata;
+        return 0;
+}
+
+u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
+                                             u32 vin_id, s8 *gain,
+                                             s8 *offset)
+{
+        u32 data = 0;
+
+        switch (vin_id) {
+        case CTRL_CLK_VIN_ID_GPC0:
+                data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC1:
+                data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC2:
+                data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC3:
+                data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC4:
+                data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_GPC5:
+                data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_SYS:
+        case CTRL_CLK_VIN_ID_XBAR:
+        case CTRL_CLK_VIN_ID_LTC:
+                data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
+                break;
+
+        case CTRL_CLK_VIN_ID_SRAM:
+                data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
+                break;
+
+        default:
+                return -EINVAL;
+        }
+        if (data == 0xFFFFFFFF)
+                return -EINVAL;
+        *gain = (s8) (data >> 16) & 0x1f;
+        *offset = (s8) data & 0x7f;
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
index dfb776b8..f014ee8c 100644
--- a/drivers/gpu/nvgpu/gp106/fuse_gp106.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
@@ -28,5 +28,12 @@
 struct gk20a;
 
 int gp106_fuse_check_priv_security(struct gk20a *g);
+u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g);
+u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
+                                             u32 vin_id, u32 *slope,
+                                             u32 *intercept);
+u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
+                                             u32 vin_id, s8 *gain,
+                                             s8 *offset);
 
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
index a79d5e1c..3a26e1b9 100644
--- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
@@ -29,8 +29,7 @@
 
 #include "gk20a/gk20a.h"
 
-#include "gm20b/fuse_gm20b.h"
-
+#include "fuse_gm20b.h"
 #include "fuse_gp10b.h"
 
 #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
index d9037e22..d9037e22 100644
--- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 1fe0cb5d..febd7e0c 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1256,6 +1256,20 @@ struct gpu_ops {
                 int (*check_priv_security)(struct gk20a *g);
                 bool (*is_opt_ecc_enable)(struct gk20a *g);
                 bool (*is_opt_feature_override_disable)(struct gk20a *g);
+                u32 (*fuse_status_opt_fbio)(struct gk20a *g);
+                u32 (*fuse_status_opt_fbp)(struct gk20a *g);
+                u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp);
+                u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc);
+                void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val);
+                u32 (*fuse_opt_sec_debug_en)(struct gk20a *g);
+                u32 (*fuse_opt_priv_sec_en)(struct gk20a *g);
+                u32 (*read_vin_cal_fuse_rev)(struct gk20a *g);
+                u32 (*read_vin_cal_slope_intercept_fuse)(struct gk20a *g,
+                                                             u32 vin_id, u32 *slope,
+                                                             u32 *intercept);
+                u32 (*read_vin_cal_gain_offset_fuse)(struct gk20a *g,
+                                                             u32 vin_id, s8 *gain,
+                                                             s8 *offset);
         } fuse;
         struct {
                 int (*init)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index abc39362..68ae91e8 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -40,7 +40,6 @@
 #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_top_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_perf_gm20b.h>
 
 void gr_gm20b_init_gpc_mmu(struct gk20a *g)
@@ -549,7 +548,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
         struct gr_gk20a *gr = &g->gr;
 
         /* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */
-        val = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(gpc_index));
+        val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, gpc_index);
 
         return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1);
 }
@@ -1076,7 +1075,7 @@ u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g)
          * flip the bits.
          * Also set unused bits to zero
          */
-        fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r());
+        fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g);
         fbp_en_mask = ~fbp_en_mask;
         fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1);
 
@@ -1114,7 +1113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g)
 
         /* mask of Rop_L2 for each FBP */
         for_each_set_bit(i, &fbp_en_mask, max_fbps_count) {
-                tmp = gk20a_readl(g, fuse_status_opt_rop_l2_fbp_r(i));
+                tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i);
                 gr->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp;
         }
 
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 431cfc9b..acdf4591 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -32,6 +32,7 @@
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gm20b.h"
 #include "common/ltc/ltc_gm20b.h"
+#include "common/fuse/fuse_gm20b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ce2_gk20a.h"
@@ -55,7 +56,6 @@
 #include "regops_gm20b.h"
 #include "hal_gm20b.h"
 #include "acr_gm20b.h"
-#include "fuse_gm20b.h"
 
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
@@ -64,7 +64,6 @@
 #include <nvgpu/error_notifier.h>
 
 #include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_top_gm20b.h>
@@ -649,6 +648,16 @@ static const struct gpu_ops gm20b_ops = {
         },
         .fuse = {
                 .check_priv_security = gm20b_fuse_check_priv_security,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = NULL,
+                .read_vin_cal_slope_intercept_fuse = NULL,
+                .read_vin_cal_gain_offset_fuse = NULL,
         },
         .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
         .get_litter_value = gm20b_get_litter_value,
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 731078f7..53bec96f 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -36,7 +36,6 @@
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
 
 #define gm20b_dbg_pmu(g, fmt, arg...) \
         nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
@@ -267,9 +266,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g)
         u32 val;
 
         nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x",
-                        gk20a_readl(g, fuse_opt_sec_debug_en_r()));
+                        g->ops.fuse.fuse_opt_sec_debug_en(g));
         nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
-                        gk20a_readl(g, fuse_opt_priv_sec_en_r()));
+                        g->ops.fuse.fuse_opt_priv_sec_en(g));
         nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
         nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
 }
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.c b/drivers/gpu/nvgpu/gp106/fuse_gp106.c
deleted file mode 100644
index 82e3217f..00000000
--- a/drivers/gpu/nvgpu/gp106/fuse_gp106.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * GP106 FUSE
- *
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-
-#include "gk20a/gk20a.h"
-#include "gp106/fuse_gp106.h"
-
-int gp106_fuse_check_priv_security(struct gk20a *g)
-{
-        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 52fcc9d3..f3b5dd87 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -38,6 +38,9 @@
 #include "common/therm/therm_gp106.h"
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
+#include "common/fuse/fuse_gp106.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -60,7 +63,6 @@
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
 #include "gp10b/gr_gp10b.h"
-#include "gp10b/fuse_gp10b.h"
 
 #include "gp106/fifo_gp106.h"
 #include "gp106/regops_gp106.h"
@@ -85,7 +87,6 @@
 #include "gp106/gr_ctx_gp106.h"
 #include "gp106/gr_gp106.h"
 #include "gp106/flcn_gp106.h"
-#include "gp106/fuse_gp106.h"
 
 #include "hal_gp106.h"
 
@@ -788,6 +789,18 @@ static const struct gpu_ops gp106_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev,
+                .read_vin_cal_slope_intercept_fuse =
+                        gp106_fuse_read_vin_cal_slope_intercept_fuse,
+                .read_vin_cal_gain_offset_fuse =
+                        gp106_fuse_read_vin_cal_gain_offset_fuse,
         },
         .get_litter_value = gp106_get_litter_value,
         .chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 7df17ed7..efd66b5d 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -36,6 +36,8 @@
 #include "common/therm/therm_gp10b.h"
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -70,7 +72,6 @@
 
 #include "gp10b.h"
 #include "hal_gp10b.h"
-#include "fuse_gp10b.h"
 
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
@@ -80,7 +81,6 @@
 #include <nvgpu/error_notifier.h>
 
 #include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_top_gp10b.h>
@@ -597,7 +597,7 @@ static const struct gpu_ops gp10b_ops = {
                 .pmu_pg_init_param = gp10b_pg_gr_init,
                 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
                 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
-                .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
+                .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
                 .reset_engine = gk20a_pmu_engine_reset,
                 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
                 .get_irqdest = gk20a_pmu_get_irqdest,
@@ -702,6 +702,16 @@ static const struct gpu_ops gp10b_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = NULL,
+                .read_vin_cal_slope_intercept_fuse = NULL,
+                .read_vin_cal_gain_offset_fuse = NULL,
         },
         .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
         .get_litter_value = gp10b_get_litter_value,
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 6ecb7957..d6497173 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -36,7 +36,6 @@
 #include "pmu_gp10b.h"
 
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 
 #define gp10b_dbg_pmu(g, fmt, arg...) \
         nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
@@ -375,19 +374,6 @@ bool gp10b_is_priv_load(u32 falcon_id)
         return enable_status;
 }
 
-/*Dump Security related fuses*/
-void pmu_dump_security_fuses_gp10b(struct gk20a *g)
-{
-        u32 val;
-
-        nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x",
-                        gk20a_readl(g, fuse_opt_sec_debug_en_r()));
-        nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
-                        gk20a_readl(g, fuse_opt_priv_sec_en_r()));
-        nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
-        nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
-}
-
 bool gp10b_is_pmu_supported(struct gk20a *g)
 {
         return true;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 44e0ec98..87c3ba79 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -35,7 +35,6 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g);
 void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 int gp10b_pmu_setup_elpg(struct gk20a *g);
-void pmu_dump_security_fuses_gp10b(struct gk20a *g);
 int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
 int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index 13092f2a..79526947 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -37,7 +37,6 @@
 #include <nvgpu/hw/gv100/hw_gr_gv100.h>
 #include <nvgpu/hw/gv100/hw_fb_gv100.h>
 #include <nvgpu/hw/gv100/hw_proj_gv100.h>
-#include <nvgpu/hw/gv100/hw_fuse_gv100.h>
 #include <nvgpu/hw/gv100/hw_top_gv100.h>
 #include <nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h>
 #include <nvgpu/hw/gv100/hw_perf_gv100.h>
@@ -391,7 +390,7 @@ static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g)
          * flip the bits.
          * Also set unused bits to zero
          */
-        active_fbpa_mask = nvgpu_readl(g, fuse_status_opt_fbio_r());
+        active_fbpa_mask = g->ops.fuse.fuse_status_opt_fbio(g);
         active_fbpa_mask = ~active_fbpa_mask;
         active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1);
 
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 8565d5fc..69ad018a 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -42,6 +42,9 @@
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
 #include "common/ltc/ltc_gv11b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
+#include "common/fuse/fuse_gp106.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -77,7 +80,6 @@
 #include "gp10b/fecs_trace_gp10b.h"
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
-#include "gp10b/fuse_gp10b.h"
 
 #include "gv11b/css_gr_gv11b.h"
 #include "gv11b/dbg_gpu_gv11b.h"
@@ -883,6 +885,18 @@ static const struct gpu_ops gv100_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev,
+                .read_vin_cal_slope_intercept_fuse =
+                        gp106_fuse_read_vin_cal_slope_intercept_fuse,
+                .read_vin_cal_gain_offset_fuse =
+                        gp106_fuse_read_vin_cal_gain_offset_fuse,
         },
 #if defined(CONFIG_TEGRA_NVLINK)
         .nvlink = {
@@ -947,6 +961,7 @@ int gv100_init_hal(struct gk20a *g)
         gops->xve = gv100_ops.xve;
         gops->falcon = gv100_ops.falcon;
         gops->priv_ring = gv100_ops.priv_ring;
+        gops->fuse = gv100_ops.fuse;
         gops->nvlink = gv100_ops.nvlink;
 
         /* clocks */
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 41d2f695..5d237839 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -59,7 +59,6 @@
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 
 #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100
 
@@ -131,16 +130,16 @@ bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
 
 void gr_gv11b_powergate_tpc(struct gk20a *g)
 {
-        u32 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0));
+        u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
 
         if (tpc_pg_status == g->tpc_pg_mask) {
                 return;
         }
 
-        gk20a_writel(g, fuse_ctrl_opt_tpc_gpc_r(0), (g->tpc_pg_mask));
+        g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask);
 
         do {
-                tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0));
+                tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
         } while (tpc_pg_status != g->tpc_pg_mask);
 
         gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index baafa801..0989e00a 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -39,6 +39,8 @@
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
 #include "common/ltc/ltc_gv11b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -65,7 +67,6 @@
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
 #include "gp10b/gr_gp10b.h"
-#include "gp10b/fuse_gp10b.h"
 
 #include "gp106/pmu_gp106.h"
 #include "gp106/acr_gp106.h"
@@ -100,7 +101,6 @@
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
 int gv11b_get_litter_value(struct gk20a *g, int value)
@@ -689,7 +689,7 @@ static const struct gpu_ops gv11b_ops = {
                 .pmu_pg_init_param = gv11b_pg_gr_init,
                 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
                 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
-                .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
+                .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
                 .reset_engine = gp106_pmu_engine_reset,
                 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
                 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
@@ -801,6 +801,16 @@ static const struct gpu_ops gv11b_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = NULL,
+                .read_vin_cal_slope_intercept_fuse = NULL,
+                .read_vin_cal_gain_offset_fuse = NULL,
         },
         .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
         .get_litter_value = gv11b_get_litter_value,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index b046ba6c..00efe316 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -32,6 +32,8 @@
 #include "common/therm/therm_gp10b.h"
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
 
 #include "vgpu/fifo_vgpu.h"
 #include "vgpu/gr_vgpu.h"
@@ -59,7 +61,6 @@
 #include "gp10b/gr_ctx_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/regops_gp10b.h"
-#include "gp10b/fuse_gp10b.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
@@ -71,7 +72,6 @@
 #include <nvgpu/vgpu/vgpu.h>
 #include <nvgpu/error_notifier.h>
 
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_top_gp10b.h>
@@ -464,7 +464,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .pmu_pg_init_param = gp10b_pg_gr_init,
                 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
                 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
-                .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
+                .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
                 .reset_engine = gk20a_pmu_engine_reset,
                 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
         },
@@ -566,6 +566,16 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = NULL,
+                .read_vin_cal_slope_intercept_fuse = NULL,
+                .read_vin_cal_gain_offset_fuse = NULL,
         },
         .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
         .get_litter_value = gp10b_get_litter_value,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index f9d09ebd..204c0105 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -35,6 +35,8 @@
 #include "common/ltc/ltc_gm20b.h"
 #include "common/ltc/ltc_gp10b.h"
 #include "common/ltc/ltc_gv11b.h"
+#include "common/fuse/fuse_gm20b.h"
+#include "common/fuse/fuse_gp10b.h"
 
 #include <gk20a/gk20a.h>
 #include <gv11b/hal_gv11b.h>
@@ -68,7 +70,6 @@
 #include <gp10b/ce_gp10b.h>
 #include "gp10b/gr_gp10b.h"
 #include <gp10b/fifo_gp10b.h>
-#include <gp10b/fuse_gp10b.h>
 
 #include <gp106/pmu_gp106.h>
 #include <gp106/acr_gp106.h>
@@ -91,7 +92,6 @@
 #include "vgpu_subctx_gv11b.h"
 #include "vgpu_tsg_gv11b.h"
 
-#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
@@ -530,7 +530,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .pmu_pg_init_param = gv11b_pg_gr_init,
                 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
                 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
-                .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
+                .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
                 .reset_engine = gp106_pmu_engine_reset,
                 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
                 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
@@ -635,6 +635,16 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
                 .is_opt_feature_override_disable =
                         gp10b_fuse_is_opt_feature_override_disable,
+                .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
+                .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
+                .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
+                .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
+                .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
+                .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
+                .read_vin_cal_fuse_rev = NULL,
+                .read_vin_cal_slope_intercept_fuse = NULL,
+                .read_vin_cal_gain_offset_fuse = NULL,
         },
         .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
         .get_litter_value = gv11b_get_litter_value,
@@ -669,6 +679,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 #endif
         gops->falcon = vgpu_gv11b_ops.falcon;
         gops->priv_ring = vgpu_gv11b_ops.priv_ring;
+        gops->fuse = vgpu_gv11b_ops.fuse;
 
         /* Lone functions */
         gops->chip_init_gpu_characteristics =