gpu: nvgpu: move gm20b clock register to platform file

We currently register gm20b clock operations gm20b_clk_ops
in function gm20b_register_gpcclk() which is in clk_gm20b.c

Since this is common clock framework and hence linux dependency,
move this clock registration to platform specific file

Note that all the clock operations remain in clk_gm20b.c.
APIs in platform file will eventually call operations
in clk_gm20b.c

Jira NVGPU-49

Change-Id: Ib0b0d9f4719b196d764825a7dddb08f1fbd7a567
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 98 insertions, 72 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index f1f75b74..31ec419a 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -1131,13 +1131,7 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
         return 0;
 }
 
-static int gm20b_init_clk_reset_enable_hw(struct gk20a *g)
-{
-        gk20a_dbg_fn("");
-        return 0;
-}
-
-static int gm20b_init_clk_setup_sw(struct gk20a *g)
+int gm20b_init_clk_setup_sw(struct gk20a *g)
 {
         struct clk_gk20a *clk = &g->clk;
         unsigned long safe_rate;
@@ -1238,13 +1232,11 @@ fail:
 }
 
 
-#ifdef CONFIG_COMMON_CLK
 static int set_pll_freq(struct gk20a *g, int allow_slide);
 static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq);
 
-static int gm20b_clk_prepare(struct clk_hw *hw)
+int gm20b_clk_prepare(struct clk_gk20a *clk)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
         int ret = 0;
 
         nvgpu_mutex_acquire(&clk->clk_mutex);
@@ -1254,34 +1246,27 @@ static int gm20b_clk_prepare(struct clk_hw *hw)
         return ret;
 }
 
-static void gm20b_clk_unprepare(struct clk_hw *hw)
+void gm20b_clk_unprepare(struct clk_gk20a *clk)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
-
         nvgpu_mutex_acquire(&clk->clk_mutex);
         if (clk->gpc_pll.enabled && clk->clk_hw_on)
                 clk_disable_gpcpll(clk->g, 1);
         nvgpu_mutex_release(&clk->clk_mutex);
 }
 
-static int gm20b_clk_is_prepared(struct clk_hw *hw)
+int gm20b_clk_is_prepared(struct clk_gk20a *clk)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
-
         return clk->gpc_pll.enabled && clk->clk_hw_on;
 }
 
-static unsigned long gm20b_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
-
         return rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
 }
 
-static int gm20b_gpcclk_set_rate(struct clk_hw *hw, unsigned long rate,
+int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate,
                                  unsigned long parent_rate)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
         u32 old_freq;
         int ret = -ENODATA;
 
@@ -1295,10 +1280,9 @@ static int gm20b_gpcclk_set_rate(struct clk_hw *hw, unsigned long rate,
         return ret;
 }
 
-static long gm20b_round_rate(struct clk_hw *hw, unsigned long rate,
+long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
                              unsigned long *parent_rate)
 {
-        struct clk_gk20a *clk = to_clk_gk20a(hw);
         u32 freq;
         struct pll tmp_pll;
         unsigned long maxrate;
@@ -1321,48 +1305,6 @@ static long gm20b_round_rate(struct clk_hw *hw, unsigned long rate,
         return rate_gpc2clk_to_gpu(tmp_pll.freq);
 }
 
-static const struct clk_ops gm20b_clk_ops = {
-        .prepare = gm20b_clk_prepare,
-        .unprepare = gm20b_clk_unprepare,
-        .is_prepared = gm20b_clk_is_prepared,
-        .recalc_rate = gm20b_recalc_rate,
-        .set_rate = gm20b_gpcclk_set_rate,
-        .round_rate = gm20b_round_rate,
-};
-
-int gm20b_register_gpcclk(struct gk20a *g) {
-        const char *parent_name = "pllg_ref";
-        struct clk_gk20a *clk = &g->clk;
-        struct clk_init_data init;
-        struct clk *c;
-        int err = 0;
-
-        err = gm20b_init_clk_setup_sw(g);
-        if (err)
-                return err;
-
-        init.name = "gpcclk";
-        init.ops = &gm20b_clk_ops;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-        init.flags = 0;
-
-        /* Data in .init is copied by clk_register(), so stack variable OK */
-        clk->hw.init = &init;
-        c = clk_register(g->dev, &clk->hw);
-        if (IS_ERR(c)) {
-                nvgpu_err(g, "Failed to register GPCPLL clock");
-                return -EINVAL;
-        }
-
-        clk->g = g;
-        clk_register_clkdev(c, "gpcclk", "gpcclk");
-
-        return err;
-}
-#endif /* CONFIG_COMMON_CLK */
-
-
 static int gm20b_init_clk_setup_hw(struct gk20a *g)
 {
         u32 data;
@@ -1475,10 +1417,6 @@ static int gm20b_init_clk_support(struct gk20a *g)
 
         gk20a_dbg_fn("");
 
-        err = gm20b_init_clk_reset_enable_hw(g);
-        if (err)
-                return err;
-
         nvgpu_mutex_acquire(&clk->clk_mutex);
         clk->clk_hw_on = true;
 
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
index 5746165e..f7912345 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
@@ -23,8 +23,15 @@
 
 void gm20b_init_clk_ops(struct gpu_ops *gops);
 
-#ifdef CONFIG_COMMON_CLK
-int gm20b_register_gpcclk(struct gk20a *g);
-#endif
+int gm20b_init_clk_setup_sw(struct gk20a *g);
+
+int gm20b_clk_prepare(struct clk_gk20a *clk);
+void gm20b_clk_unprepare(struct clk_gk20a *clk);
+int gm20b_clk_is_prepared(struct clk_gk20a *clk);
+unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate);
+int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate,
+                unsigned long parent_rate);
+long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
+                unsigned long *parent_rate);
 
 #endif /* _NVHOST_CLK_GM20B_H_ */
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
index a8a1451a..d6e448d8 100644
--- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
@@ -753,6 +753,87 @@ void gk20a_tegra_init_secure_alloc(struct gk20a *g)
         g->ops.mm.secure_alloc = gk20a_tegra_secure_alloc;
 }
 
+#ifdef CONFIG_COMMON_CLK
+static int gm20b_clk_prepare_ops(struct clk_hw *hw)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        return gm20b_clk_prepare(clk);
+}
+
+static void gm20b_clk_unprepare_ops(struct clk_hw *hw)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        gm20b_clk_unprepare(clk);
+}
+
+static int gm20b_clk_is_prepared_ops(struct clk_hw *hw)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        return gm20b_clk_is_prepared(clk);
+}
+
+static unsigned long gm20b_recalc_rate_ops(struct clk_hw *hw, unsigned long parent_rate)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        return gm20b_recalc_rate(clk, parent_rate);
+}
+
+static int gm20b_gpcclk_set_rate_ops(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long parent_rate)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        return gm20b_gpcclk_set_rate(clk, rate, parent_rate);
+}
+
+static long gm20b_round_rate_ops(struct clk_hw *hw, unsigned long rate,
+                             unsigned long *parent_rate)
+{
+        struct clk_gk20a *clk = to_clk_gk20a(hw);
+        return gm20b_round_rate(clk, rate, parent_rate);
+}
+
+static const struct clk_ops gm20b_clk_ops = {
+        .prepare = gm20b_clk_prepare_ops,
+        .unprepare = gm20b_clk_unprepare_ops,
+        .is_prepared = gm20b_clk_is_prepared_ops,
+        .recalc_rate = gm20b_recalc_rate_ops,
+        .set_rate = gm20b_gpcclk_set_rate_ops,
+        .round_rate = gm20b_round_rate_ops,
+};
+
+static int gm20b_register_gpcclk(struct gk20a *g)
+{
+        const char *parent_name = "pllg_ref";
+        struct clk_gk20a *clk = &g->clk;
+        struct clk_init_data init;
+        struct clk *c;
+        int err = 0;
+
+        err = gm20b_init_clk_setup_sw(g);
+        if (err)
+                return err;
+
+        init.name = "gpcclk";
+        init.ops = &gm20b_clk_ops;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+        init.flags = 0;
+
+        /* Data in .init is copied by clk_register(), so stack variable OK */
+        clk->hw.init = &init;
+        c = clk_register(g->dev, &clk->hw);
+        if (IS_ERR(c)) {
+                nvgpu_err(g, "Failed to register GPCPLL clock");
+                return -EINVAL;
+        }
+
+        clk->g = g;
+        clk_register_clkdev(c, "gpcclk", "gpcclk");
+
+        return err;
+}
+#endif /* CONFIG_COMMON_CLK */
+
 static int gk20a_tegra_probe(struct device *dev)
 {
         struct gk20a_platform *platform = dev_get_drvdata(dev);