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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-11-07 13:25:07 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-09 17:27:04 -0500
commit1dad4adbd2aecfd484a84d47b29b81bb665bc60b (patch)
treeafe2829ebef911e8ee4409753a2db7f626897624
parent39527d58855fb7cb7dffef01c4f7290ae3a119ce (diff)
gpu: nvgpu: Move fuse override DT handling
Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Iba64a5d53bf4eb94198c0408a462620efc2ddde4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c46
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c48
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.h1
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c1
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c1
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c39
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c1
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c1
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c1
11 files changed, 46 insertions, 97 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index 2e90fbe4..6b27c9f1 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -25,6 +25,8 @@
25#include <linux/reset.h> 25#include <linux/reset.h>
26#include <linux/platform/tegra/common.h> 26#include <linux/platform/tegra/common.h>
27#include <uapi/linux/nvgpu.h> 27#include <uapi/linux/nvgpu.h>
28#include <dt-bindings/soc/gm20b-fuse.h>
29#include <dt-bindings/soc/gp10b-fuse.h>
28 30
29#include <nvgpu/dma.h> 31#include <nvgpu/dma.h>
30#include <nvgpu/kmem.h> 32#include <nvgpu/kmem.h>
@@ -994,6 +996,48 @@ static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)
994 gk20a_get_platform(&pdev->dev)->g = gk20a; 996 gk20a_get_platform(&pdev->dev)->g = gk20a;
995} 997}
996 998
999static int nvgpu_read_fuse_overrides(struct gk20a *g)
1000{
1001 struct device_node *np = dev_from_gk20a(g)->of_node;
1002 u32 *fuses;
1003 int count, i;
1004
1005 if (!np) /* may be pcie device */
1006 return 0;
1007
1008 count = of_property_count_elems_of_size(np, "fuse-overrides", 8);
1009 if (count <= 0)
1010 return count;
1011
1012 fuses = nvgpu_kmalloc(g, sizeof(u32) * count * 2);
1013 if (!fuses)
1014 return -ENOMEM;
1015 of_property_read_u32_array(np, "fuse-overrides", fuses, count * 2);
1016 for (i = 0; i < count; i++) {
1017 u32 fuse, value;
1018
1019 fuse = fuses[2 * i];
1020 value = fuses[2 * i + 1];
1021 switch (fuse) {
1022 case GM20B_FUSE_OPT_TPC_DISABLE:
1023 g->tpc_fs_mask_user = ~value;
1024 break;
1025#ifdef CONFIG_ARCH_TEGRA_18x_SOC
1026 case GP10B_FUSE_OPT_ECC_EN:
1027 g->gr.t18x.fecs_feature_override_ecc_val = value;
1028 break;
1029#endif
1030 default:
1031 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
1032 break;
1033 }
1034 }
1035
1036 nvgpu_kfree(g, fuses);
1037
1038 return 0;
1039}
1040
997static int gk20a_probe(struct platform_device *dev) 1041static int gk20a_probe(struct platform_device *dev)
998{ 1042{
999 struct nvgpu_os_linux *l; 1043 struct nvgpu_os_linux *l;
@@ -1077,6 +1121,8 @@ static int gk20a_probe(struct platform_device *dev)
1077 if (err) 1121 if (err)
1078 return err; 1122 return err;
1079 1123
1124 err = nvgpu_read_fuse_overrides(gk20a);
1125
1080#ifdef CONFIG_RESET_CONTROLLER 1126#ifdef CONFIG_RESET_CONTROLLER
1081 platform->reset_control = devm_reset_control_get(&dev->dev, NULL); 1127 platform->reset_control = devm_reset_control_get(&dev->dev, NULL);
1082 if (IS_ERR(platform->reset_control)) 1128 if (IS_ERR(platform->reset_control))
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 4a344387..92b83978 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -385,7 +385,6 @@ struct gpu_ops {
385 void (*update_boosted_ctx)(struct gk20a *g, 385 void (*update_boosted_ctx)(struct gk20a *g,
386 struct nvgpu_mem *mem, 386 struct nvgpu_mem *mem,
387 struct gr_ctx_desc *gr_ctx); 387 struct gr_ctx_desc *gr_ctx);
388 int (*fuse_override)(struct gk20a *g);
389 void (*init_sm_id_table)(struct gk20a *g); 388 void (*init_sm_id_table)(struct gk20a *g);
390 int (*load_smid_config)(struct gk20a *g); 389 int (*load_smid_config)(struct gk20a *g);
391 void (*program_sm_id_numbering)(struct gk20a *g, 390 void (*program_sm_id_numbering)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index d4d6cd2d..73cfa3bf 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4813,9 +4813,6 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
4813 return 0; 4813 return 0;
4814 } 4814 }
4815 4815
4816 if (g->ops.gr.fuse_override)
4817 g->ops.gr.fuse_override(g);
4818
4819 gr->g = g; 4816 gr->g = g;
4820 4817
4821#if defined(CONFIG_GK20A_CYCLE_STATS) 4818#if defined(CONFIG_GK20A_CYCLE_STATS)
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 7ec8e2cb..afe60b98 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -22,8 +22,6 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#include <dt-bindings/soc/gm20b-fuse.h>
26
27#include <nvgpu/kmem.h> 25#include <nvgpu/kmem.h>
28#include <nvgpu/log.h> 26#include <nvgpu/log.h>
29#include <nvgpu/enabled.h> 27#include <nvgpu/enabled.h>
@@ -1423,52 +1421,6 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
1423 return 0; 1421 return 0;
1424} 1422}
1425 1423
1426int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask)
1427{
1428 if (!mask)
1429 return 0;
1430
1431 g->tpc_fs_mask_user = ~mask;
1432
1433 return 0;
1434}
1435
1436int gm20b_gr_fuse_override(struct gk20a *g)
1437{
1438 struct device_node *np = dev_from_gk20a(g)->of_node;
1439 u32 *fuses;
1440 int count, i;
1441
1442 if (!np) /* may be pcie device */
1443 return 0;
1444
1445 count = of_property_count_elems_of_size(np, "fuse-overrides", 8);
1446 if (count <= 0)
1447 return count;
1448
1449 fuses = nvgpu_kmalloc(g, sizeof(u32) * count * 2);
1450 if (!fuses)
1451 return -ENOMEM;
1452 of_property_read_u32_array(np, "fuse-overrides", fuses, count * 2);
1453 for (i = 0; i < count; i++) {
1454 u32 fuse, value;
1455
1456 fuse = fuses[2 * i];
1457 value = fuses[2 * i + 1];
1458 switch (fuse) {
1459 case GM20B_FUSE_OPT_TPC_DISABLE:
1460 gm20b_gr_tpc_disable_override(g, value);
1461 break;
1462 default:
1463 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
1464 break;
1465 }
1466 }
1467
1468 nvgpu_kfree(g, fuses);
1469 return 0;
1470}
1471
1472bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr) 1424bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
1473{ 1425{
1474 u32 ltc_shared_base = ltc_ltcs_ltss_v(); 1426 u32 ltc_shared_base = ltc_ltcs_ltss_v();
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 15deaa0d..18e6b032 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -124,7 +124,6 @@ int gm20b_gr_clear_sm_error_state(struct gk20a *g,
124 struct channel_gk20a *ch, u32 sm_id); 124 struct channel_gk20a *ch, u32 sm_id);
125int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, 125int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
126 struct nvgpu_preemption_modes_rec *preemption_modes_rec); 126 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
127int gm20b_gr_fuse_override(struct gk20a *g);
128bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr); 127bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
129bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr); 128bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
130void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr, 129void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 69afb9bc..4e214cc4 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -254,7 +254,6 @@ static const struct gpu_ops gm20b_ops = {
254 .suspend_contexts = gr_gk20a_suspend_contexts, 254 .suspend_contexts = gr_gk20a_suspend_contexts,
255 .resume_contexts = gr_gk20a_resume_contexts, 255 .resume_contexts = gr_gk20a_resume_contexts,
256 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, 256 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
257 .fuse_override = gm20b_gr_fuse_override,
258 .init_sm_id_table = gr_gk20a_init_sm_id_table, 257 .init_sm_id_table = gr_gk20a_init_sm_id_table,
259 .load_smid_config = gr_gm20b_load_smid_config, 258 .load_smid_config = gr_gm20b_load_smid_config,
260 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, 259 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 0c431385..5771e6e4 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -300,7 +300,6 @@ static const struct gpu_ops gp106_ops = {
300 .suspend_contexts = gr_gp10b_suspend_contexts, 300 .suspend_contexts = gr_gp10b_suspend_contexts,
301 .resume_contexts = gr_gk20a_resume_contexts, 301 .resume_contexts = gr_gk20a_resume_contexts,
302 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, 302 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
303 .fuse_override = gp10b_gr_fuse_override,
304 .init_sm_id_table = gr_gk20a_init_sm_id_table, 303 .init_sm_id_table = gr_gk20a_init_sm_id_table,
305 .load_smid_config = gr_gp10b_load_smid_config, 304 .load_smid_config = gr_gp10b_load_smid_config,
306 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, 305 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 66d48e6a..2fd393bd 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -2291,45 +2291,6 @@ int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
2291 2291
2292 return 0; 2292 return 0;
2293} 2293}
2294int gp10b_gr_fuse_override(struct gk20a *g)
2295{
2296 struct device_node *np = dev_from_gk20a(g)->of_node;
2297 u32 *fuses;
2298 int count, i;
2299
2300 if (!np) /* may be pcie device */
2301 return 0;
2302
2303 count = of_property_count_elems_of_size(np, "fuse-overrides", 8);
2304 if (count <= 0)
2305 return count;
2306
2307 fuses = nvgpu_kmalloc(g, sizeof(u32) * count * 2);
2308 if (!fuses)
2309 return -ENOMEM;
2310 of_property_read_u32_array(np, "fuse-overrides", fuses, count * 2);
2311 for (i = 0; i < count; i++) {
2312 u32 fuse, value;
2313
2314 fuse = fuses[2 * i];
2315 value = fuses[2 * i + 1];
2316 switch (fuse) {
2317 case GM20B_FUSE_OPT_TPC_DISABLE:
2318 gm20b_gr_tpc_disable_override(g, value);
2319 break;
2320 case GP10B_FUSE_OPT_ECC_EN:
2321 g->gr.t18x.fecs_feature_override_ecc_val = value;
2322 break;
2323 default:
2324 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
2325 break;
2326 }
2327 }
2328
2329 nvgpu_kfree(g, fuses);
2330
2331 return 0;
2332}
2333 2294
2334int gr_gp10b_init_preemption_state(struct gk20a *g) 2295int gr_gp10b_init_preemption_state(struct gk20a *g)
2335{ 2296{
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a54a3297..757eae04 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -263,7 +263,6 @@ static const struct gpu_ops gp10b_ops = {
263 .suspend_contexts = gr_gp10b_suspend_contexts, 263 .suspend_contexts = gr_gp10b_suspend_contexts,
264 .resume_contexts = gr_gk20a_resume_contexts, 264 .resume_contexts = gr_gk20a_resume_contexts,
265 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, 265 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
266 .fuse_override = gp10b_gr_fuse_override,
267 .init_sm_id_table = gr_gk20a_init_sm_id_table, 266 .init_sm_id_table = gr_gk20a_init_sm_id_table,
268 .load_smid_config = gr_gp10b_load_smid_config, 267 .load_smid_config = gr_gp10b_load_smid_config,
269 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, 268 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
index 05295fa0..fd89e23c 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -150,7 +150,6 @@ static const struct gpu_ops vgpu_gm20b_ops = {
150 .suspend_contexts = vgpu_gr_suspend_contexts, 150 .suspend_contexts = vgpu_gr_suspend_contexts,
151 .resume_contexts = vgpu_gr_resume_contexts, 151 .resume_contexts = vgpu_gr_resume_contexts,
152 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, 152 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
153 .fuse_override = gm20b_gr_fuse_override,
154 .init_sm_id_table = gr_gk20a_init_sm_id_table, 153 .init_sm_id_table = gr_gk20a_init_sm_id_table,
155 .load_smid_config = gr_gm20b_load_smid_config, 154 .load_smid_config = gr_gm20b_load_smid_config,
156 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, 155 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 04fb286a..fcb05937 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -163,7 +163,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
163 .suspend_contexts = vgpu_gr_suspend_contexts, 163 .suspend_contexts = vgpu_gr_suspend_contexts,
164 .resume_contexts = vgpu_gr_resume_contexts, 164 .resume_contexts = vgpu_gr_resume_contexts,
165 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, 165 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
166 .fuse_override = gp10b_gr_fuse_override,
167 .init_sm_id_table = gr_gk20a_init_sm_id_table, 166 .init_sm_id_table = gr_gk20a_init_sm_id_table,
168 .load_smid_config = gr_gp10b_load_smid_config, 167 .load_smid_config = gr_gp10b_load_smid_config,
169 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, 168 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,