diff options
author | Tejal Kudav <tkudav@nvidia.com> | 2018-08-21 03:44:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-27 03:53:24 -0400 |
commit | 14949fbad615ef55adf08c39fd7614d1cbd4109e (patch) | |
tree | f35d77e2493ed4e641635adcec61a9bf3e9edeb8 | |
parent | bfe65407bde2b5d0776724301e215c6553c989f3 (diff) |
gpu: nvgpu: Remove NVHSCLK coreclk programming
top_nvhsclk_ctrl_e_clk_core and top_nvhsclk_ctrl_swap_clk_core
default to values 1 and 0 respectively on reset.
We need not explicitly program them to same values.
JIRA NVGPU-966
Change-Id: I71976c73d74cf81184c79ac9a23e01d26c31be42
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803639
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index e32b303d..df948301 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1485,12 +1485,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1485 | 1485 | ||
1486 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | 1486 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), |
1487 | top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); | 1487 | top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); |
1488 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_core_m(), | ||
1489 | top_nvhsclk_ctrl_e_clk_core_f(0x1)); | ||
1490 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | 1488 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), |
1491 | top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); | 1489 | top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); |
1492 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_core_m(), | ||
1493 | top_nvhsclk_ctrl_swap_clk_core_f(0x0)); | ||
1494 | 1490 | ||
1495 | gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); | 1491 | gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); |
1496 | 1492 | ||