gpu: nvgpu: gk20a, gm20b headers

update headers from latest gen_register/ip_check info

Change-Id: Iae892ab7138e7bba4abc821b9d7893e768647daa
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/399382

6 files changed, 163 insertions, 123 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
index e2a4f2f2..747566f0 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
@@ -94,10 +94,6 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
 {
         return 0x7 << 0;
 }
-static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r)
-{
-        return (r >> 0) & 0x7;
-}
 static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
         return 0x0;
@@ -106,18 +102,14 @@ static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
         return 0x7 << 3;
 }
-static inline u32 ctxsw_prog_main_image_pm_smpc_mode_v(u32 r)
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
 {
-        return (r >> 3) & 0x7;
+        return 0x8;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
 {
         return 0x0;
 }
-static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
-{
-        return 0x8;
-}
 static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
 {
         return 0x0000002c;
@@ -138,46 +130,6 @@ static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
 {
         return 0x600dc0de;
 }
-static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
-{
-        return 0x000000a0;
-}
-static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
-{
-        return 0x0;
-}
-static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_none_f(void)
-{
-        return 0x1;
-}
-static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
-{
-        return 0x2;
-}
-static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
-{
-        return 0x000000a4;
-}
-static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
-{
-        return 0x000000a8;
-}
-static inline u32 ctxsw_prog_main_image_misc_options_o(void)
-{
-        return 0x0000003c;
-}
-static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
-{
-        return 0x1 << 3;
-}
-static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
-{
-        return 0x0;
-}
-static inline u32 ctxsw_prog_main_image_misc_options_verif_features_enabled_f(void)
-{
-        return 0x8;
-}
 static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
 {
         return 0x0000000c;
@@ -242,4 +194,48 @@ static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void)
 {
         return 0x00000004;
 }
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003c;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
index 5ebb8365..83e7d776 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
@@ -130,6 +130,22 @@ static inline u32 fifo_eng_timeslice_enable_true_f(void)
 {
         return 0x10000000;
 }
+static inline u32 fifo_eng_timeout_r(void)
+{
+        return 0x00002a0c;
+}
+static inline u32 fifo_eng_timeout_period_max_f(void)
+{
+        return 0x7fffffff;
+}
+static inline u32 fifo_eng_timeout_detection_enabled_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 fifo_eng_timeout_detection_disabled_f(void)
+{
+        return 0x0;
+}
 static inline u32 fifo_pb_timeslice_r(u32 i)
 {
         return 0x00002350 + i*4;
@@ -350,30 +366,6 @@ static inline u32 fifo_pb_timeout_detection_enabled_f(void)
 {
         return 0x80000000;
 }
-static inline u32 fifo_eng_timeout_r(void)
-{
-        return 0x00002a0c;
-}
-static inline u32 fifo_eng_timeout_period_m(void)
-{
-        return 0x7fffffff << 0;
-}
-static inline u32 fifo_eng_timeout_period_max_f(void)
-{
-        return 0x7fffffff;
-}
-static inline u32 fifo_eng_timeout_detection_m(void)
-{
-        return 0x1 << 31;
-}
-static inline u32 fifo_eng_timeout_detection_enabled_f(void)
-{
-        return 0x80000000;
-}
-static inline u32 fifo_eng_timeout_detection_disabled_f(void)
-{
-        return 0x0;
-}
 static inline u32 fifo_error_sched_disable_r(void)
 {
         return 0x0000262c;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index fad8d3a6..6fba0b46 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -98,6 +98,18 @@ static inline u32 gr_intr_illegal_notify_reset_f(void)
 {
         return 0x40;
 }
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100;
+}
 static inline u32 gr_intr_illegal_class_pending_f(void)
 {
         return 0x20;
@@ -130,14 +142,6 @@ static inline u32 gr_intr_exception_reset_f(void)
 {
         return 0x200000;
 }
-static inline u32 gr_intr_firmware_method_pending_f(void)
-{
-        return 0x100;
-}
-static inline u32 gr_intr_firmware_method_reset_f(void)
-{
-        return 0x100;
-}
 static inline u32 gr_fecs_intr_r(void)
 {
         return 0x00400144;
@@ -258,7 +262,7 @@ static inline u32 gr_status_fe_method_lower_idle_v(void)
 {
         return 0x00000000;
 }
-static inline u32 gr_status_fe_method_fe_gi_v(u32 r)
+static inline u32 gr_status_fe_gi_v(u32 r)
 {
         return (r >> 21) & 0x1;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h
index 1692bb54..479db499 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h
@@ -110,14 +110,6 @@ static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
 {
         return 0x1000000;
 }
-static inline u32 mc_intr_mask_1_r(void)
-{
-        return 0x00000644;
-}
-static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
-{
-        return 0x1000000;
-}
 static inline u32 mc_intr_en_0_r(void)
 {
         return 0x00000140;
@@ -130,6 +122,30 @@ static inline u32 mc_intr_en_0_inta_hardware_f(void)
 {
         return 0x1;
 }
+static inline u32 mc_intr_mask_1_r(void)
+{
+        return 0x00000644;
+}
+static inline u32 mc_intr_mask_1_pmu_s(void)
+{
+        return 1;
+}
+static inline u32 mc_intr_mask_1_pmu_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_m(void)
+{
+        return 0x1 << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_v(u32 r)
+{
+        return (r >> 24) & 0x1;
+}
+static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
+{
+        return 0x1000000;
+}
 static inline u32 mc_intr_en_1_r(void)
 {
         return 0x00000144;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_pbdma_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_pbdma_gk20a.h
index df1a6d48..60e83122 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_pbdma_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_pbdma_gk20a.h
@@ -146,38 +146,6 @@ static inline u32 pbdma_formats_mp_fermi0_f(void)
 {
         return 0x0;
 }
-static inline u32 pbdma_syncpointa_r(u32 i)
-{
-        return 0x000400a4 + i*8192;
-}
-static inline u32 pbdma_syncpointa_payload_v(u32 r)
-{
-        return (r >> 0) & 0xffffffff;
-}
-static inline u32 pbdma_syncpointb_r(u32 i)
-{
-        return 0x000400a8 + i*8192;
-}
-static inline u32 pbdma_syncpointb_op_v(u32 r)
-{
-        return (r >> 0) & 0x3;
-}
-static inline u32 pbdma_syncpointb_op_wait_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
-{
-        return (r >> 4) & 0x1;
-}
-static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
-{
-        return 0x00000001;
-}
-static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
-{
-        return (r >> 8) & 0xff;
-}
 static inline u32 pbdma_pb_header_r(u32 i)
 {
         return 0x00040084 + i*8192;
@@ -466,4 +434,36 @@ static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008;
 }
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4 + i*8192;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8 + i*8192;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8) & 0xff;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h
index e403abdb..c64184cb 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h
@@ -434,4 +434,36 @@ static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008;
 }
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4 + i*8192;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8 + i*8192;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8) & 0xff;
+}
 #endif