diff options
author | Tejal Kudav <tkudav@nvidia.com> | 2018-06-03 08:56:37 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | 097b42f088c52b2b15c50c4fd6ae2cb670d2d6c3 (patch) | |
tree | 98b72b3c801ecc6a03e68f539141daf7d02a96e0 | |
parent | 118b7fb891e976d7f5e8845b08d90f33d7e3043e (diff) |
gpu: nvgpu: nvlink: Add HAL for SW WAR
Workaround of setting SAFE_CTR_INIT on NVLINK (WAR for Bug 1888034)
is needed only on nvlink 2.0. Add HAL to avoid running the WAR on
future chips.
Bug 2006692
Change-Id: I85fb90ea5ce7b848946f2c362e7a952787cc1261
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1738401
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.h | 1 |
4 files changed, 18 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2dc62716..8b7315f6 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1201,6 +1201,7 @@ struct gpu_ops { | |||
1201 | int (*minion_data_ready_en)(struct gk20a *g, | 1201 | int (*minion_data_ready_en)(struct gk20a *g, |
1202 | unsigned long link_mask, bool sync); | 1202 | unsigned long link_mask, bool sync); |
1203 | void (*get_connected_link_mask)(u32 *link_mask); | 1203 | void (*get_connected_link_mask)(u32 *link_mask); |
1204 | void (*set_sw_war)(struct gk20a *g, u32 link_id); | ||
1204 | /* API */ | 1205 | /* API */ |
1205 | int (*link_early_init)(struct gk20a *g, unsigned long mask); | 1206 | int (*link_early_init)(struct gk20a *g, unsigned long mask); |
1206 | u32 (*link_get_mode)(struct gk20a *g, u32 link_id); | 1207 | u32 (*link_get_mode)(struct gk20a *g, u32 link_id); |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 92900421..b3d97f89 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -844,6 +844,7 @@ static const struct gpu_ops gv100_ops = { | |||
844 | .setup_pll = gv100_nvlink_setup_pll, | 844 | .setup_pll = gv100_nvlink_setup_pll, |
845 | .minion_data_ready_en = gv100_nvlink_minion_data_ready_en, | 845 | .minion_data_ready_en = gv100_nvlink_minion_data_ready_en, |
846 | .get_connected_link_mask = gv100_nvlink_get_connected_link_mask, | 846 | .get_connected_link_mask = gv100_nvlink_get_connected_link_mask, |
847 | .set_sw_war = gv100_nvlink_set_sw_war, | ||
847 | /* API */ | 848 | /* API */ |
848 | .link_early_init = gv100_nvlink_link_early_init, | 849 | .link_early_init = gv100_nvlink_link_early_init, |
849 | .link_get_state = gv100_nvlink_link_get_state, | 850 | .link_get_state = gv100_nvlink_link_get_state, |
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index e85b5a93..c328dd70 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1625,23 +1625,28 @@ static int gv100_nvlink_enable_links_pre_top(struct gk20a *g, u32 links) | |||
1625 | return -EINVAL; | 1625 | return -EINVAL; |
1626 | } | 1626 | } |
1627 | 1627 | ||
1628 | void gv100_nvlink_set_sw_war(struct gk20a *g, u32 link_id) | ||
1629 | { | ||
1630 | u32 reg; | ||
1631 | |||
1632 | /* WAR for HW bug 1888034 */ | ||
1633 | reg = DLPL_REG_RD32(g, link_id, nvl_sl0_safe_ctrl2_tx_r()); | ||
1634 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_init_m(), | ||
1635 | nvl_sl0_safe_ctrl2_tx_ctr_init_init_f()); | ||
1636 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(), | ||
1637 | nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f()); | ||
1638 | DLPL_REG_WR32(g, link_id, nvl_sl0_safe_ctrl2_tx_r(), reg); | ||
1639 | } | ||
1640 | |||
1628 | static int gv100_nvlink_enable_links_post_top(struct gk20a *g, u32 links) | 1641 | static int gv100_nvlink_enable_links_post_top(struct gk20a *g, u32 links) |
1629 | { | 1642 | { |
1630 | u32 link_id; | 1643 | u32 link_id; |
1631 | unsigned long enabled_links = (links & g->nvlink.enabled_links) & | 1644 | unsigned long enabled_links = (links & g->nvlink.enabled_links) & |
1632 | ~g->nvlink.initialized_links; | 1645 | ~g->nvlink.initialized_links; |
1633 | u32 reg; | ||
1634 | 1646 | ||
1635 | for_each_set_bit(link_id, &enabled_links, 32) { | 1647 | for_each_set_bit(link_id, &enabled_links, 32) { |
1636 | 1648 | if (g->ops.nvlink.set_sw_war) | |
1637 | /* WAR for HW bug 1888034 */ | 1649 | g->ops.nvlink.set_sw_war(g, link_id); |
1638 | reg = DLPL_REG_RD32(g, link_id, nvl_sl0_safe_ctrl2_tx_r()); | ||
1639 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_init_m(), | ||
1640 | nvl_sl0_safe_ctrl2_tx_ctr_init_init_f()); | ||
1641 | reg = set_field(reg, nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(), | ||
1642 | nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f()); | ||
1643 | DLPL_REG_WR32(g, link_id, nvl_sl0_safe_ctrl2_tx_r(), reg); | ||
1644 | |||
1645 | gv100_nvlink_initialize_tlc(g, link_id); | 1650 | gv100_nvlink_initialize_tlc(g, link_id); |
1646 | gv100_nvlink_initialize_nvlipt(g, link_id); | 1651 | gv100_nvlink_initialize_nvlipt(g, link_id); |
1647 | gv100_nvlink_enable_link_intr(g, link_id, true); | 1652 | gv100_nvlink_enable_link_intr(g, link_id, true); |
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h index d9a4b073..6310af28 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h | |||
@@ -37,6 +37,7 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask); | |||
37 | int gv100_nvlink_minion_data_ready_en(struct gk20a *g, | 37 | int gv100_nvlink_minion_data_ready_en(struct gk20a *g, |
38 | unsigned long link_mask, bool sync); | 38 | unsigned long link_mask, bool sync); |
39 | void gv100_nvlink_get_connected_link_mask(u32 *link_mask); | 39 | void gv100_nvlink_get_connected_link_mask(u32 *link_mask); |
40 | void gv100_nvlink_set_sw_war(struct gk20a *g, u32 link_id); | ||
40 | /* API */ | 41 | /* API */ |
41 | int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask); | 42 | int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask); |
42 | u32 gv100_nvlink_link_get_mode(struct gk20a *g, u32 link_id); | 43 | u32 gv100_nvlink_link_get_mode(struct gk20a *g, u32 link_id); |