gpu: nvgpu: switch gk20a nonstall ops to #defines

Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.

Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.

The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.

JIRA NVGPU-650

Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

9 files changed, 23 insertions, 25 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 5aae0613..0248b0ca 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -88,9 +88,9 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         return;
 }
 
-int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 {
-        int ops = 0;
+        u32 ops = 0;
         u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
 
         nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
@@ -98,8 +98,8 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
                 gk20a_writel(g, ce2_intr_status_r(),
                         ce2_nonblockpipe_isr(g, ce2_intr));
-                ops |= (gk20a_nonstall_ops_wakeup_semaphore |
-                        gk20a_nonstall_ops_post_events);
+                ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+                        GK20A_NONSTALL_OPS_POST_EVENTS);
         }
         return ops;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
index 1a102070..19a169da 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
@@ -3,7 +3,7 @@
  *
  * GK20A graphics copy engine (gr host)
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,7 +30,7 @@
 #include "tsg_gk20a.h"
 
 void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
-int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 
 /* CE command utility macros */
 #define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 4628de4f..20fb51e7 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2720,7 +2720,7 @@ void gk20a_fifo_isr(struct gk20a *g)
         return;
 }
 
-enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g)
+u32 gk20a_fifo_nonstall_isr(struct gk20a *g)
 {
         u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r());
         u32 clear_intr = 0;
@@ -2732,7 +2732,7 @@ enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g)
 
         gk20a_writel(g, fifo_intr_0_r(), clear_intr);
 
-        return gk20a_nonstall_ops_wakeup_semaphore;
+        return GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE;
 }
 
 void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 120950c1..77030c94 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -31,7 +31,6 @@
 
 struct gk20a_debug_output;
 struct mmu_fault_info;
-enum gk20a_nonstall_ops;
 
 enum {
         NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0,
@@ -229,7 +228,7 @@ int gk20a_init_fifo_support(struct gk20a *g);
 int gk20a_init_fifo_setup_hw(struct gk20a *g);
 
 void gk20a_fifo_isr(struct gk20a *g);
-enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g);
+u32 gk20a_fifo_nonstall_isr(struct gk20a *g);
 
 int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid);
 int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5300f7dd..cf202f14 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -207,7 +207,7 @@ struct gpu_ops {
         } ltc;
         struct {
                 void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
-                int (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
+                u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
                 u32 (*get_num_pce)(struct gk20a *g);
         } ce2;
         struct {
@@ -1668,10 +1668,8 @@ struct gk20a_cyclestate_buffer_elem {
 };
 
 /* operations that will need to be executed on non stall workqueue */
-enum gk20a_nonstall_ops {
-        gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */
-        gk20a_nonstall_ops_post_events = BIT(1),
-};
+#define GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE     BIT32(0)
+#define GK20A_NONSTALL_OPS_POST_EVENTS          BIT32(1)
 
 /* register accessors */
 void __nvgpu_check_gpu_state(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 90643971..f2b083d7 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6101,8 +6101,8 @@ u32 gk20a_gr_nonstall_isr(struct gk20a *g)
                 /* Clear the interrupt */
                 gk20a_writel(g, gr_intr_nonstall_r(),
                         gr_intr_nonstall_trap_pending_f());
-                ops |= (u32)(gk20a_nonstall_ops_wakeup_semaphore |
-                        gk20a_nonstall_ops_post_events);
+                ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+                        GK20A_NONSTALL_OPS_POST_EVENTS);
         }
         return ops;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 26084bd6..a0eae127 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -319,9 +319,10 @@ void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops)
 {
         bool semaphore_wakeup, post_events;
 
-        semaphore_wakeup = (((ops & (u32)gk20a_nonstall_ops_wakeup_semaphore) != 0U) ?
+        semaphore_wakeup =
+                (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
                                         true : false);
-        post_events = (((ops & (u32)gk20a_nonstall_ops_post_events) != 0U) ?
+        post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ?
                                         true: false);
 
         if (semaphore_wakeup) {
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
index 048a9ba0..76179b78 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
@@ -61,9 +61,9 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         return;
 }
 
-int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 {
-        int ops = 0;
+        u32 ops = 0;
         u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
 
         nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
@@ -71,8 +71,8 @@ int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) {
                 gk20a_writel(g, ce_intr_status_r(inst_id),
                         ce_intr_status_nonblockpipe_pending_f());
-                ops |= (gk20a_nonstall_ops_wakeup_semaphore |
-                        gk20a_nonstall_ops_post_events);
+                ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+                        GK20A_NONSTALL_OPS_POST_EVENTS);
         }
 
         return ops;
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 7b747751..fbf5e6f8 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * Pascal GPU series Copy Engine.
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,6 @@
 #include "gk20a/tsg_gk20a.h"
 
 void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
-int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 
 #endif /*__CE2_GP10B_H__*/