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authorSourab Gupta <sourabg@nvidia.com>2018-05-04 02:13:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-18 02:34:32 -0400
commitfc3ac7d2ae2c7cb856fff58af77bb8d453ff5473 (patch)
tree412d3ebe84b7ba469b6ff4d49936c4d4b8920c18
parent6a43e51ee362bbf61ca35cda75f31ed3f01862ed (diff)
gpu: nvgpu: move clk_arb.c to common code
Now that clk_arb.c is free of Linux'isms, move it to the clk/ directory. Jira VQRM-741 Change-Id: I53298c76f834322aa586781cdfd2e6031f4826a1 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709651 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/Makefile4
-rw-r--r--drivers/gpu/nvgpu/clk/clk_arb.c (renamed from drivers/gpu/nvgpu/common/linux/clk_arb.c)31
-rw-r--r--drivers/gpu/nvgpu/common/linux/clk_arb_linux.h163
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c1
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/clk_arb.h120
5 files changed, 140 insertions, 179 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 8f8f8dc8..599e97e2 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -29,6 +29,7 @@ nvgpu-y := \
29 common/linux/ioctl_channel.o \ 29 common/linux/ioctl_channel.o \
30 common/linux/ioctl_tsg.o \ 30 common/linux/ioctl_tsg.o \
31 common/linux/ioctl_dbg.o \ 31 common/linux/ioctl_dbg.o \
32 common/linux/ioctl_clk_arb.o \
32 common/linux/log.o \ 33 common/linux/log.o \
33 common/linux/cond.o \ 34 common/linux/cond.o \
34 common/linux/nvgpu_mem.o \ 35 common/linux/nvgpu_mem.o \
@@ -282,8 +283,7 @@ nvgpu-y += \
282 clk/clk_domain.o \ 283 clk/clk_domain.o \
283 clk/clk_prog.o \ 284 clk/clk_prog.o \
284 clk/clk_vf_point.o \ 285 clk/clk_vf_point.o \
285 common/linux/ioctl_clk_arb.o \ 286 clk/clk_arb.o \
286 common/linux/clk_arb.o \
287 clk/clk_freq_controller.o \ 287 clk/clk_freq_controller.o \
288 perf/vfe_var.o \ 288 perf/vfe_var.o \
289 perf/vfe_equ.o \ 289 perf/vfe_equ.o \
diff --git a/drivers/gpu/nvgpu/common/linux/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
index 2a6278e8..fdf17408 100644
--- a/drivers/gpu/nvgpu/common/linux/clk_arb.c
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -1,17 +1,23 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * License version 2, as published by the Free Software Foundation, and 5 * copy of this software and associated documentation files (the "Software"),
6 * may be copied, distributed, and modified under those terms. 6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
7 * 10 *
8 * This program is distributed in the hope that it will be useful, 11 * The above copyright notice and this permission notice shall be included in
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * all copies or substantial portions of the Software.
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 * 13 *
13 * You should have received a copy of the GNU General Public License 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
15 */ 21 */
16 22
17#include <nvgpu/bitops.h> 23#include <nvgpu/bitops.h>
@@ -28,7 +34,6 @@
28 34
29#include "gk20a/gk20a.h" 35#include "gk20a/gk20a.h"
30#include "clk/clk.h" 36#include "clk/clk.h"
31#include "clk_arb_linux.h"
32#include "pstate/pstate.h" 37#include "pstate/pstate.h"
33#include "lpwr/lpwr.h" 38#include "lpwr/lpwr.h"
34#include "volt/volt.h" 39#include "volt/volt.h"
@@ -1198,7 +1203,7 @@ void nvgpu_clk_arb_worker_enqueue(struct gk20a *g,
1198/** 1203/**
1199 * Initialize the clk arb worker's metadata and start the background thread. 1204 * Initialize the clk arb worker's metadata and start the background thread.
1200 */ 1205 */
1201int nvgpu_clk_arb_worker_init(struct gk20a *g) 1206static int nvgpu_clk_arb_worker_init(struct gk20a *g)
1202{ 1207{
1203 int err; 1208 int err;
1204 1209
@@ -1380,7 +1385,7 @@ void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm)
1380 nvgpu_clk_arb_worker_enqueue(g, &arb->update_arb_work_item); 1385 nvgpu_clk_arb_worker_enqueue(g, &arb->update_arb_work_item);
1381} 1386}
1382 1387
1383void nvgpu_clk_arb_worker_deinit(struct gk20a *g) 1388static void nvgpu_clk_arb_worker_deinit(struct gk20a *g)
1384{ 1389{
1385 nvgpu_mutex_acquire(&g->clk_arb_worker.start_lock); 1390 nvgpu_mutex_acquire(&g->clk_arb_worker.start_lock);
1386 nvgpu_thread_stop(&g->clk_arb_worker.poll_task); 1391 nvgpu_thread_stop(&g->clk_arb_worker.poll_task);
diff --git a/drivers/gpu/nvgpu/common/linux/clk_arb_linux.h b/drivers/gpu/nvgpu/common/linux/clk_arb_linux.h
deleted file mode 100644
index 464590d5..00000000
--- a/drivers/gpu/nvgpu/common/linux/clk_arb_linux.h
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __NVGPU_CLK_ARB_LINUX_H__
18#define __NVGPU_CLK_ARB_LINUX_H__
19
20#include <nvgpu/types.h>
21#include <nvgpu/bitops.h>
22#include <nvgpu/lock.h>
23#include <nvgpu/kmem.h>
24#include <nvgpu/atomic.h>
25#include <nvgpu/bug.h>
26#include <nvgpu/kref.h>
27#include <nvgpu/log.h>
28#include <nvgpu/barrier.h>
29#include <nvgpu/cond.h>
30#include <nvgpu/list.h>
31
32#include "gk20a/gk20a.h"
33#include "clk/clk.h"
34#include "pstate/pstate.h"
35#include "lpwr/lpwr.h"
36#include "volt/volt.h"
37
38/*
39 * The defines here should finally move to clk_arb.h, once these are
40 * refactored to be free of Linux fields.
41 */
42
43enum clk_arb_work_item_type {
44 CLK_ARB_WORK_UPDATE_VF_TABLE,
45 CLK_ARB_WORK_UPDATE_ARB
46};
47
48struct nvgpu_clk_arb_work_item {
49 enum clk_arb_work_item_type item_type;
50 struct nvgpu_clk_arb *arb;
51 struct nvgpu_list_node worker_item;
52};
53
54struct nvgpu_clk_arb {
55 struct nvgpu_spinlock sessions_lock;
56 struct nvgpu_spinlock users_lock;
57 struct nvgpu_spinlock requests_lock;
58
59 struct nvgpu_mutex pstate_lock;
60 struct nvgpu_list_node users;
61 struct nvgpu_list_node sessions;
62 struct nvgpu_list_node requests;
63
64 struct gk20a *g;
65 int status;
66
67 struct nvgpu_clk_arb_target actual_pool[2];
68 struct nvgpu_clk_arb_target *actual;
69
70 u16 gpc2clk_default_mhz;
71 u16 mclk_default_mhz;
72 u32 voltuv_actual;
73
74 u16 gpc2clk_min, gpc2clk_max;
75 u16 mclk_min, mclk_max;
76
77 struct nvgpu_clk_arb_work_item update_vf_table_work_item;
78 struct nvgpu_clk_arb_work_item update_arb_work_item;
79
80 struct nvgpu_cond request_wq;
81
82 struct nvgpu_clk_vf_table *current_vf_table;
83 struct nvgpu_clk_vf_table vf_table_pool[2];
84 u32 vf_table_index;
85
86 u16 *mclk_f_points;
87 nvgpu_atomic_t req_nr;
88
89 u32 mclk_f_numpoints;
90 u16 *gpc2clk_f_points;
91 u32 gpc2clk_f_numpoints;
92
93 nvgpu_atomic64_t alarm_mask;
94 struct nvgpu_clk_notification_queue notification_queue;
95
96#ifdef CONFIG_DEBUG_FS
97 struct nvgpu_clk_arb_debug debug_pool[2];
98 struct nvgpu_clk_arb_debug *debug;
99 bool debugfs_set;
100#endif
101};
102
103struct nvgpu_clk_dev {
104 struct nvgpu_clk_session *session;
105 union {
106 struct nvgpu_list_node link;
107 struct nvgpu_list_node node;
108 };
109 struct nvgpu_cond readout_wq;
110 nvgpu_atomic_t poll_mask;
111 u16 gpc2clk_target_mhz;
112 u16 mclk_target_mhz;
113 u32 alarms_reported;
114 nvgpu_atomic_t enabled_mask;
115 struct nvgpu_clk_notification_queue queue;
116 u32 arb_queue_head;
117 struct nvgpu_ref refcount;
118};
119
120struct nvgpu_clk_session {
121 bool zombie;
122 struct gk20a *g;
123 struct nvgpu_ref refcount;
124 struct nvgpu_list_node link;
125 struct nvgpu_list_node targets;
126
127 struct nvgpu_spinlock session_lock;
128 struct nvgpu_clk_arb_target target_pool[2];
129 struct nvgpu_clk_arb_target *target;
130};
131
132static inline struct nvgpu_clk_session *
133nvgpu_clk_session_from_link(struct nvgpu_list_node *node)
134{
135 return (struct nvgpu_clk_session *)
136 ((uintptr_t)node - offsetof(struct nvgpu_clk_session, link));
137};
138
139static inline struct nvgpu_clk_dev *
140nvgpu_clk_dev_from_node(struct nvgpu_list_node *node)
141{
142 return (struct nvgpu_clk_dev *)
143 ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, node));
144};
145
146static inline struct nvgpu_clk_dev *
147nvgpu_clk_dev_from_link(struct nvgpu_list_node *node)
148{
149 return (struct nvgpu_clk_dev *)
150 ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, link));
151};
152
153static inline struct nvgpu_clk_arb_work_item *
154nvgpu_clk_arb_work_item_from_worker_item(struct nvgpu_list_node *node)
155{
156 return (struct nvgpu_clk_arb_work_item *)
157 ((uintptr_t)node - offsetof(struct nvgpu_clk_arb_work_item, worker_item));
158};
159
160void nvgpu_clk_arb_worker_enqueue(struct gk20a *g,
161 struct nvgpu_clk_arb_work_item *work_item);
162#endif /* __NVGPU_CLK_ARB_LINUX_H__ */
163
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
index 3ab8cf9e..e4ac68a3 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
@@ -38,7 +38,6 @@
38 38
39#include "gk20a/gk20a.h" 39#include "gk20a/gk20a.h"
40#include "clk/clk.h" 40#include "clk/clk.h"
41#include "clk_arb_linux.h"
42#include "pstate/pstate.h" 41#include "pstate/pstate.h"
43#include "lpwr/lpwr.h" 42#include "lpwr/lpwr.h"
44#include "volt/volt.h" 43#include "volt/volt.h"
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
index a5f8a7d5..c9a32cf1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
@@ -151,6 +151,126 @@ struct nvgpu_clk_arb_target {
151 u32 pstate; 151 u32 pstate;
152}; 152};
153 153
154enum clk_arb_work_item_type {
155 CLK_ARB_WORK_UPDATE_VF_TABLE,
156 CLK_ARB_WORK_UPDATE_ARB
157};
158
159struct nvgpu_clk_arb_work_item {
160 enum clk_arb_work_item_type item_type;
161 struct nvgpu_clk_arb *arb;
162 struct nvgpu_list_node worker_item;
163};
164
165struct nvgpu_clk_arb {
166 struct nvgpu_spinlock sessions_lock;
167 struct nvgpu_spinlock users_lock;
168 struct nvgpu_spinlock requests_lock;
169
170 struct nvgpu_mutex pstate_lock;
171 struct nvgpu_list_node users;
172 struct nvgpu_list_node sessions;
173 struct nvgpu_list_node requests;
174
175 struct gk20a *g;
176 int status;
177
178 struct nvgpu_clk_arb_target actual_pool[2];
179 struct nvgpu_clk_arb_target *actual;
180
181 u16 gpc2clk_default_mhz;
182 u16 mclk_default_mhz;
183 u32 voltuv_actual;
184
185 u16 gpc2clk_min, gpc2clk_max;
186 u16 mclk_min, mclk_max;
187
188 struct nvgpu_clk_arb_work_item update_vf_table_work_item;
189 struct nvgpu_clk_arb_work_item update_arb_work_item;
190
191 struct nvgpu_cond request_wq;
192
193 struct nvgpu_clk_vf_table *current_vf_table;
194 struct nvgpu_clk_vf_table vf_table_pool[2];
195 u32 vf_table_index;
196
197 u16 *mclk_f_points;
198 nvgpu_atomic_t req_nr;
199
200 u32 mclk_f_numpoints;
201 u16 *gpc2clk_f_points;
202 u32 gpc2clk_f_numpoints;
203
204 nvgpu_atomic64_t alarm_mask;
205 struct nvgpu_clk_notification_queue notification_queue;
206
207#ifdef CONFIG_DEBUG_FS
208 struct nvgpu_clk_arb_debug debug_pool[2];
209 struct nvgpu_clk_arb_debug *debug;
210 bool debugfs_set;
211#endif
212};
213
214struct nvgpu_clk_dev {
215 struct nvgpu_clk_session *session;
216 union {
217 struct nvgpu_list_node link;
218 struct nvgpu_list_node node;
219 };
220 struct nvgpu_cond readout_wq;
221 nvgpu_atomic_t poll_mask;
222 u16 gpc2clk_target_mhz;
223 u16 mclk_target_mhz;
224 u32 alarms_reported;
225 nvgpu_atomic_t enabled_mask;
226 struct nvgpu_clk_notification_queue queue;
227 u32 arb_queue_head;
228 struct nvgpu_ref refcount;
229};
230
231struct nvgpu_clk_session {
232 bool zombie;
233 struct gk20a *g;
234 struct nvgpu_ref refcount;
235 struct nvgpu_list_node link;
236 struct nvgpu_list_node targets;
237
238 struct nvgpu_spinlock session_lock;
239 struct nvgpu_clk_arb_target target_pool[2];
240 struct nvgpu_clk_arb_target *target;
241};
242
243static inline struct nvgpu_clk_session *
244nvgpu_clk_session_from_link(struct nvgpu_list_node *node)
245{
246 return (struct nvgpu_clk_session *)
247 ((uintptr_t)node - offsetof(struct nvgpu_clk_session, link));
248};
249
250static inline struct nvgpu_clk_dev *
251nvgpu_clk_dev_from_node(struct nvgpu_list_node *node)
252{
253 return (struct nvgpu_clk_dev *)
254 ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, node));
255};
256
257static inline struct nvgpu_clk_dev *
258nvgpu_clk_dev_from_link(struct nvgpu_list_node *node)
259{
260 return (struct nvgpu_clk_dev *)
261 ((uintptr_t)node - offsetof(struct nvgpu_clk_dev, link));
262};
263
264static inline struct nvgpu_clk_arb_work_item *
265nvgpu_clk_arb_work_item_from_worker_item(struct nvgpu_list_node *node)
266{
267 return (struct nvgpu_clk_arb_work_item *)
268 ((uintptr_t)node - offsetof(struct nvgpu_clk_arb_work_item, worker_item));
269};
270
271void nvgpu_clk_arb_worker_enqueue(struct gk20a *g,
272 struct nvgpu_clk_arb_work_item *work_item);
273
154int nvgpu_clk_arb_init_arbiter(struct gk20a *g); 274int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
155 275
156int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, 276int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,