diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-11-03 03:40:02 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:59 -0400 |
commit | f82d6e9d190449b06066eff1a01700e8387eb7c2 (patch) | |
tree | ca11319c970f87cf4efd2b869eb453f7664546ba | |
parent | 7784fb18a3e9b86ea86c2eff756443c005dd3e32 (diff) |
gpu: nvgpu: Regenerate HW headers
Regenerate HW headers after adding SM debugger registers.
Change-Id: Icc47c11f8e9ff52c0cf1f3a54233fb781c2c2b67
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 64 |
3 files changed, 80 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 63ab6c9f..f87608d1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -7285,7 +7285,7 @@ void gk20a_resume_all_sms(struct gk20a *g) | |||
7285 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | 7285 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); |
7286 | 7286 | ||
7287 | /* Run trigger */ | 7287 | /* Run trigger */ |
7288 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f(); | 7288 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(); |
7289 | gk20a_writel(g, | 7289 | gk20a_writel(g, |
7290 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | 7290 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); |
7291 | } | 7291 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 65a3072c..3b16df58 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -2812,7 +2812,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | |||
2812 | } | 2812 | } |
2813 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | 2813 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) |
2814 | { | 2814 | { |
2815 | return 0x00000000; | 2815 | return 0x0; |
2816 | } | 2816 | } |
2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
2818 | { | 2818 | { |
@@ -3234,38 +3234,40 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | |||
3234 | { | 3234 | { |
3235 | return 0x00419e10; | 3235 | return 0x00419e10; |
3236 | } | 3236 | } |
3237 | 3237 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | |
3238 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r_debugger_mode_v(u32 r) | ||
3239 | { | 3238 | { |
3240 | return (r >> 0) & 0x1; | 3239 | return (v & 0x1) << 0; |
3241 | } | 3240 | } |
3242 | 3241 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | |
3243 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3244 | { | 3242 | { |
3245 | return (r >> 31) & 0x1; | 3243 | return 0x00000001; |
3246 | } | 3244 | } |
3247 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | 3245 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) |
3248 | { | 3246 | { |
3249 | return 0x1 << 31; | 3247 | return 0x1 << 31; |
3250 | } | 3248 | } |
3249 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3250 | { | ||
3251 | return (r >> 31) & 0x1; | ||
3252 | } | ||
3251 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | 3253 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) |
3252 | { | 3254 | { |
3253 | return 0x80000000; | 3255 | return 0x80000000; |
3254 | } | 3256 | } |
3255 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | 3257 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) |
3256 | { | 3258 | { |
3257 | return (r >> 30) & 0x1; | 3259 | return 0x0; |
3258 | } | 3260 | } |
3259 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3261 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3260 | { | 3262 | { |
3261 | return 0x1 << 30; | 3263 | return 0x1 << 30; |
3262 | } | 3264 | } |
3263 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f(void) | 3265 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) |
3264 | { | 3266 | { |
3265 | return 0x40000000; | 3267 | return (r >> 30) & 0x1; |
3266 | } | 3268 | } |
3267 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_f(void) | 3269 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) |
3268 | { | 3270 | { |
3269 | return 0x1; | 3271 | return 0x40000000; |
3270 | } | 3272 | } |
3271 | #endif | 3273 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 95d06cc6..0dae5896 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -2830,6 +2830,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | |||
2830 | { | 2830 | { |
2831 | return 0x80000000; | 2831 | return 0x80000000; |
2832 | } | 2832 | } |
2833 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | ||
2834 | { | ||
2835 | return 0x0; | ||
2836 | } | ||
2837 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | ||
2838 | { | ||
2839 | return 0x40000000; | ||
2840 | } | ||
2833 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 2841 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
2834 | { | 2842 | { |
2835 | return 0x0050460c; | 2843 | return 0x0050460c; |
@@ -2842,6 +2850,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) | |||
2842 | { | 2850 | { |
2843 | return 0x00000001; | 2851 | return 0x00000001; |
2844 | } | 2852 | } |
2853 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) | ||
2854 | { | ||
2855 | return 0x00419e50; | ||
2856 | } | ||
2857 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) | ||
2858 | { | ||
2859 | return 0x10; | ||
2860 | } | ||
2861 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) | ||
2862 | { | ||
2863 | return 0x20; | ||
2864 | } | ||
2865 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) | ||
2866 | { | ||
2867 | return 0x40; | ||
2868 | } | ||
2845 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 2869 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
2846 | { | 2870 | { |
2847 | return 0x00504650; | 2871 | return 0x00504650; |
@@ -3242,4 +3266,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | |||
3242 | { | 3266 | { |
3243 | return 0x004188ac; | 3267 | return 0x004188ac; |
3244 | } | 3268 | } |
3269 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | ||
3270 | { | ||
3271 | return 0x00419e10; | ||
3272 | } | ||
3273 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | ||
3274 | { | ||
3275 | return (v & 0x1) << 0; | ||
3276 | } | ||
3277 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | ||
3278 | { | ||
3279 | return 0x00000001; | ||
3280 | } | ||
3281 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | ||
3282 | { | ||
3283 | return 0x1 << 31; | ||
3284 | } | ||
3285 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3286 | { | ||
3287 | return (r >> 31) & 0x1; | ||
3288 | } | ||
3289 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | ||
3290 | { | ||
3291 | return 0x80000000; | ||
3292 | } | ||
3293 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | ||
3294 | { | ||
3295 | return 0x0; | ||
3296 | } | ||
3297 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | ||
3298 | { | ||
3299 | return 0x1 << 30; | ||
3300 | } | ||
3301 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | ||
3302 | { | ||
3303 | return (r >> 30) & 0x1; | ||
3304 | } | ||
3305 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) | ||
3306 | { | ||
3307 | return 0x40000000; | ||
3308 | } | ||
3245 | #endif | 3309 | #endif |