diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-09-14 08:48:07 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-15 15:48:22 -0400 |
commit | f720b309f1ea87a301bcb216983396f3d9c55abc (patch) | |
tree | 7776523be5dadc1a1af918e1d3f4525beadba075 | |
parent | 52f50addc6cedf57fc3d8ff06314921499fb59e3 (diff) |
gpu: nvgpu: add tsg_verify_status_faulted operation
Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as
g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100
This API will check if channel has ENG_FAULTED status set, if yes it will clear
CE method buffer in case saved out channel is same as faulted channel
We need to write 0 to method count to invalidate CE method buffer
Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100
Bug 200327095
Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 12 |
6 files changed, 65 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cc20fa43..9a2807a2 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -399,6 +399,8 @@ static const struct gpu_ops gv100_ops = { | |||
399 | .preempt_tsg = gv11b_fifo_preempt_tsg, | 399 | .preempt_tsg = gv11b_fifo_preempt_tsg, |
400 | .enable_tsg = gv11b_fifo_enable_tsg, | 400 | .enable_tsg = gv11b_fifo_enable_tsg, |
401 | .disable_tsg = gk20a_disable_tsg, | 401 | .disable_tsg = gk20a_disable_tsg, |
402 | .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, | ||
403 | .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, | ||
402 | .update_runlist = gk20a_fifo_update_runlist, | 404 | .update_runlist = gk20a_fifo_update_runlist, |
403 | .trigger_mmu_fault = NULL, | 405 | .trigger_mmu_fault = NULL, |
404 | .get_mmu_fault_info = NULL, | 406 | .get_mmu_fault_info = NULL, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1d5e593c..b4e4b875 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, | |||
1811 | else | 1811 | else |
1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; | 1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; |
1813 | } | 1813 | } |
1814 | |||
1815 | static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid) | ||
1816 | { | ||
1817 | u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); | ||
1818 | |||
1819 | return ccsr_channel_eng_faulted_v(channel) == | ||
1820 | ccsr_channel_eng_faulted_true_v(); | ||
1821 | } | ||
1822 | |||
1823 | void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch) | ||
1824 | { | ||
1825 | struct gk20a *g = ch->g; | ||
1826 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
1827 | |||
1828 | /* | ||
1829 | * If channel has FAULTED set, clear the CE method buffer | ||
1830 | * if saved out channel is same as faulted channel | ||
1831 | */ | ||
1832 | if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid)) | ||
1833 | return; | ||
1834 | |||
1835 | if (tsg->eng_method_buffers == NULL) | ||
1836 | return; | ||
1837 | |||
1838 | /* | ||
1839 | * CE method buffer format : | ||
1840 | * DWord0 = method count | ||
1841 | * DWord1 = channel id | ||
1842 | * | ||
1843 | * It is sufficient to write 0 to method count to invalidate | ||
1844 | */ | ||
1845 | if ((u32)ch->chid == | ||
1846 | nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1)) | ||
1847 | nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0); | ||
1848 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index e576714c..0cc1c7c2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -103,4 +103,6 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, | |||
103 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); | 103 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); |
104 | int gv11b_init_fifo_setup_hw(struct gk20a *g); | 104 | int gv11b_init_fifo_setup_hw(struct gk20a *g); |
105 | 105 | ||
106 | void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); | ||
107 | |||
106 | #endif | 108 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 947ac503..fcc3b91a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -432,6 +432,8 @@ static const struct gpu_ops gv11b_ops = { | |||
432 | .preempt_tsg = gv11b_fifo_preempt_tsg, | 432 | .preempt_tsg = gv11b_fifo_preempt_tsg, |
433 | .enable_tsg = gv11b_fifo_enable_tsg, | 433 | .enable_tsg = gv11b_fifo_enable_tsg, |
434 | .disable_tsg = gk20a_disable_tsg, | 434 | .disable_tsg = gk20a_disable_tsg, |
435 | .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, | ||
436 | .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, | ||
435 | .update_runlist = gk20a_fifo_update_runlist, | 437 | .update_runlist = gk20a_fifo_update_runlist, |
436 | .trigger_mmu_fault = NULL, | 438 | .trigger_mmu_fault = NULL, |
437 | .get_mmu_fault_info = NULL, | 439 | .get_mmu_fault_info = NULL, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index 664c0b80..dfebd60f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | |||
@@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) | |||
146 | { | 146 | { |
147 | return 0x00000001; | 147 | return 0x00000001; |
148 | } | 148 | } |
149 | static inline u32 ccsr_channel_force_ctx_reload_true_f(void) | ||
150 | { | ||
151 | return 0x100; | ||
152 | } | ||
149 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | 153 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) |
150 | { | 154 | { |
151 | return (v & 0x1) << 22; | 155 | return (v & 0x1) << 22; |
@@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) | |||
158 | { | 162 | { |
159 | return (v & 0x1) << 23; | 163 | return (v & 0x1) << 23; |
160 | } | 164 | } |
165 | static inline u32 ccsr_channel_eng_faulted_v(u32 r) | ||
166 | { | ||
167 | return (r >> 23) & 0x1; | ||
168 | } | ||
161 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) | 169 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) |
162 | { | 170 | { |
163 | return 0x800000; | 171 | return 0x800000; |
164 | } | 172 | } |
173 | static inline u32 ccsr_channel_eng_faulted_true_v(void) | ||
174 | { | ||
175 | return 0x00000001; | ||
176 | } | ||
165 | static inline u32 ccsr_channel_busy_v(u32 r) | 177 | static inline u32 ccsr_channel_busy_v(u32 r) |
166 | { | 178 | { |
167 | return (r >> 28) & 0x1; | 179 | return (r >> 28) & 0x1; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 7e30c34b..bd1e31c7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | |||
@@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) | |||
146 | { | 146 | { |
147 | return 0x00000001; | 147 | return 0x00000001; |
148 | } | 148 | } |
149 | static inline u32 ccsr_channel_force_ctx_reload_true_f(void) | ||
150 | { | ||
151 | return 0x100; | ||
152 | } | ||
149 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | 153 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) |
150 | { | 154 | { |
151 | return (v & 0x1) << 22; | 155 | return (v & 0x1) << 22; |
@@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) | |||
158 | { | 162 | { |
159 | return (v & 0x1) << 23; | 163 | return (v & 0x1) << 23; |
160 | } | 164 | } |
165 | static inline u32 ccsr_channel_eng_faulted_v(u32 r) | ||
166 | { | ||
167 | return (r >> 23) & 0x1; | ||
168 | } | ||
161 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) | 169 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) |
162 | { | 170 | { |
163 | return 0x800000; | 171 | return 0x800000; |
164 | } | 172 | } |
173 | static inline u32 ccsr_channel_eng_faulted_true_v(void) | ||
174 | { | ||
175 | return 0x00000001; | ||
176 | } | ||
165 | static inline u32 ccsr_channel_busy_v(u32 r) | 177 | static inline u32 ccsr_channel_busy_v(u32 r) |
166 | { | 178 | { |
167 | return (r >> 28) & 0x1; | 179 | return (r >> 28) & 0x1; |