diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-28 13:05:04 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-02 13:20:07 -0400 |
commit | f525ff15c4e8b5994201585ad584237b62bf3083 (patch) | |
tree | 9f9679c03dbd20e5efd2f603eedcdf563bf3dd87 | |
parent | c865b16337bf37959f6b7e8ff1970d8c3d3a927e (diff) |
gpu: nvgpu: gv11b: add ce interrupt handling
Added handling for below ce interrupts
-INVALID_CONFIG interrupt will be generated if a floorswept
PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG
registers. This is a fatal error and the LCE will have to be
reset to get back to a working state.
-MTHD_BUFFER_FAULT interrupt will be triggered if any access to
a method buffer during context load or save encounters a fault.
This is a fatal interrupt and will require at least the LCE to be reset
before operations can start again, if not the entire GPU.
JIRA GPUT19X-12
JIRA GPUT19X-46
Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1510298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 20 |
2 files changed, 59 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index efe443cc..1ba009bd 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c | |||
@@ -16,13 +16,52 @@ | |||
16 | * this program. | 16 | * this program. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include "nvgpu/log.h" | ||
20 | |||
19 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
20 | 22 | ||
21 | #include "gp10b/ce_gp10b.h" | 23 | #include "gp10b/ce_gp10b.h" |
22 | 24 | ||
23 | #include "ce_gv11b.h" | 25 | #include "ce_gv11b.h" |
24 | 26 | ||
27 | #include <nvgpu/hw/gv11b/hw_ce_gv11b.h> | ||
28 | |||
29 | static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
30 | { | ||
31 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | ||
32 | u32 clear_intr = 0; | ||
33 | |||
34 | nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id); | ||
35 | |||
36 | /* An INVALID_CONFIG interrupt will be generated if a floorswept | ||
37 | * PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG | ||
38 | * registers. This is a fatal error and the LCE will have to be | ||
39 | * reset to get back to a working state. | ||
40 | */ | ||
41 | if (ce_intr & ce_intr_status_invalid_config_pending_f()) { | ||
42 | nvgpu_log(g, gpu_dbg_intr, | ||
43 | "ce: inst %d: invalid config", inst_id); | ||
44 | clear_intr |= ce_intr_status_invalid_config_reset_f(); | ||
45 | } | ||
46 | |||
47 | /* A MTHD_BUFFER_FAULT interrupt will be triggered if any access | ||
48 | * to a method buffer during context load or save encounters a fault. | ||
49 | * This is a fatal interrupt and will require at least the LCE to be | ||
50 | * reset before operations can start again, if not the entire GPU. | ||
51 | */ | ||
52 | if (ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) { | ||
53 | nvgpu_log(g, gpu_dbg_intr, | ||
54 | "ce: inst %d: mthd buffer fault", inst_id); | ||
55 | clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f(); | ||
56 | } | ||
57 | |||
58 | gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); | ||
59 | |||
60 | gp10b_ce_isr(g, inst_id, pri_base); | ||
61 | } | ||
62 | |||
25 | void gv11b_init_ce(struct gpu_ops *gops) | 63 | void gv11b_init_ce(struct gpu_ops *gops) |
26 | { | 64 | { |
27 | gp10b_init_ce(gops); | 65 | gp10b_init_ce(gops); |
66 | gops->ce2.isr_stall = gv11b_ce_isr; | ||
28 | } | 67 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 9f279207..fbf10b82 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | |||
@@ -78,4 +78,24 @@ static inline u32 ce_intr_status_launcherr_reset_f(void) | |||
78 | { | 78 | { |
79 | return 0x4; | 79 | return 0x4; |
80 | } | 80 | } |
81 | static inline u32 ce_intr_status_invalid_config_pending_f(void) | ||
82 | { | ||
83 | return 0x8; | ||
84 | } | ||
85 | static inline u32 ce_intr_status_invalid_config_reset_f(void) | ||
86 | { | ||
87 | return 0x8; | ||
88 | } | ||
89 | static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) | ||
90 | { | ||
91 | return 0x10; | ||
92 | } | ||
93 | static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) | ||
94 | { | ||
95 | return 0x10; | ||
96 | } | ||
97 | static inline u32 ce_pce_map_r(void) | ||
98 | { | ||
99 | return 0x00104028; | ||
100 | } | ||
81 | #endif | 101 | #endif |