gpu: nvgpu: gv11b: update code to HW CL 36758735

Update headers and corresponding code to work with
HW CL # 36758735

Bug 1735760

Change-Id: Ie26bfaa6377ab797c5ad978e4796a55334761b5d
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1175882
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

18 files changed, 1097 insertions, 416 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index a23c5e8c..c5d2aa56 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -911,17 +911,6 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
                                 ctxsw_prog_main_image_magic_value_o()),
                 ctxsw_prog_main_image_magic_value_v_value_v());
 
-        gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n",
-                gk20a_mem_rd(g, mem,
-                                ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
-
-        gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n",
-                gk20a_mem_rd(g, mem,
-                                ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
-
-        gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n",
-                gk20a_mem_rd(g, mem,
-                                ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
 
         gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
                 gk20a_mem_rd(g, mem,
@@ -1144,8 +1133,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
         gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
                 gk20a_readl(g, gr_cwd_fs_r()));
         gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
-                gk20a_readl(g, gr_fe_tpc_fs_r(0)));
-        gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n",
+                gk20a_readl(g, gr_fe_tpc_fs_r()));
+        gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
                 gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
         gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
                 gk20a_readl(g, gr_cwd_sm_id_r(0)));
@@ -1552,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
                         gpc, tpc, global_esr);
 
         if (cilp_enabled && sm_debugger_attached) {
-                if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f())
-                        gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset,
-                                        gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f());
+                if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
+                        gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
+                                        gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
 
-                if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f())
-                        gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset,
-                                        gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f());
+                if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
+                        gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
+                                        gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
 
-                global_mask = gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f() |
-                        gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f();
+                global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
+                        gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
 
                 if (warp_esr != 0 || (global_esr & global_mask) != 0) {
                         *ignore_debugger = true;
@@ -1585,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
                         }
 
                         /* reset the HWW errors after locking down */
-                        global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset);
+                        global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
                         gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
                         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
                                         "CILP: HWWs cleared for gpc %d tpc %d\n",
@@ -1598,7 +1587,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
                                 return ret;
                         }
 
-                        dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset);
+                        dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
                         if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
                                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
                                                 "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
@@ -1606,7 +1595,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
                                 dbgr_control0 = set_field(dbgr_control0,
                                                 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
                                                 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
-                                gk20a_writel(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset, dbgr_control0);
+                                gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
                         }
 
                         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
@@ -1720,10 +1709,10 @@ clean_up:
 
 static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr)
 {
-        if (!(hww_warp_esr & gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m()))
+        if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
                 hww_warp_esr = set_field(hww_warp_esr,
-                        gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(),
-                        gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f());
+                        gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
+                        gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
 
         return hww_warp_esr;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
index b6efacf3..c06a106a 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
@@ -50,30 +50,6 @@
 #ifndef _hw_bus_gv11b_h_
 #define _hw_bus_gv11b_h_
 
-static inline u32 bus_bar0_window_r(void)
-{
-        return 0x00001700;
-}
-static inline u32 bus_bar0_window_base_f(u32 v)
-{
-        return (v & 0xffffff) << 0;
-}
-static inline u32 bus_bar0_window_target_vid_mem_f(void)
-{
-        return 0x0;
-}
-static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
-{
-        return 0x2000000;
-}
-static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
-{
-        return 0x3000000;
-}
-static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
-{
-        return 0x00000010;
-}
 static inline u32 bus_bar1_block_r(void)
 {
         return 0x00001704;
@@ -130,6 +106,58 @@ static inline u32 bus_bar2_block_ptr_shift_v(void)
 {
         return 0x0000000c;
 }
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8;
+}
 static inline u32 bus_intr_0_r(void)
 {
         return 0x00001100;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h
index 04055b8c..ed1e657c 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h
@@ -56,7 +56,7 @@ static inline u32 ccsr_channel_inst_r(u32 i)
 }
 static inline u32 ccsr_channel_inst__size_1_v(void)
 {
-        return 0x00001000;
+        return 0x00000200;
 }
 static inline u32 ccsr_channel_inst_ptr_f(u32 v)
 {
@@ -88,7 +88,7 @@ static inline u32 ccsr_channel_r(u32 i)
 }
 static inline u32 ccsr_channel__size_1_v(void)
 {
-        return 0x00001000;
+        return 0x00000200;
 }
 static inline u32 ccsr_channel_enable_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h
index 5c60c30c..57a6b28d 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h
@@ -290,168 +290,4 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_
 {
         return 0x2;
 }
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
-{
-        return 0x000000ac;
-}
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
-{
-        return (v & 0xffff) << 0;
-}
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
-{
-        return 0x000000b0;
-}
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
-{
-        return 0x1ffff << 0;
-}
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
-{
-        return 0x000000b4;
-}
-static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
-{
-        return (v & 0xffffffff) << 0;
-}
-static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
-{
-        return 0x00000080;
-}
-static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
-{
-        return 0x00000020;
-}
-static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
-{
-        return 0x00000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
-{
-        return 0x00000004;
-}
-static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
-{
-        return 0x600dbeef;
-}
-static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
-{
-        return 0x00000008;
-}
-static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
-{
-        return 0x0000000c;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
-{
-        return 0x00000018;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
-{
-        return 0x0000001c;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
-{
-        return (v & 0xffffff) << 0;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
-{
-        return (r >> 0) & 0xffffff;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
-{
-        return (v & 0xff) << 24;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
-{
-        return 0xff << 24;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
-{
-        return (r >> 24) & 0xff;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
-{
-        return 0x00000001;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
-{
-        return 0x1000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
-{
-        return 0x00000002;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
-{
-        return 0x2000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
-{
-        return 0x0000000a;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
-{
-        return 0xa000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
-{
-        return 0x0000000b;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
-{
-        return 0xb000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
-{
-        return 0x0000000c;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
-{
-        return 0xc000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
-{
-        return 0x0000000d;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
-{
-        return 0xd000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
-{
-        return 0x00000003;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
-{
-        return 0x3000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
-{
-        return 0x00000004;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
-{
-        return 0x4000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
-{
-        return 0x00000005;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
-{
-        return 0x5000000;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
-{
-        return 0x000000ff;
-}
-static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
-{
-        return 0xff000000;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
index 0a5622b4..900054aa 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
@@ -182,6 +182,10 @@ static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
 {
         return 0x20;
 }
+static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
+{
+        return 0x20;
+}
 static inline u32 fb_mmu_invalidate_sys_membar_s(void)
 {
         return 1;
@@ -470,4 +474,8 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
 {
         return 0x00000001;
 }
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
index 55960a4d..9c0f2483 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i)
 }
 static inline u32 fifo_eng_runlist_base__size_1_v(void)
 {
-        return 0x0000000d;
+        return 0x00000001;
 }
 static inline u32 fifo_eng_runlist_r(u32 i)
 {
@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i)
 }
 static inline u32 fifo_eng_runlist__size_1_v(void)
 {
-        return 0x0000000d;
+        return 0x00000001;
 }
 static inline u32 fifo_eng_runlist_length_f(u32 v)
 {
@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void)
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
 {
-        return 0x00000040;
+        return 0x00000000;
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
 {
@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
 }
 static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
 {
-        return 0x0000000e;
+        return 0x00000001;
 }
 static inline u32 fifo_intr_runlist_r(void)
 {
@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i)
 }
 static inline u32 fifo_engine_status__size_1_v(void)
 {
-        return 0x0000000f;
+        return 0x00000002;
 }
 static inline u32 fifo_engine_status_id_v(u32 r)
 {
@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i)
 }
 static inline u32 fifo_pbdma_status__size_1_v(void)
 {
-        return 0x0000000e;
+        return 0x00000001;
 }
 static inline u32 fifo_pbdma_status_id_v(u32 r)
 {
@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
 {
-        return (v & 0x3fff) << 0;
+        return (v & 0x1ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
 {
-        return 0x00002000;
+        return 0x000000c0;
 }
 static inline u32 fifo_replay_fault_buffer_get_r(void)
 {
@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
 {
-        return (v & 0x3fff) << 0;
+        return (v & 0x1ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
 {
@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
 {
-        return (v & 0x3fff) << 0;
+        return (v & 0x1ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h
index 75617e6e..280a048a 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h
@@ -124,7 +124,7 @@ static inline u32 fuse_status_opt_fbp_r(void)
 }
 static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
-        return (r >> (0 + i*0)) & 0x1;
+        return (r >> (0 + i*1)) & 0x1;
 }
 static inline u32 fuse_opt_ecc_en_r(void)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
index d54957eb..955626a6 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
@@ -70,9 +70,17 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
 {
         return 0x2;
 }
+static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
 static inline u32 gmmu_new_pde_address_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xffffff) << 8;
 }
 static inline u32 gmmu_new_pde_address_sys_w(void)
 {
@@ -118,6 +126,14 @@ static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
 {
         return 0x2;
 }
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
 static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
 {
         return (v & 0xfffffff) << 4;
@@ -138,6 +154,14 @@ static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
 {
         return 0x2;
 }
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
 static inline u32 gmmu_new_dual_pde_vol_small_w(void)
 {
         return 2;
@@ -164,7 +188,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xffffff) << 8;
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
 {
@@ -212,7 +236,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void)
 }
 static inline u32 gmmu_new_pte_address_sys_f(u32 v)
 {
-        return (v & 0xfffffff) << 8;
+        return (v & 0xffffff) << 8;
 }
 static inline u32 gmmu_new_pte_address_sys_w(void)
 {
@@ -238,6 +262,14 @@ static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
 {
         return 0x0;
 }
+static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
 static inline u32 gmmu_new_pte_read_only_w(void)
 {
         return 0;
@@ -1078,7 +1110,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
 {
         return 0x000000de;
 }
-static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
+static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
 {
         return 0x000000cc;
 }
@@ -1142,7 +1174,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
 {
         return 0x000000ec;
 }
-static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void)
+static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
 {
         return 0x000000cd;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
index 39b7074f..a37ce6e7 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
@@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
-        return 0x0050433c;
+        return 0x005046a4;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 {
-        return 0x00419b3c;
+        return 0x00419ea4;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
@@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
 {
-        return 0x00504358;
+        return 0x005046b8;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
 {
@@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
 {
-        return 0x0050436c;
+        return 0x005044a0;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
 {
@@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
 {
-        return 0x0050435c;
+        return 0x005046bc;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
 {
-        return 0x00504360;
+        return 0x005046c0;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
 {
-        return 0x00504370;
+        return 0x005044a4;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
 {
@@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
 }
 static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
 {
-        return 0x1800;
+        return 0x7fffffff;
 }
 static inline u32 gr_fe_object_table_r(u32 i)
 {
@@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r)
 {
         return (r >> 0) & 0xffff;
 }
-static inline u32 gr_fe_tpc_fs_r(u32 i)
+static inline u32 gr_fe_tpc_fs_r(void)
 {
-        return 0x0040a200 + i*4;
+        return 0x004041c4;
 }
 static inline u32 gr_pri_mme_shadow_raw_index_r(void)
 {
@@ -1530,9 +1530,29 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
         return 0x00502420;
 }
-static inline u32 gr_rstr2d_gpc_map_r(u32 i)
+static inline u32 gr_rstr2d_gpc_map0_r(void)
 {
-        return 0x0040780c + i*4;
+        return 0x0040780c;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781c;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820;
 }
 static inline u32 gr_rstr2d_map_table_cfg_r(void)
 {
@@ -1636,7 +1656,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
 }
 static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
 {
-        return 0x00001d80;
+        return 0x000001c0;
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
 {
@@ -1648,7 +1668,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
 {
-        return 0x00001d80;
+        return 0x00000182;
 }
 static inline u32 gr_pd_dist_skip_table_r(u32 i)
 {
@@ -2032,7 +2052,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
 {
-        return 0x00000030;
+        return 0x00000018;
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
 {
@@ -2146,10 +2166,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
 {
         return 0x00405b60 + i*4;
 }
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+        return 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
 {
         return (v & 0xf) << 0;
 }
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+        return 4;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+        return (v & 0xf) << 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
 {
         return (v & 0xf) << 8;
@@ -2158,6 +2190,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i)
 {
         return 0x00405ba0 + i*4;
 }
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+        return 0x00000010;
+}
 static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
 {
         return (v & 0xff) << 0;
@@ -2316,7 +2352,7 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
 {
-        return 0x00504608;
+        return 0x00504698;
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
 {
@@ -2328,7 +2364,7 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
 {
-        return 0x00504330;
+        return 0x0050469c;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
 {
@@ -2368,11 +2404,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
-        return 0x00000480;
+        return 0x00030000;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
 {
-        return 0x00000d10;
+        return 0x00030a00;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
 {
@@ -2416,11 +2452,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
 {
-        return 0x00000480;
+        return 0x00030000;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
 {
-        return 0x00419e00;
+        return 0x00419b00;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
 {
@@ -2428,7 +2464,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
 {
-        return 0x00419e04;
+        return 0x00419b04;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
 {
@@ -2672,11 +2708,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
 {
-        return 0x00000030;
+        return 0x00000018;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
 {
-        return 0x30;
+        return 0x18;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
 {
@@ -2712,7 +2748,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
 {
-        return 0x005001dc;
+        return 0x00500ee4;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
 {
@@ -2720,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
 {
-        return 0x00000de0;
+        return 0x00000250;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
 {
@@ -2728,7 +2764,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
 {
-        return 0x005001d8;
+        return 0x00500ee0;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
 {
@@ -2740,7 +2776,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
 {
-        return 0x004181e4;
+        return 0x00418eec;
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
 {
@@ -2834,33 +2870,173 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
 {
         return 0x80000000;
 }
-static inline u32 gr_crstr_gpc_map_r(u32 i)
+static inline u32 gr_crstr_gpc_map0_r(void)
 {
-        return 0x00418b08 + i*4;
+        return 0x00418b08;
 }
-static inline u32 gr_crstr_gpc_map_tile0_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
 {
-        return (v & 0x1f) << 0;
+        return (v & 0x7) << 0;
 }
-static inline u32 gr_crstr_gpc_map_tile1_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
 {
-        return (v & 0x1f) << 5;
+        return (v & 0x7) << 5;
 }
-static inline u32 gr_crstr_gpc_map_tile2_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
 {
-        return (v & 0x1f) << 10;
+        return (v & 0x7) << 10;
 }
-static inline u32 gr_crstr_gpc_map_tile3_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
 {
-        return (v & 0x1f) << 15;
+        return (v & 0x7) << 15;
 }
-static inline u32 gr_crstr_gpc_map_tile4_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
 {
-        return (v & 0x1f) << 20;
+        return (v & 0x7) << 20;
 }
-static inline u32 gr_crstr_gpc_map_tile5_f(u32 v)
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
 {
-        return (v & 0x1f) << 25;
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0c;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1c;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7) << 25;
 }
 static inline u32 gr_crstr_map_table_cfg_r(void)
 {
@@ -2874,39 +3050,159 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
 {
         return (v & 0xff) << 8;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
 {
-        return 0x00418980 + i*4;
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7) << 28;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7 << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28) & 0x7;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898c;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
 {
         return (v & 0x7) << 0;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
 {
         return (v & 0x7) << 4;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
 {
         return (v & 0x7) << 8;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
 {
         return (v & 0x7) << 12;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
 {
         return (v & 0x7) << 16;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
 {
         return (v & 0x7) << 20;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
 {
         return (v & 0x7) << 24;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
 {
         return (v & 0x7) << 28;
 }
@@ -2990,87 +3286,135 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
 {
         return 0x10000000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
 {
-        return 0x00419fa8;
+        return 0x00419e44;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_error_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
 {
         return 0x2;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
 {
         return 0x4;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
 {
         return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
 {
         return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
 {
         return 0x40;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
 {
         return 0x100;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
 {
         return 0x200;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
 {
         return 0x800;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_reg_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
 {
         return 0x2000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_addr_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
 {
         return 0x4000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
 {
         return 0x8000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
 {
         return 0x10000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
 {
         return 0x40000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
 {
         return 0x800000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
 {
         return 0x400000;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
 {
-        return 0x00419fac;
+        return 0x80000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4c;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
 {
         return 0x4;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_int_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
 {
         return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_pause_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
 {
         return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_single_step_complete_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
 {
         return 0x40;
 }
@@ -3138,118 +3482,190 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
         return 0x00000001;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_r(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
-        return 0x00504784;
+        return 0x00504610;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_m(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
 {
         return 0x1 << 0;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
         return (r >> 0) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_on_v(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
 {
         return 0x00000001;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_off_v(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
 {
         return 0x00000000;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_enable_f(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
         return 0x80000000;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_disable_f(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
         return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_enable_f(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
 {
         return 0x8;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_disable_f(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
 {
         return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_run_trigger_task_f(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
         return 0x40000000;
 }
-static inline u32 gr_gpc0_tpc0_sm1_warp_valid_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
 {
-        return 0x00504788;
+        return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
 {
-        return 0x00504790;
+        return 0x00504624;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_trap_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
 {
-        return 0x00504798;
+        return 0x00504634;
 }
-static inline u32 gr_gpcs_tpcs_sm1_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
 {
-        return 0x00419f90;
+        return 0x00419e24;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_r(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
-        return 0x00504780;
+        return 0x0050460c;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_sm_in_trap_mode_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
 {
         return (r >> 0) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
 {
         return (r >> 4) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_true_v(void)
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
 {
         return 0x00000001;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_r(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
 {
-        return 0x00419fb4;
+        return 0x00419e50;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_int_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
 {
         return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
 {
         return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_single_step_complete_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
 {
         return 0x40;
 }
-static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
         return 0x4;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_r(void)
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
 {
-        return 0x005047b4;
+        return 0x00504650;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
 {
         return 0x10;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_pause_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
 {
         return 0x20;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
 {
         return 0x40;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_multiple_warp_errors_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
         return 0x4;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000;
+}
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
 {
         return 0x00504224;
@@ -3266,45 +3682,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
         return 0x100;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_r(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
-        return 0x005047b0;
+        return 0x00504648;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
 {
         return (r >> 0) & 0xffff;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_v(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
 {
         return 0x00000000;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
 {
         return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
 {
         return 0x1 << 24;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
 {
         return 0x7 << 25;
 }
-static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f(void)
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
 {
         return 0x0;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
 {
-        return 0x005047b8;
+        return 0x00504654;
 }
 static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
 {
-        return 0x005043a0;
+        return 0x00504770;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 {
-        return 0x00419ba0;
+        return 0x00419f70;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
@@ -3316,11 +3732,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 }
 static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
 {
-        return 0x005043b0;
+        return 0x0050477c;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 {
-        return 0x00419bb0;
+        return 0x00419f7c;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
@@ -3338,9 +3754,29 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
 {
         return 0x4;
 }
-static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i)
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0c;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
 {
-        return 0x0041bf00 + i*4;
+        return 0x0041bf14;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
 {
@@ -3362,6 +3798,10 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
 {
         return (v & 0x7) << 21;
 }
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 24;
+}
 static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
 {
         return 0x0041bfd4;
@@ -3370,6 +3810,34 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
 {
         return (v & 0xffffff) << 0;
 }
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 5;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 10;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 15;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 20;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 25;
+}
 static inline u32 gr_bes_zrop_settings_r(void)
 {
         return 0x00408850;
@@ -3416,75 +3884,107 @@ static inline u32 gr_zcull_subregion_qty_v(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
 {
-        return 0x00504308;
+        return 0x00504604;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
 {
-        return 0x0050430c;
+        return 0x00504608;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
 {
-        return 0x00504318;
+        return 0x0050465c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
 {
-        return 0x00504320;
+        return 0x00504660;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
 {
-        return 0x00504324;
+        return 0x00504664;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
 {
-        return 0x00504328;
+        return 0x00504668;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
 {
-        return 0x0050432c;
+        return 0x0050466c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
 {
-        return 0x0050431c;
+        return 0x00504658;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
 {
-        return 0x00504378;
+        return 0x00504730;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
 {
-        return 0x0050437c;
+        return 0x00504734;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
 {
-        return 0x00504380;
+        return 0x00504738;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
 {
-        return 0x00504384;
+        return 0x0050473c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
 {
-        return 0x00504388;
+        return 0x00504740;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
 {
-        return 0x0050438c;
+        return 0x00504744;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
 {
-        return 0x00504390;
+        return 0x00504748;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
 {
-        return 0x00504394;
+        return 0x0050474c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00504678;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694;
 }
-static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status_s1_r(void)
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
 {
-        return 0x005047c4;
+        return 0x005046f0;
 }
-static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status1_r(void)
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
 {
-        return 0x005047d0;
+        return 0x00504700;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+        return 0x005046f4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00504704;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+        return 0x005046f8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+        return 0x00504708;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+        return 0x005046fc;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+        return 0x0050470c;
 }
 static inline u32 gr_fe_pwr_mode_r(void)
 {
@@ -3584,7 +4084,7 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
 {
-        return 0x00419f84;
+        return 0x00419e10;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
 {
@@ -3648,7 +4148,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
 {
-        return 0x00419bd8;
+        return 0x00419c84;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 {
@@ -3664,7 +4164,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
 {
-        return 0x00419ba4;
+        return 0x00419f78;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
 {
@@ -3680,10 +4180,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void)
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
 {
-        return (v & 0x1ff) << 0;
+        return (v & 0xff) << 0;
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
 {
-        return 0x1ff << 0;
+        return 0xff << 0;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
index 02db6af6..2dbd759f 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
@@ -50,6 +50,26 @@
 #ifndef _hw_ltc_gv11b_h_
 #define _hw_ltc_gv11b_h_
 
+static inline u32 ltc_pltcg_base_v(void)
+{
+        return 0x00140000;
+}
+static inline u32 ltc_pltcg_extent_v(void)
+{
+        return 0x0017ffff;
+}
+static inline u32 ltc_ltc0_ltss_v(void)
+{
+        return 0x00140200;
+}
+static inline u32 ltc_ltc0_lts0_v(void)
+{
+        return 0x00140400;
+}
+static inline u32 ltc_ltcs_ltss_v(void)
+{
+        return 0x0017e200;
+}
 static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
 {
         return 0x0014046c;
@@ -550,4 +570,12 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
 {
         return (r >> 16) & 0x1f;
 }
+static inline u32 ltc_ltca_g_axi_pctrl_r(void)
+{
+        return 0x00160000;
+}
+static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
+{
+        return (v & 0xff) << 2;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h
index 98bec43a..7fe4d158 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h
@@ -78,10 +78,6 @@ static inline u32 mc_intr_pfifo_pending_f(void)
 {
         return 0x100;
 }
-static inline u32 mc_intr_hub_pending_f(void)
-{
-        return 0x200;
-}
 static inline u32 mc_intr_pgraph_pending_f(void)
 {
         return 0x1000;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
index 3863c6d6..b3aaa7e6 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i)
 }
 static inline u32 pbdma_gp_base__size_1_v(void)
 {
-        return 0x0000000e;
+        return 0x00000001;
 }
 static inline u32 pbdma_gp_base_offset_f(u32 v)
 {
@@ -334,6 +334,38 @@ static inline u32 pbdma_userd_addr_f(u32 v)
 {
         return (v & 0x7fffff) << 9;
 }
+static inline u32 pbdma_config_r(u32 i)
+{
+        return 0x000400f4 + i*8192;
+}
+static inline u32 pbdma_config_l2_evict_first_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_config_l2_evict_normal_f(void)
+{
+        return 0x1;
+}
+static inline u32 pbdma_config_l2_evict_last_f(void)
+{
+        return 0x2;
+}
+static inline u32 pbdma_config_ce_split_enable_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_config_ce_split_disable_f(void)
+{
+        return 0x10;
+}
+static inline u32 pbdma_config_auth_level_non_privileged_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+        return 0x100;
+}
 static inline u32 pbdma_userd_hi_r(u32 i)
 {
         return 0x0004000c + i*8192;
@@ -478,6 +510,14 @@ static inline u32 pbdma_intr_0_signature_pending_f(void)
 {
         return 0x80000000;
 }
+static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148 + i*8192;
+}
 static inline u32 pbdma_intr_en_0_r(u32 i)
 {
         return 0x0004010c + i*8192;
@@ -526,6 +566,38 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
 {
         return (v & 0x7fff) << 0;
 }
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4 + i*8192;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8 + i*8192;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8) & 0xfff;
+}
 static inline u32 pbdma_runlist_timeslice_r(u32 i)
 {
         return 0x000400f8 + i*8192;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
index 836c014b..4d11fef4 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
@@ -52,7 +52,7 @@
 
 static inline u32 perf_pmasys_control_r(void)
 {
-        return 0x0024a000;
+        return 0x001b4000;
 }
 static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
 {
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
 }
 static inline u32 perf_pmasys_mem_block_r(void)
 {
-        return 0x0024a070;
+        return 0x001b4070;
 }
 static inline u32 perf_pmasys_mem_block_base_f(u32 v)
 {
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void)
 }
 static inline u32 perf_pmasys_outbase_r(void)
 {
-        return 0x0024a074;
+        return 0x001b4074;
 }
 static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
 {
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
 }
 static inline u32 perf_pmasys_outbaseupper_r(void)
 {
-        return 0x0024a078;
+        return 0x001b4078;
 }
 static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
 {
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
 }
 static inline u32 perf_pmasys_outsize_r(void)
 {
-        return 0x0024a07c;
+        return 0x001b407c;
 }
 static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
 {
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_mem_bytes_r(void)
 {
-        return 0x0024a084;
+        return 0x001b4084;
 }
 static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
 {
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_mem_bump_r(void)
 {
-        return 0x0024a088;
+        return 0x001b4088;
 }
 static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
 {
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_enginestatus_r(void)
 {
-        return 0x0024a0a4;
+        return 0x001b40a4;
 }
 static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
index f107300e..e08c6854 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
@@ -70,6 +70,10 @@ static inline u32 proj_lts_stride_v(void)
 {
         return 0x00000200;
 }
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00004000;
+}
 static inline u32 proj_ppc_in_gpc_base_v(void)
 {
         return 0x00003000;
@@ -102,29 +106,37 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
 {
         return 0x00001800;
 }
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000002;
+}
 static inline u32 proj_host_num_pbdma_v(void)
 {
-        return 0x0000000e;
+        return 0x00000001;
 }
 static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
 {
-        return 0x00000007;
+        return 0x00000002;
 }
 static inline u32 proj_scal_litter_num_fbps_v(void)
 {
-        return 0x00000008;
+        return 0x00000001;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000001;
 }
 static inline u32 proj_scal_litter_num_gpcs_v(void)
 {
-        return 0x00000008;
+        return 0x00000001;
 }
 static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
 {
-        return 0x00000003;
+        return 0x00000001;
 }
 static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
 {
-        return 0x00000003;
+        return 0x00000002;
 }
 static inline u32 proj_scal_litter_num_zcull_banks_v(void)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
index bb8b5dea..27ea4246 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
@@ -542,6 +542,10 @@ static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
 {
         return 0x20000000;
 }
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000;
+}
 static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
 {
         return (v & 0x1) << 30;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
index a19e5251..6ccbc266 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void)
 }
 static inline u32 ram_in_page_dir_base_hi_f(u32 v)
 {
-        return (v & 0xffffffff) << 0;
+        return (v & 0xff) << 0;
 }
 static inline u32 ram_in_page_dir_base_hi_w(void)
 {
@@ -354,6 +354,14 @@ static inline u32 ram_fc_allowed_syncpoints_w(void)
 {
         return 58;
 }
+static inline u32 ram_fc_syncpointa_w(void)
+{
+        return 41;
+}
+static inline u32 ram_fc_syncpointb_w(void)
+{
+        return 42;
+}
 static inline u32 ram_fc_target_w(void)
 {
         return 43;
@@ -436,7 +444,11 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void)
 }
 static inline u32 ram_rl_entry_size_v(void)
 {
-        return 0x00000010;
+        return 0x00000008;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfff) << 0;
 }
 static inline u32 ram_rl_entry_id_f(u32 v)
 {
@@ -444,14 +456,34 @@ static inline u32 ram_rl_entry_id_f(u32 v)
 }
 static inline u32 ram_rl_entry_type_f(u32 v)
 {
-        return (v & 0x1) << 0;
+        return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0;
 }
 static inline u32 ram_rl_entry_type_tsg_f(void)
 {
-        return 0x1;
+        return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000;
 }
 static inline u32 ram_rl_entry_tsg_length_f(u32 v)
 {
-        return (v & 0xff) << 0;
+        return (v & 0x3f) << 26;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
index ee3dbc0e..2c464d2c 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
@@ -54,6 +54,114 @@ static inline u32 therm_use_a_r(void)
 {
         return 0x00020798;
 }
+static inline u32 therm_use_a_ext_therm_0_enable_f(void)
+{
+        return 0x1;
+}
+static inline u32 therm_use_a_ext_therm_1_enable_f(void)
+{
+        return 0x2;
+}
+static inline u32 therm_use_a_ext_therm_2_enable_f(void)
+{
+        return 0x4;
+}
+static inline u32 therm_evt_ext_therm_0_r(void)
+{
+        return 0x00020700;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
+{
+        return (v & 0x3f) << 24;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
+{
+        return (v & 0x3) << 30;
+}
+static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 therm_evt_ext_therm_1_r(void)
+{
+        return 0x00020704;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
+{
+        return (v & 0x3f) << 24;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
+{
+        return (v & 0x3) << 30;
+}
+static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 therm_evt_ext_therm_2_r(void)
+{
+        return 0x00020708;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
+{
+        return (v & 0x3f) << 24;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
+{
+        return (v & 0x3) << 30;
+}
+static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
+{
+        return 0x00000003;
+}
 static inline u32 therm_weight_1_r(void)
 {
         return 0x00020024;
@@ -106,6 +214,22 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
 {
         return 0x4;
 }
+static inline u32 therm_gate_ctrl_eng_pwr_m(void)
+{
+        return 0x3 << 4;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
+{
+        return 0x10;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
+{
+        return 0x20;
+}
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
 {
         return (v & 0x1f) << 8;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
index 65ffebb0..cb65cad8 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
@@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void)
 {
         return 0x0;
 }
-static inline u32 top_device_info_type_enum_copy0_v(void)
+static inline u32 top_device_info_type_enum_copy2_v(void)
 {
-        return 0x00000001;
+        return 0x00000003;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xc;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+        return 0x00000013;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+        return 0x4c;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5) & 0x1;
 }
-static inline u32 top_device_info_type_enum_copy0_f(void)
+static inline u32 top_device_info_runlist_v(u32 r)
 {
-        return 0x4;
+        return (r >> 4) & 0x1;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2) & 0x1;
 }
 static inline u32 top_device_info_entry_v(u32 r)
 {
@@ -158,10 +182,6 @@ static inline u32 top_device_info_entry_enum_v(void)
 {
         return 0x00000002;
 }
-static inline u32 top_device_info_entry_engine_type_v(void)
-{
-        return 0x00000002;
-}
 static inline u32 top_device_info_entry_data_v(void)
 {
         return 0x00000001;