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authorVijayakumar <vsubbu@nvidia.com>2018-03-04 23:45:34 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-30 17:53:45 -0400
commitf07b2df173d9bde832c5bf7d7f3b498b533dcb22 (patch)
treea71d73bb320189c335a835fef2db5944d9e800d6
parent0d97b549892be7b91d4497f055c62e681e12a075 (diff)
gpu: nvgpu: gv100: set sched err and ctxsw_timeout hals
gv100 does not have new fifo ctxsw timeout interrupt that is present on gv11b. Use non gv11b sched error and ctxsw timeout handlers. Bug 2069807 Change-Id: I9dc2b8d9212145d7a1b0fef656aa20d2f073ea13 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1668401 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index e2fcbf08..0dcfb064 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -503,7 +503,7 @@ static const struct gpu_ops gv100_ops = {
503 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, 503 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
504 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, 504 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
505 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, 505 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
506 .handle_sched_error = gv11b_fifo_handle_sched_error, 506 .handle_sched_error = gk20a_fifo_handle_sched_error,
507 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, 507 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
508 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, 508 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
509 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, 509 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
@@ -534,7 +534,6 @@ static const struct gpu_ops gv100_ops = {
534 .device_info_fault_id = top_device_info_data_fault_id_enum_v, 534 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
535 .free_channel_ctx_header = gv11b_free_subctx_header, 535 .free_channel_ctx_header = gv11b_free_subctx_header,
536 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, 536 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
537 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
538 .apply_ctxsw_timeout_intr = gv100_apply_ctxsw_timeout_intr, 537 .apply_ctxsw_timeout_intr = gv100_apply_ctxsw_timeout_intr,
539 }, 538 },
540 .gr_ctx = { 539 .gr_ctx = {