diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-02-06 18:57:12 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-07 18:16:53 -0500 |
commit | f04a84b7ce976e911bf81497796016e149d17082 (patch) | |
tree | efc265ce2726409bdf9e6888e428858222e7d118 | |
parent | cabba6686643dbb4bd8a023ad4622a49114b5159 (diff) |
gpu: nvgpu: gv11b: chip specific init_elcg_mode
Added thermal registers for gv11b. Implemented chip specific
init_elcg_mode. In thermal control register, engine power auto
control config is removed and added new field for engine holdoff
enable signal.
JIRA GV11B-58
Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1300119
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 354 |
2 files changed, 388 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index daadef68..3c332bbf 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | 41 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> |
42 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 42 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
43 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> | 43 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> |
44 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> | ||
44 | 45 | ||
45 | static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | 46 | static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) |
46 | { | 47 | { |
@@ -1970,6 +1971,39 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, | |||
1970 | ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); | 1971 | ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); |
1971 | } | 1972 | } |
1972 | 1973 | ||
1974 | void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | ||
1975 | { | ||
1976 | u32 gate_ctrl; | ||
1977 | |||
1978 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | ||
1979 | |||
1980 | switch (mode) { | ||
1981 | case ELCG_RUN: | ||
1982 | gate_ctrl = set_field(gate_ctrl, | ||
1983 | therm_gate_ctrl_eng_clk_m(), | ||
1984 | therm_gate_ctrl_eng_clk_run_f()); | ||
1985 | gate_ctrl = set_field(gate_ctrl, | ||
1986 | therm_gate_ctrl_idle_holdoff_m(), | ||
1987 | therm_gate_ctrl_idle_holdoff_on_f()); | ||
1988 | break; | ||
1989 | case ELCG_STOP: | ||
1990 | gate_ctrl = set_field(gate_ctrl, | ||
1991 | therm_gate_ctrl_eng_clk_m(), | ||
1992 | therm_gate_ctrl_eng_clk_stop_f()); | ||
1993 | break; | ||
1994 | case ELCG_AUTO: | ||
1995 | gate_ctrl = set_field(gate_ctrl, | ||
1996 | therm_gate_ctrl_eng_clk_m(), | ||
1997 | therm_gate_ctrl_eng_clk_auto_f()); | ||
1998 | break; | ||
1999 | default: | ||
2000 | gk20a_err(dev_from_gk20a(g), | ||
2001 | "invalid elcg mode %d", mode); | ||
2002 | } | ||
2003 | |||
2004 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | ||
2005 | } | ||
2006 | |||
1973 | void gv11b_init_gr(struct gpu_ops *gops) | 2007 | void gv11b_init_gr(struct gpu_ops *gops) |
1974 | { | 2008 | { |
1975 | gp10b_init_gr(gops); | 2009 | gp10b_init_gr(gops); |
@@ -2025,5 +2059,6 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2025 | gops->gr.restore_context_header = gv11b_restore_context_header; | 2059 | gops->gr.restore_context_header = gv11b_restore_context_header; |
2026 | gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; | 2060 | gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; |
2027 | gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; | 2061 | gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; |
2062 | gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; | ||
2028 | 2063 | ||
2029 | } | 2064 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index a3cfcf91..7be6d074 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -50,4 +50,356 @@ | |||
50 | #ifndef _hw_therm_gv11b_h_ | 50 | #ifndef _hw_therm_gv11b_h_ |
51 | #define _hw_therm_gv11b_h_ | 51 | #define _hw_therm_gv11b_h_ |
52 | 52 | ||
53 | static inline u32 therm_use_a_r(void) | ||
54 | { | ||
55 | return 0x00020798; | ||
56 | } | ||
57 | static inline u32 therm_use_a_ext_therm_0_enable_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 therm_use_a_ext_therm_1_enable_f(void) | ||
62 | { | ||
63 | return 0x2; | ||
64 | } | ||
65 | static inline u32 therm_use_a_ext_therm_2_enable_f(void) | ||
66 | { | ||
67 | return 0x4; | ||
68 | } | ||
69 | static inline u32 therm_evt_ext_therm_0_r(void) | ||
70 | { | ||
71 | return 0x00020700; | ||
72 | } | ||
73 | static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) | ||
74 | { | ||
75 | return (v & 0x3f) << 24; | ||
76 | } | ||
77 | static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) | ||
82 | { | ||
83 | return (v & 0x3) << 30; | ||
84 | } | ||
85 | static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) | ||
86 | { | ||
87 | return 0x00000000; | ||
88 | } | ||
89 | static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) | ||
90 | { | ||
91 | return 0x00000001; | ||
92 | } | ||
93 | static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) | ||
94 | { | ||
95 | return 0x00000002; | ||
96 | } | ||
97 | static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) | ||
98 | { | ||
99 | return 0x00000003; | ||
100 | } | ||
101 | static inline u32 therm_evt_ext_therm_1_r(void) | ||
102 | { | ||
103 | return 0x00020704; | ||
104 | } | ||
105 | static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x3f) << 24; | ||
108 | } | ||
109 | static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) | ||
114 | { | ||
115 | return (v & 0x3) << 30; | ||
116 | } | ||
117 | static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) | ||
118 | { | ||
119 | return 0x00000000; | ||
120 | } | ||
121 | static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) | ||
122 | { | ||
123 | return 0x00000001; | ||
124 | } | ||
125 | static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) | ||
126 | { | ||
127 | return 0x00000002; | ||
128 | } | ||
129 | static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) | ||
130 | { | ||
131 | return 0x00000003; | ||
132 | } | ||
133 | static inline u32 therm_evt_ext_therm_2_r(void) | ||
134 | { | ||
135 | return 0x00020708; | ||
136 | } | ||
137 | static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x3f) << 24; | ||
140 | } | ||
141 | static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) | ||
142 | { | ||
143 | return 0x00000003; | ||
144 | } | ||
145 | static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x3) << 30; | ||
148 | } | ||
149 | static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) | ||
150 | { | ||
151 | return 0x00000000; | ||
152 | } | ||
153 | static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) | ||
154 | { | ||
155 | return 0x00000001; | ||
156 | } | ||
157 | static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) | ||
158 | { | ||
159 | return 0x00000002; | ||
160 | } | ||
161 | static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) | ||
162 | { | ||
163 | return 0x00000003; | ||
164 | } | ||
165 | static inline u32 therm_weight_1_r(void) | ||
166 | { | ||
167 | return 0x00020024; | ||
168 | } | ||
169 | static inline u32 therm_config1_r(void) | ||
170 | { | ||
171 | return 0x00020050; | ||
172 | } | ||
173 | static inline u32 therm_config2_r(void) | ||
174 | { | ||
175 | return 0x00020130; | ||
176 | } | ||
177 | static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) | ||
178 | { | ||
179 | return (v & 0x1) << 24; | ||
180 | } | ||
181 | static inline u32 therm_config2_grad_enable_f(u32 v) | ||
182 | { | ||
183 | return (v & 0x1) << 31; | ||
184 | } | ||
185 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
186 | { | ||
187 | return 0x00020200 + i*4; | ||
188 | } | ||
189 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
190 | { | ||
191 | return 0x3 << 0; | ||
192 | } | ||
193 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
194 | { | ||
195 | return 0x0; | ||
196 | } | ||
197 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
198 | { | ||
199 | return 0x1; | ||
200 | } | ||
201 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
202 | { | ||
203 | return 0x2; | ||
204 | } | ||
205 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
206 | { | ||
207 | return 0x3 << 2; | ||
208 | } | ||
209 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
210 | { | ||
211 | return 0x0; | ||
212 | } | ||
213 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
214 | { | ||
215 | return 0x4; | ||
216 | } | ||
217 | static inline u32 therm_gate_ctrl_idle_holdoff_m(void) | ||
218 | { | ||
219 | return 0x1 << 4; | ||
220 | } | ||
221 | static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) | ||
222 | { | ||
223 | return 0x0; | ||
224 | } | ||
225 | static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) | ||
226 | { | ||
227 | return 0x10; | ||
228 | } | ||
229 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
230 | { | ||
231 | return (v & 0x1f) << 8; | ||
232 | } | ||
233 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
234 | { | ||
235 | return 0x1f << 8; | ||
236 | } | ||
237 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
238 | { | ||
239 | return (v & 0x7) << 13; | ||
240 | } | ||
241 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
242 | { | ||
243 | return 0x7 << 13; | ||
244 | } | ||
245 | static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) | ||
246 | { | ||
247 | return (v & 0xf) << 16; | ||
248 | } | ||
249 | static inline u32 therm_gate_ctrl_eng_delay_before_m(void) | ||
250 | { | ||
251 | return 0xf << 16; | ||
252 | } | ||
253 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
254 | { | ||
255 | return (v & 0xf) << 20; | ||
256 | } | ||
257 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
258 | { | ||
259 | return 0xf << 20; | ||
260 | } | ||
261 | static inline u32 therm_fecs_idle_filter_r(void) | ||
262 | { | ||
263 | return 0x00020288; | ||
264 | } | ||
265 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
266 | { | ||
267 | return 0xffffffff << 0; | ||
268 | } | ||
269 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
270 | { | ||
271 | return 0x0002028c; | ||
272 | } | ||
273 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
274 | { | ||
275 | return 0xffffffff << 0; | ||
276 | } | ||
277 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
278 | { | ||
279 | return 0x00020160 + i*4; | ||
280 | } | ||
281 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
282 | { | ||
283 | return (v & 0x3f) << 16; | ||
284 | } | ||
285 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
286 | { | ||
287 | return 0x3f << 16; | ||
288 | } | ||
289 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
290 | { | ||
291 | return (r >> 16) & 0x3f; | ||
292 | } | ||
293 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
294 | { | ||
295 | return 0x0; | ||
296 | } | ||
297 | static inline u32 therm_grad_stepping_table_r(u32 i) | ||
298 | { | ||
299 | return 0x000202c8 + i*4; | ||
300 | } | ||
301 | static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) | ||
302 | { | ||
303 | return (v & 0x3f) << 0; | ||
304 | } | ||
305 | static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) | ||
306 | { | ||
307 | return 0x3f << 0; | ||
308 | } | ||
309 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) | ||
310 | { | ||
311 | return 0x1; | ||
312 | } | ||
313 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) | ||
314 | { | ||
315 | return 0x2; | ||
316 | } | ||
317 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) | ||
318 | { | ||
319 | return 0x6; | ||
320 | } | ||
321 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) | ||
322 | { | ||
323 | return 0xe; | ||
324 | } | ||
325 | static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) | ||
326 | { | ||
327 | return (v & 0x3f) << 6; | ||
328 | } | ||
329 | static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) | ||
330 | { | ||
331 | return 0x3f << 6; | ||
332 | } | ||
333 | static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) | ||
334 | { | ||
335 | return (v & 0x3f) << 12; | ||
336 | } | ||
337 | static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) | ||
338 | { | ||
339 | return 0x3f << 12; | ||
340 | } | ||
341 | static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) | ||
342 | { | ||
343 | return (v & 0x3f) << 18; | ||
344 | } | ||
345 | static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) | ||
346 | { | ||
347 | return 0x3f << 18; | ||
348 | } | ||
349 | static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) | ||
350 | { | ||
351 | return (v & 0x3f) << 24; | ||
352 | } | ||
353 | static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) | ||
354 | { | ||
355 | return 0x3f << 24; | ||
356 | } | ||
357 | static inline u32 therm_grad_stepping0_r(void) | ||
358 | { | ||
359 | return 0x000202c0; | ||
360 | } | ||
361 | static inline u32 therm_grad_stepping0_feature_s(void) | ||
362 | { | ||
363 | return 1; | ||
364 | } | ||
365 | static inline u32 therm_grad_stepping0_feature_f(u32 v) | ||
366 | { | ||
367 | return (v & 0x1) << 0; | ||
368 | } | ||
369 | static inline u32 therm_grad_stepping0_feature_m(void) | ||
370 | { | ||
371 | return 0x1 << 0; | ||
372 | } | ||
373 | static inline u32 therm_grad_stepping0_feature_v(u32 r) | ||
374 | { | ||
375 | return (r >> 0) & 0x1; | ||
376 | } | ||
377 | static inline u32 therm_grad_stepping0_feature_enable_f(void) | ||
378 | { | ||
379 | return 0x1; | ||
380 | } | ||
381 | static inline u32 therm_grad_stepping1_r(void) | ||
382 | { | ||
383 | return 0x000202c4; | ||
384 | } | ||
385 | static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) | ||
386 | { | ||
387 | return (v & 0x1ffff) << 0; | ||
388 | } | ||
389 | static inline u32 therm_clk_timing_r(u32 i) | ||
390 | { | ||
391 | return 0x000203c0 + i*4; | ||
392 | } | ||
393 | static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) | ||
394 | { | ||
395 | return (v & 0x1) << 16; | ||
396 | } | ||
397 | static inline u32 therm_clk_timing_grad_slowdown_m(void) | ||
398 | { | ||
399 | return 0x1 << 16; | ||
400 | } | ||
401 | static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) | ||
402 | { | ||
403 | return 0x10000; | ||
404 | } | ||
53 | #endif | 405 | #endif |